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/wasmtime-44.0.1/cranelift/codegen/src/isa/s390x/inst/
H A Dimms.rs81 pub shift: u8, field
95 shift: 0, in maybe_from_u64()
101 shift: 1, in maybe_from_u64()
107 shift: 2, in maybe_from_u64()
113 shift: 3, in maybe_from_u64()
126 shift: shift_enc, in maybe_with_shift()
134 shift: self.shift, in negate_bits()
145 pub shift: u8, field
157 shift: 0, in maybe_from_u64()
163 shift: 1, in maybe_from_u64()
[all …]
/wasmtime-44.0.1/cranelift/isle/veri/veri_engine/examples/broken/isub/
H A Dbroken_shift.isle13 ;; the two msb encode the type of shift as follows:
18 ;; the rest will encode a 8-bit shift amount
60 (spec (sub_shift ty a b shift)
63 (conv_to 64 (bvsub (extract 31 0 a) (switch (extract 15 8 shift)
64 …Lsr) (bvshl (extract 31 0 b) (zero_ext 32 (bvand (bvsub (int2bv 8 ty) #x01) (extract 7 0 shift)))))
65 …sl) (bvlshr (extract 31 0 b) (zero_ext 32 (bvand (bvsub (int2bv 8 ty) #x01) (extract 7 0 shift)))))
66 … (bvashr (extract 31 0 b) (zero_ext 32 (bvand (bvsub (int2bv 8 ty) #x01) (extract 7 0 shift))))))))
67 (bvsub a (switch (extract 15 8 shift)
68 ((ALUOp.Lsr) (bvshl b (zero_ext 64 (bvand (bvsub (int2bv 8 ty) #x01) (extract 7 0 shift)))))
69 … ((ALUOp.Lsl) (bvlshr b (zero_ext 64 (bvand (bvsub (int2bv 8 ty) #x01) (extract 7 0 shift)))))
[all …]
/wasmtime-44.0.1/cranelift/isle/veri/veri_engine/examples/broken/iadd/
H A Dbroken_shift.isle13 ;; the two msb encode the type of shift as follows:
18 ;; the rest will encode a 8-bit shift amount
59 (spec (add_shift ty a b shift)
63 (switch (extract 15 8 shift)
64 …Lsr) (bvshl (extract 31 0 b) (zero_ext 32 (bvand (bvsub (int2bv 8 ty) #x01) (extract 7 0 shift)))))
65 …sl) (bvlshr (extract 31 0 b) (zero_ext 32 (bvand (bvsub (int2bv 8 ty) #x01) (extract 7 0 shift)))))
66 … (bvashr (extract 31 0 b) (zero_ext 32 (bvand (bvsub (int2bv 8 ty) #x01) (extract 7 0 shift))))))))
68 (switch (extract 15 8 shift)
69 ((ALUOp.Lsr) (bvshl b (zero_ext 64 (bvand (bvsub (int2bv 8 ty) #x01) (extract 7 0 shift)))))
70 … ((ALUOp.Lsl) (bvlshr b (zero_ext 64 (bvand (bvsub (int2bv 8 ty) #x01) (extract 7 0 shift)))))
[all …]
H A Dbroken_shift2.isle13 ;; the two msb encode the type of shift as follows:
18 ;; the rest will encode a 8-bit shift amount
58 (spec (add_shift ty a b shift)
62 (switch (extract 15 8 shift)
63 …Lsl) (bvshl (extract 31 0 b) (zero_ext 32 (bvand (bvsub (int2bv 8 ty) #x01) (extract 7 0 shift)))))
64 …sr) (bvlshr (extract 31 0 b) (zero_ext 32 (bvand (bvsub (int2bv 8 ty) #x01) (extract 7 0 shift)))))
65 … (bvashr (extract 31 0 b) (zero_ext 32 (bvand (bvsub (int2bv 8 ty) #x01) (extract 7 0 shift))))))))
67 (switch (extract 15 8 shift)
68 ((ALUOp.Lsl) (bvshl b (zero_ext 64 (bvand (bvsub (int2bv 8 ty) #x01) (extract 7 0 shift)))))
69 … ((ALUOp.Lsr) (bvlshr b (zero_ext 64 (bvand (bvsub (int2bv 8 ty) #x01) (extract 7 0 shift)))))
[all …]
/wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/inst/
H A Dimms.rs567 pub shift: u8, field
581 shift: 0, in maybe_from_u64()
587 shift: 1, in maybe_from_u64()
593 shift: 2, in maybe_from_u64()
599 shift: 3, in maybe_from_u64()
628 shift: u8, field
642 shift: 0, in maybe_from_u64()
722 shift: 0, in maybe_from_u64()
735 shift: 0, in zero()
918 if self.shift == 0 { in pretty_print()
[all …]
H A Dargs.rs39 pub fn maybe_from_shift(shift: u64) -> Option<ShiftOpShiftImm> { in maybe_from_shift()
40 if shift <= Self::MAX_SHIFT { in maybe_from_shift()
41 Some(ShiftOpShiftImm(shift as u8)) in maybe_from_shift()
64 shift: ShiftOpShiftImm, field
69 pub fn new(op: ShiftOp, shift: ShiftOpShiftImm) -> ShiftOpAndAmt { in new()
70 ShiftOpAndAmt { op, shift } in new()
80 self.shift in amt()
364 let shift = shift_for_type(size_bytes); in pretty_print() localVariable
368 let shift = shift_for_type(size_bytes); in pretty_print() localVariable
H A Demit.rs210 assert!(imm.shift <= 0b11); in enc_move_wide()
218 | u32::from(imm.shift) << 21 in enc_move_wide()
225 assert!(imm.shift <= 0b11); in enc_movk()
228 | u32::from(imm.shift) << 21 in enc_movk()
2412 assert_eq!(shift, 0); in emit()
2417 let s = shift & 8; in emit()
2420 assert_eq!(s, shift); in emit()
2426 assert!(shift == 8 || shift == 16); in emit()
2430 let s = shift & 24; in emit()
2439 assert_eq!(shift, 0); in emit()
[all …]
/wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/lower/
H A Disle.rs302 let shift = 32 - bits; in load_constant_full() localVariable
308 ((value << shift) >> shift) as u32 as u64 in load_constant_full()
314 let shift = 64 - bits; in load_constant_full() localVariable
317 ((value << shift) >> shift) as u64 in load_constant_full()
325 fn get(value: u64, shift: u8) -> u16 { in load_constant_full()
326 (value >> (shift * 16)) as u16 in load_constant_full()
329 let offset = shift * 16; in load_constant_full()
384 shift: first, in load_constant_full()
392 let bits = get(value, shift); in load_constant_full()
726 shift in fpu_op_ri_ushr()
[all …]
/wasmtime-44.0.1/cranelift/isle/veri/veri_engine/examples/x86/
H A Damode_add_uextend_shl.isle75 ;; Crocus specification to model the Wasm shift semantics:
106 ;; Sign-extend-32-to-64(simm32) + base + (index << shift)
107 (spec (Amode.ImmRegRegShift simm base index shift flags)
112 (bvshl index (zero_ext 64 shift)))))
127 ;; Sign-extend-32-to-64(simm32) + base + (index << shift)
131 (shift u8)
172 (uextend (ishl index (iconst (uimm8 shift)))))
173 (if (u32_lteq (u8_as_u32 shift) 3))
174 (Amode.ImmRegRegShift off base (extend_to_gpr index $I64 (ExtendKind.Zero)) shift flags))
H A Damode_add_shl.isle96 ;; Sign-extend-32-to-64(simm32) + base + (index << shift)
97 (spec (Amode.ImmRegRegShift simm base index shift flags)
102 (bvshl index (zero_ext 64 shift)))))
116 ;; Sign-extend-32-to-64(simm32) + base + (index << shift)
120 (shift u8)
156 (rule 2 (amode_add (Amode.ImmReg off (valid_reg base) flags) (ishl index (iconst (uimm8 shift))))
157 (if (u32_lteq (u8_as_u32 shift) 3))
158 (Amode.ImmRegRegShift off base index shift flags))
/wasmtime-44.0.1/cranelift/isle/isle/isle_examples/pass/
H A Dprio_trie_bug.isle50 ;; Sign-extend-32-to-64(simm32) + base + (index << shift)
54 (shift u32)
94 (rule 1 (amode_add (Amode.ImmRegRegShift off base index shift flags)
97 (Amode.ImmRegRegShift sum base index shift flags))
104 (rule (amode_add (Amode.ImmRegRegShift off base index shift flags) value)
106 (Amode.ImmRegRegShift off sum index shift flags)))
/wasmtime-44.0.1/cranelift/codegen/src/opts/
H A Dshifts.isle26 ;; this is a signed or unsigned shift right).
84 (rule (simplify (sshr (ty_int ty) (ishl ty x (iconst _ shift)) (iconst _ shift)))
85 (if-let (u64_from_imm64 (u64_extract_non_zero shift_u64)) shift)
88 (rule (simplify (ushr (ty_int ty) (ishl ty x (iconst _ shift)) (iconst _ shift)))
89 (if-let (u64_from_imm64 (u64_extract_non_zero shift_u64)) shift)
104 ;; can remove any extend/reduce operations on the shift amount.
113 ;; backend doesn't support SIMD shifts with 128-bit shift amounts.
145 ;; Try to combine the shift amount from multiple consecutive shifts
146 ;; This only works if the shift amount remains smaller than the bit
179 ;; Similarly, if the shift amount overflows the type, then we can turn
[all …]
/wasmtime-44.0.1/cranelift/codegen/src/
H A Disle_prelude.rs61 let shift = 64 - type_width; localVariable
68 let min = ((self.ty_smin(ty) as i64) << shift) >> shift;
120 let x = (x.bits() << shift) >> shift;
239 let shift = 64_u64 localVariable
242 u64::MAX >> shift
249 let shift = 64_u64 localVariable
252 u64::MAX >> shift
274 let shift = 64_u64 localVariable
277 (i64::MIN as u64) >> shift
284 let shift = 64_u64 localVariable
[all …]
/wasmtime-44.0.1/cranelift/codegen/src/isa/x64/
H A Dlower.rs210 matches_input(ctx, spec, Opcode::Ishl).and_then(|shift| { in matches_small_constant_shift()
214 insn: shift, in matches_small_constant_shift()
220 insn: shift, in matches_small_constant_shift()
260 let (base, index, shift) = if let Some((shift_input, shift_amt)) = in lower_to_amode()
308 shift, in lower_to_amode()
/wasmtime-44.0.1/cranelift/codegen/src/isa/x64/inst/
H A Dargs.rs354 pub fn imm_reg_reg_shift(simm32: i32, base: Gpr, index: Gpr, shift: u8) -> Self { in imm_reg_reg_shift()
357 debug_assert!(shift <= 3); in imm_reg_reg_shift()
362 shift, in imm_reg_reg_shift()
383 shift, in with_flags()
389 shift, in with_flags()
469 shift, in pretty_print()
476 1 << shift in pretty_print()
/wasmtime-44.0.1/winch/codegen/src/isa/x64/
H A Daddress.rs18 shift: u8,
/wasmtime-44.0.1/cranelift/isle/veri/veri_engine/examples/store/
H A Dbroken_bvsub_store_with_load.isle17 ;; Sign-extend-32-to-64(simm32) + base + (index << shift)
21 (shift u8)
H A Dbroken_isub_store_with_load.isle17 ;; Sign-extend-32-to-64(simm32) + base + (index << shift)
21 (shift u8)
/wasmtime-44.0.1/cranelift/assembler-x64/src/
H A Dmem.rs196 let shift = scale.shift(); in fmt() localVariable
197 if shift > 1 { in fmt()
250 fn shift(&self) -> u8 { in shift() method
/wasmtime-44.0.1/cranelift/codegen/meta/src/
H A Dgen_isle.rs623 let shift = NumericOp { in ops_for_type() localVariable
775 ..shift.clone() in ops_for_type()
780 ..shift.clone() in ops_for_type()
790 ..shift.clone() in ops_for_type()
795 ..shift.clone() in ops_for_type()
800 ..shift.clone() in ops_for_type()
805 ..shift.clone() in ops_for_type()
/wasmtime-44.0.1/cranelift/assembler-x64/meta/src/
H A Dinstructions.rs30 mod shift; module
70 all.extend(shift::list()); in list()
/wasmtime-44.0.1/cranelift/codegen/src/isa/aarch64/
H A Dlower.isle907 (shift Reg (shll32 sum false))
1548 (shift Reg (vec_dup masked_shift_amt size)))
1549 (sshl x shift size)))
1561 ;; shift amount where necessary.
1602 ;; 8/16-bit shift base case.
1621 ;; 32/64-bit shift base cases.
1632 (if-let shift (imm_shift_from_imm64 ty k))
1633 (alu_rr_imm_shift op ty x shift))
1658 (ushl x shift size)))
1716 (sshl x shift size)))
[all …]
H A Dinst.isle1550 ;; Signed shift left
1552 ;; Unsigned shift left
1747 ;; Unsigned shift left
1749 ;; Unsigned shift right
1751 ;; Signed shift right
1906 ;; and the amount to shift by.
2251 src1 src2 shift)))
2260 src1 src2 shift)))
3211 (rule (orr_not_shift ty x y shift) (alu_rrr_shift (ALUOp.OrrNot) ty x y shift))
3238 (rule (orr_shift ty x y shift) (alu_rrr_shift (ALUOp.Orr) ty x y shift))
[all …]
/wasmtime-44.0.1/cranelift/codegen/src/isa/riscv64/lower/
H A Disle.rs331 let shift = Imm12::from_i16(trailing as i16 - 12); in i64_shift_for_lui() localVariable
333 Some((base, shift)) in i64_shift_for_lui()
343 let shift = Imm12::from_i16(trailing as i16); in i64_shift() localVariable
345 Some((base, shift)) in i64_shift()
/wasmtime-44.0.1/tests/misc_testsuite/custom-page-sizes/
H A Dcustom-page-sizes-invalid.wast79 ;; shift overflow.

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