Lines Matching refs:shift
703 ;; Vector shift by immediate Shift Left (immediate), Unsigned Shift Right (immediate)
706 ;; right-shift cannot be encoded. Left shifts are "normal", though, having valid `imm`
715 ;; Destructive vector shift by immediate.
1550 ;; Signed shift left
1552 ;; Unsigned shift left
1744 ;; A shift-by-immediate operation on each lane of a vector.
1747 ;; Unsigned shift left
1749 ;; Unsigned shift right
1751 ;; Signed shift right
1755 ;; Destructive shift-by-immediate operation on each lane of a vector.
1906 ;; and the amount to shift by.
1911 ;; and the amount to shift by.
2239 (rule (alu_rrr_shift op ty src1 src2 shift)
2241 (_ Unit (emit (MInst.AluRRRShift op (operand_size ty) dst src1 src2 shift))))
2248 (if-let shift (lshr_from_u64 $I64 shift_amount))
2251 src1 src2 shift)))
2257 (if-let shift (ashr_from_u64 $I64 shift_amount))
2260 src1 src2 shift)))
2780 (spec (add_shift ty a b shift)
2784 (switch (extract 15 8 shift)
2785 …Lsl) (bvshl (extract 31 0 b) (zero_ext 32 (bvand (bvsub (int2bv 8 ty) #x01) (extract 7 0 shift)))))
2786 …sr) (bvlshr (extract 31 0 b) (zero_ext 32 (bvand (bvsub (int2bv 8 ty) #x01) (extract 7 0 shift)))))
2787 … (bvashr (extract 31 0 b) (zero_ext 32 (bvand (bvsub (int2bv 8 ty) #x01) (extract 7 0 shift))))))))
2789 (switch (extract 15 8 shift)
2790 ((ALUOp.Lsl) (bvshl b (zero_ext 64 (bvand (bvsub (int2bv 8 ty) #x01) (extract 7 0 shift)))))
2791 … ((ALUOp.Lsr) (bvlshr b (zero_ext 64 (bvand (bvsub (int2bv 8 ty) #x01) (extract 7 0 shift)))))
2792 …((ALUOp.Asr) (bvashr b (zero_ext 64 (bvand (bvsub (int2bv 8 ty) #x01) (extract 7 0 shift)))))))))))
2849 (spec (sub_shift ty a b shift)
2852 (conv_to 64 (bvsub (extract 31 0 a) (switch (extract 15 8 shift)
2853 …Lsl) (bvshl (extract 31 0 b) (zero_ext 32 (bvand (bvsub (int2bv 8 ty) #x01) (extract 7 0 shift)))))
2854 …sr) (bvlshr (extract 31 0 b) (zero_ext 32 (bvand (bvsub (int2bv 8 ty) #x01) (extract 7 0 shift)))))
2855 … (bvashr (extract 31 0 b) (zero_ext 32 (bvand (bvsub (int2bv 8 ty) #x01) (extract 7 0 shift))))))))
2856 (bvsub a (switch (extract 15 8 shift)
2857 ((ALUOp.Lsl) (bvshl b (zero_ext 64 (bvand (bvsub (int2bv 8 ty) #x01) (extract 7 0 shift)))))
2858 … ((ALUOp.Lsr) (bvlshr b (zero_ext 64 (bvand (bvsub (int2bv 8 ty) #x01) (extract 7 0 shift)))))
2859 …((ALUOp.Asr) (bvashr b (zero_ext 64 (bvand (bvsub (int2bv 8 ty) #x01) (extract 7 0 shift)))))))))))
3205 (spec (orr_not_shift ty a b shift)
3208 …64 (bvor a (bvnot (bvshl b (zero_ext 64 (bvand (bvsub (int2bv 8 ty) #x01) (extract 7 0 shift)))))))
3209 …(bvor a (bvnot (bvshl b (zero_ext 64 (bvand (bvsub (int2bv 8 ty) #x01) (extract 7 0 shift))))))))))
3211 (rule (orr_not_shift ty x y shift) (alu_rrr_shift (ALUOp.OrrNot) ty x y shift))
3238 (rule (orr_shift ty x y shift) (alu_rrr_shift (ALUOp.Orr) ty x y shift))
3342 (rule (a64_extr ty x y shift) (alu_rrr_shift (ALUOp.Extr) ty x y (a64_extr_imm ty shift)))
3735 ;; a 32-bit register produces -129 with no overflow). However, if we left shift
3955 ;; extension must happen before the shift. This will pattern-match the shift
4339 ;; Helper for getting the maximum shift amount for a type.