Lines Matching refs:shift

82 ;; Special cases for when we're adding the shift of a different
83 ;; register by a constant amount and the shift can get folded into the add.
157 ;; When the shuffle looks like "concatenate `a` and `b` and shift right by n*8
741 ;; Finally a special case for when we're subtracting the shift of a different
742 ;; register by a constant amount and the shift can get folded into the sub.
890             ;; below would shift out the overflow bits anyway.
907             (shift Reg (shll32 sum false))
912             (result Reg (umlal32 shift tmp2 tmp1 false)))
1072 ;; In the narrow 8 or 16 bit case, we need to insert an additional left-shift
1454 ;; shift-right. Two patterns are used here to detect either ordering of the
1548             (shift Reg (vec_dup masked_shift_amt size)))
1549         (sshl x shift size)))
1556 ;; Helper function to emit a shift operation with the opcode specified and
1561 ;; shift amount where necessary.
1602 ;; 8/16-bit shift base case.
1604 ;; When shifting for amounts larger than the size of the type, the CLIF shift
1609 ;; types (i16, i8) we need to do this manually, so we wrap the shift amount
1621 ;; 32/64-bit shift base cases.
1632       (if-let shift (imm_shift_from_imm64 ty k))
1633       (alu_rr_imm_shift op ty x shift))
1651 ;; Note that for constant shifts a 0-width shift can't be emitted so it's
1652 ;; special cased to pass through the input as-is since a 0-shift doesn't modify
1657             (shift Reg (vec_dup (sub $I64 (zero_reg) masked_shift_amt) size)))
1658         (ushl x shift size)))
1708 ;; Note that right shifts are implemented with a negative left shift. Also note
1709 ;; that for constant shifts a 0-width shift can't be emitted so it's special
1710 ;; cased to pass through the input as-is since a 0-shift doesn't modify the
1715             (shift Reg (vec_dup (sub $I64 (zero_reg) masked_shift_amt) size)))
1716         (sshl x shift size)))
1769 ;; Note that when negating the shift amount here the upper bits are ignored
1770 ;; by the rotr instruction, meaning that we'll still left-shift by the desired
1939 ;; the reversed result in the highest 8 bits, so we need to shift them down into
1945 ;; the reversed result in the highest 16 bits, so we need to shift them down into
2875 ;; temporaries.  The shift is done early so as to give the register
2886             ;; the whole lane (sshr is an arithmetic right shift).
2910             ;; the whole lane (sshr is an arithmetic right shift).
2923             ;; the whole lane (sshr is an arithmetic right shift).
2935             ;; Grab the MSB out of each of the lanes, right-shift to
2936             ;; LSB, and add with a left-shift of upper lane's MSB back
2938             ;; shift).