Searched refs:mask (Results 1 – 6 of 6) sorted by relevance
| /pciutils/ |
| H A D | bitops.h | 32 #define GET_REG_MASK(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1))) argument 33 #define SET_REG_MASK(reg, mask, val) \ argument 34 (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
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| H A D | setpci.c | 31 unsigned int mask; member 162 if ((op->values[i].mask & max_values[width]) == max_values[width]) in exec_op() 181 x = (y & ~op->values[i].mask) | op->values[i].value; in exec_op() 182 trace(mask_formats[width], y, op->values[i].value, op->values[i].mask, x); in exec_op() 770 op->values[j].mask = ll; in parse_op() 774 op->values[j].mask = ~0U; in parse_op()
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| H A D | ls-caps.c | 635 u32 mask, pending; in cap_msi() local 641 mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_64); in cap_msi() 648 mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_32); in cap_msi() 651 printf("\t\tMasking: %08x Pending: %08x\n", mask, pending); in cap_msi()
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| H A D | ChangeLog | 603 * When scanning extended capabilities, properly mask the lowest 2 bits, 1709 * setpci.c: Cleaned up mask/value code. 1713 * setpci.c: Individual bits to be set can be specified as <value>:<mask>.
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| H A D | pci.ids | 38824 # observed, and documented in Intel revision note; new mask of 1011:0026
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| /pciutils/lib/ |
| H A D | filter.c | 75 unsigned int mask = ~0U; in parse_hex_field() local 95 mask = mask << 4; in parse_hex_field() 110 mask = (mask << 4) | 0xf; in parse_hex_field() 119 *maskp = mask; in parse_hex_field()
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