1 /*
2 * The PCI Utilities -- Show Capabilities
3 *
4 * Copyright (c) 1997--2018 Martin Mares <[email protected]>
5 *
6 * Can be freely distributed and used under the terms of the GNU GPL v2+.
7 *
8 * SPDX-License-Identifier: GPL-2.0-or-later
9 */
10
11 #include <stdio.h>
12 #include <string.h>
13 #include <stdlib.h>
14
15 #include "lspci.h"
16
17 static void
cap_pm(struct device * d,int where,int cap)18 cap_pm(struct device *d, int where, int cap)
19 {
20 int t, b;
21 static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 };
22
23 printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK);
24 if (verbose < 2)
25 return;
26 printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n",
27 FLAG(cap, PCI_PM_CAP_PME_CLOCK),
28 FLAG(cap, PCI_PM_CAP_DSI),
29 FLAG(cap, PCI_PM_CAP_D1),
30 FLAG(cap, PCI_PM_CAP_D2),
31 pm_aux_current[(cap & PCI_PM_CAP_AUX_C_MASK) >> 6],
32 FLAG(cap, PCI_PM_CAP_PME_D0),
33 FLAG(cap, PCI_PM_CAP_PME_D1),
34 FLAG(cap, PCI_PM_CAP_PME_D2),
35 FLAG(cap, PCI_PM_CAP_PME_D3_HOT),
36 FLAG(cap, PCI_PM_CAP_PME_D3_COLD));
37 if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL))
38 return;
39 t = get_conf_word(d, where + PCI_PM_CTRL);
40 printf("\t\tStatus: D%d NoSoftRst%c PME-Enable%c DSel=%d DScale=%d PME%c\n",
41 t & PCI_PM_CTRL_STATE_MASK,
42 FLAG(t, PCI_PM_CTRL_NO_SOFT_RST),
43 FLAG(t, PCI_PM_CTRL_PME_ENABLE),
44 (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9,
45 (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13,
46 FLAG(t, PCI_PM_CTRL_PME_STATUS));
47 b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS);
48 if (b)
49 printf("\t\tBridge: PM%c B3%c\n",
50 FLAG(b, PCI_PM_BPCC_ENABLE),
51 FLAG(~b, PCI_PM_PPB_B2_B3));
52 }
53
54 static void
format_agp_rate(int rate,char * buf,int agp3)55 format_agp_rate(int rate, char *buf, int agp3)
56 {
57 char *c = buf;
58 int i;
59
60 for (i=0; i<=2; i++)
61 if (rate & (1 << i))
62 {
63 if (c != buf)
64 *c++ = ',';
65 c += sprintf(c, "x%d", 1 << (i + 2*agp3));
66 }
67 if (c != buf)
68 *c = 0;
69 else
70 strcpy(buf, "<none>");
71 }
72
73 static void
cap_agp(struct device * d,int where,int cap)74 cap_agp(struct device *d, int where, int cap)
75 {
76 u32 t;
77 char rate[16];
78 int ver, rev;
79 int agp3 = 0;
80
81 ver = (cap >> 4) & 0x0f;
82 rev = cap & 0x0f;
83 printf("AGP version %x.%x\n", ver, rev);
84 if (verbose < 2)
85 return;
86 if (!config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS))
87 return;
88 t = get_conf_long(d, where + PCI_AGP_STATUS);
89 if (ver >= 3 && (t & PCI_AGP_STATUS_AGP3))
90 agp3 = 1;
91 format_agp_rate(t & 7, rate, agp3);
92 printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n",
93 ((t & PCI_AGP_STATUS_RQ_MASK) >> 24U) + 1,
94 FLAG(t, PCI_AGP_STATUS_ISOCH),
95 ((t & PCI_AGP_STATUS_ARQSZ_MASK) >> 13),
96 ((t & PCI_AGP_STATUS_CAL_MASK) >> 10),
97 FLAG(t, PCI_AGP_STATUS_SBA),
98 FLAG(t, PCI_AGP_STATUS_ITA_COH),
99 FLAG(t, PCI_AGP_STATUS_GART64),
100 FLAG(t, PCI_AGP_STATUS_HTRANS),
101 FLAG(t, PCI_AGP_STATUS_64BIT),
102 FLAG(t, PCI_AGP_STATUS_FW),
103 FLAG(t, PCI_AGP_STATUS_AGP3),
104 rate);
105 t = get_conf_long(d, where + PCI_AGP_COMMAND);
106 format_agp_rate(t & 7, rate, agp3);
107 printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n",
108 ((t & PCI_AGP_COMMAND_RQ_MASK) >> 24U) + 1,
109 ((t & PCI_AGP_COMMAND_ARQSZ_MASK) >> 13),
110 ((t & PCI_AGP_COMMAND_CAL_MASK) >> 10),
111 FLAG(t, PCI_AGP_COMMAND_SBA),
112 FLAG(t, PCI_AGP_COMMAND_AGP),
113 FLAG(t, PCI_AGP_COMMAND_GART64),
114 FLAG(t, PCI_AGP_COMMAND_64BIT),
115 FLAG(t, PCI_AGP_COMMAND_FW),
116 rate);
117 }
118
119 static void
cap_pcix_nobridge(struct device * d,int where)120 cap_pcix_nobridge(struct device *d, int where)
121 {
122 u16 command;
123 u32 status;
124 static const byte max_outstanding[8] = { 1, 2, 3, 4, 8, 12, 16, 32 };
125
126 printf("PCI-X non-bridge device\n");
127
128 if (verbose < 2)
129 return;
130
131 if (!config_fetch(d, where + PCI_PCIX_STATUS, 4))
132 return;
133
134 command = get_conf_word(d, where + PCI_PCIX_COMMAND);
135 status = get_conf_long(d, where + PCI_PCIX_STATUS);
136 printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n",
137 FLAG(command, PCI_PCIX_COMMAND_DPERE),
138 FLAG(command, PCI_PCIX_COMMAND_ERO),
139 1 << (9 + ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U)),
140 max_outstanding[(command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U]);
141 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c\n",
142 (status & PCI_PCIX_STATUS_BUS) >> 8,
143 (status & PCI_PCIX_STATUS_DEVICE) >> 3,
144 (status & PCI_PCIX_STATUS_FUNCTION),
145 FLAG(status, PCI_PCIX_STATUS_64BIT),
146 FLAG(status, PCI_PCIX_STATUS_133MHZ),
147 FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
148 FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
149 ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
150 1 << (9 + ((status & PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT) >> 21)),
151 max_outstanding[(status & PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS) >> 23],
152 1 << (3 + ((status & PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE) >> 26)),
153 FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS),
154 FLAG(status, PCI_PCIX_STATUS_266MHZ),
155 FLAG(status, PCI_PCIX_STATUS_533MHZ));
156 }
157
158 static void
cap_pcix_bridge(struct device * d,int where)159 cap_pcix_bridge(struct device *d, int where)
160 {
161 static const char * const sec_clock_freq[8] = { "conv", "66MHz", "100MHz", "133MHz", "?4", "?5", "?6", "?7" };
162 u16 secstatus;
163 u32 status, upstcr, downstcr;
164
165 printf("PCI-X bridge device\n");
166
167 if (verbose < 2)
168 return;
169
170 if (!config_fetch(d, where + PCI_PCIX_BRIDGE_STATUS, 12))
171 return;
172
173 secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS);
174 printf("\t\tSecondary Status: 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c Freq=%s\n",
175 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT),
176 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ),
177 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED),
178 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
179 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
180 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
181 sec_clock_freq[(secstatus & PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ) >> 6]);
182 status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
183 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c\n",
184 (status & PCI_PCIX_BRIDGE_STATUS_BUS) >> 8,
185 (status & PCI_PCIX_BRIDGE_STATUS_DEVICE) >> 3,
186 (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION),
187 FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
188 FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
189 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED),
190 FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC),
191 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN),
192 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED));
193 upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL);
194 printf("\t\tUpstream: Capacity=%u CommitmentLimit=%u\n",
195 (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
196 (upstcr >> 16) & 0xffff);
197 downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL);
198 printf("\t\tDownstream: Capacity=%u CommitmentLimit=%u\n",
199 (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
200 (downstcr >> 16) & 0xffff);
201 }
202
203 static void
cap_pcix(struct device * d,int where)204 cap_pcix(struct device *d, int where)
205 {
206 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
207 {
208 case PCI_HEADER_TYPE_NORMAL:
209 cap_pcix_nobridge(d, where);
210 break;
211 case PCI_HEADER_TYPE_BRIDGE:
212 cap_pcix_bridge(d, where);
213 break;
214 }
215 }
216
217 static inline char *
ht_link_width(unsigned width)218 ht_link_width(unsigned width)
219 {
220 static char * const widths[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" };
221 return widths[width];
222 }
223
224 static inline char *
ht_link_freq(unsigned freq)225 ht_link_freq(unsigned freq)
226 {
227 static char * const freqs[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz",
228 "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" };
229 return freqs[freq];
230 }
231
232 static void
cap_ht_pri(struct device * d,int where,int cmd)233 cap_ht_pri(struct device *d, int where, int cmd)
234 {
235 u16 lctr0, lcnf0, lctr1, lcnf1, eh;
236 u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn;
237
238 printf("HyperTransport: Slave or Primary Interface\n");
239 if (verbose < 2)
240 return;
241
242 if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0))
243 return;
244 rid = get_conf_byte(d, where + PCI_HT_PRI_RID);
245 if (rid < 0x22 && rid > 0x11)
246 printf("\t\t!!! Possibly incomplete decoding\n");
247
248 printf("\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c",
249 (cmd & PCI_HT_PRI_CMD_BUID),
250 (cmd & PCI_HT_PRI_CMD_UC) >> 5,
251 FLAG(cmd, PCI_HT_PRI_CMD_MH),
252 FLAG(cmd, PCI_HT_PRI_CMD_DD));
253 if (rid >= 0x22)
254 printf(" DUL%c", FLAG(cmd, PCI_HT_PRI_CMD_DUL));
255 printf("\n");
256
257 lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
258 printf("\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x",
259 FLAG(lctr0, PCI_HT_LCTR_CFLE),
260 FLAG(lctr0, PCI_HT_LCTR_CST),
261 FLAG(lctr0, PCI_HT_LCTR_CFE),
262 FLAG(lctr0, PCI_HT_LCTR_LKFAIL),
263 FLAG(lctr0, PCI_HT_LCTR_INIT),
264 FLAG(lctr0, PCI_HT_LCTR_EOC),
265 FLAG(lctr0, PCI_HT_LCTR_TXO),
266 (lctr0 & PCI_HT_LCTR_CRCERR) >> 8);
267 if (rid >= 0x22)
268 printf(" IsocEn%c LSEn%c ExtCTL%c 64b%c",
269 FLAG(lctr0, PCI_HT_LCTR_ISOCEN),
270 FLAG(lctr0, PCI_HT_LCTR_LSEN),
271 FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
272 FLAG(lctr0, PCI_HT_LCTR_64B));
273 printf("\n");
274
275 lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
276 if (rid < 0x22)
277 printf("\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n",
278 ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
279 ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
280 ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
281 ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12));
282 else
283 printf("\t\tLink Config 0: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n",
284 ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
285 FLAG(lcnf0, PCI_HT_LCNF_DFI),
286 ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
287 FLAG(lcnf0, PCI_HT_LCNF_DFO),
288 ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
289 FLAG(lcnf0, PCI_HT_LCNF_DFIE),
290 ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12),
291 FLAG(lcnf0, PCI_HT_LCNF_DFOE));
292
293 lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
294 printf("\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x",
295 FLAG(lctr1, PCI_HT_LCTR_CFLE),
296 FLAG(lctr1, PCI_HT_LCTR_CST),
297 FLAG(lctr1, PCI_HT_LCTR_CFE),
298 FLAG(lctr1, PCI_HT_LCTR_LKFAIL),
299 FLAG(lctr1, PCI_HT_LCTR_INIT),
300 FLAG(lctr1, PCI_HT_LCTR_EOC),
301 FLAG(lctr1, PCI_HT_LCTR_TXO),
302 (lctr1 & PCI_HT_LCTR_CRCERR) >> 8);
303 if (rid >= 0x22)
304 printf(" IsocEn%c LSEn%c ExtCTL%c 64b%c",
305 FLAG(lctr1, PCI_HT_LCTR_ISOCEN),
306 FLAG(lctr1, PCI_HT_LCTR_LSEN),
307 FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
308 FLAG(lctr1, PCI_HT_LCTR_64B));
309 printf("\n");
310
311 lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
312 if (rid < 0x22)
313 printf("\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n",
314 ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
315 ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
316 ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
317 ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12));
318 else
319 printf("\t\tLink Config 1: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n",
320 ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
321 FLAG(lcnf1, PCI_HT_LCNF_DFI),
322 ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
323 FLAG(lcnf1, PCI_HT_LCNF_DFO),
324 ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
325 FLAG(lcnf1, PCI_HT_LCNF_DFIE),
326 ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12),
327 FLAG(lcnf1, PCI_HT_LCNF_DFOE));
328
329 printf("\t\tRevision ID: %u.%02u\n",
330 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
331 if (rid < 0x22)
332 return;
333
334 lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
335 printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
336 printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
337 FLAG(lfrer0, PCI_HT_LFRER_PROT),
338 FLAG(lfrer0, PCI_HT_LFRER_OV),
339 FLAG(lfrer0, PCI_HT_LFRER_EOC),
340 FLAG(lfrer0, PCI_HT_LFRER_CTLT));
341
342 lfcap0 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP0);
343 printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
344 FLAG(lfcap0, PCI_HT_LFCAP_200),
345 FLAG(lfcap0, PCI_HT_LFCAP_300),
346 FLAG(lfcap0, PCI_HT_LFCAP_400),
347 FLAG(lfcap0, PCI_HT_LFCAP_500),
348 FLAG(lfcap0, PCI_HT_LFCAP_600),
349 FLAG(lfcap0, PCI_HT_LFCAP_800),
350 FLAG(lfcap0, PCI_HT_LFCAP_1000),
351 FLAG(lfcap0, PCI_HT_LFCAP_1200),
352 FLAG(lfcap0, PCI_HT_LFCAP_1400),
353 FLAG(lfcap0, PCI_HT_LFCAP_1600),
354 FLAG(lfcap0, PCI_HT_LFCAP_VEND));
355
356 ftr = get_conf_byte(d, where + PCI_HT_PRI_FTR);
357 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n",
358 FLAG(ftr, PCI_HT_FTR_ISOCFC),
359 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
360 FLAG(ftr, PCI_HT_FTR_CRCTM),
361 FLAG(ftr, PCI_HT_FTR_ECTLT),
362 FLAG(ftr, PCI_HT_FTR_64BA),
363 FLAG(ftr, PCI_HT_FTR_UIDRD));
364
365 lfrer1 = get_conf_byte(d, where + PCI_HT_PRI_LFRER1);
366 printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1 & PCI_HT_LFRER_FREQ));
367 printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
368 FLAG(lfrer1, PCI_HT_LFRER_PROT),
369 FLAG(lfrer1, PCI_HT_LFRER_OV),
370 FLAG(lfrer1, PCI_HT_LFRER_EOC),
371 FLAG(lfrer1, PCI_HT_LFRER_CTLT));
372
373 lfcap1 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP1);
374 printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
375 FLAG(lfcap1, PCI_HT_LFCAP_200),
376 FLAG(lfcap1, PCI_HT_LFCAP_300),
377 FLAG(lfcap1, PCI_HT_LFCAP_400),
378 FLAG(lfcap1, PCI_HT_LFCAP_500),
379 FLAG(lfcap1, PCI_HT_LFCAP_600),
380 FLAG(lfcap1, PCI_HT_LFCAP_800),
381 FLAG(lfcap1, PCI_HT_LFCAP_1000),
382 FLAG(lfcap1, PCI_HT_LFCAP_1200),
383 FLAG(lfcap1, PCI_HT_LFCAP_1400),
384 FLAG(lfcap1, PCI_HT_LFCAP_1600),
385 FLAG(lfcap1, PCI_HT_LFCAP_VEND));
386
387 eh = get_conf_word(d, where + PCI_HT_PRI_EH);
388 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
389 FLAG(eh, PCI_HT_EH_PFLE),
390 FLAG(eh, PCI_HT_EH_OFLE),
391 FLAG(eh, PCI_HT_EH_PFE),
392 FLAG(eh, PCI_HT_EH_OFE),
393 FLAG(eh, PCI_HT_EH_EOCFE),
394 FLAG(eh, PCI_HT_EH_RFE),
395 FLAG(eh, PCI_HT_EH_CRCFE),
396 FLAG(eh, PCI_HT_EH_SERRFE),
397 FLAG(eh, PCI_HT_EH_CF),
398 FLAG(eh, PCI_HT_EH_RE),
399 FLAG(eh, PCI_HT_EH_PNFE),
400 FLAG(eh, PCI_HT_EH_ONFE),
401 FLAG(eh, PCI_HT_EH_EOCNFE),
402 FLAG(eh, PCI_HT_EH_RNFE),
403 FLAG(eh, PCI_HT_EH_CRCNFE),
404 FLAG(eh, PCI_HT_EH_SERRNFE));
405
406 mbu = get_conf_byte(d, where + PCI_HT_PRI_MBU);
407 mlu = get_conf_byte(d, where + PCI_HT_PRI_MLU);
408 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
409
410 bn = get_conf_byte(d, where + PCI_HT_PRI_BN);
411 printf("\t\tBus Number: %02x\n", bn);
412 }
413
414 static void
cap_ht_sec(struct device * d,int where,int cmd)415 cap_ht_sec(struct device *d, int where, int cmd)
416 {
417 u16 lctr, lcnf, ftr, eh;
418 u8 rid, lfrer, lfcap, mbu, mlu;
419 char *fmt;
420
421 printf("HyperTransport: Host or Secondary Interface\n");
422 if (verbose < 2)
423 return;
424
425 if (!config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR))
426 return;
427 rid = get_conf_byte(d, where + PCI_HT_SEC_RID);
428 if (rid < 0x22 && rid > 0x11)
429 printf("\t\t!!! Possibly incomplete decoding\n");
430
431 if (rid >= 0x22)
432 fmt = "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n";
433 else
434 fmt = "\t\tCommand: WarmRst%c DblEnd%c\n";
435 printf(fmt,
436 FLAG(cmd, PCI_HT_SEC_CMD_WR),
437 FLAG(cmd, PCI_HT_SEC_CMD_DE),
438 (cmd & PCI_HT_SEC_CMD_DN) >> 2,
439 FLAG(cmd, PCI_HT_SEC_CMD_CS),
440 FLAG(cmd, PCI_HT_SEC_CMD_HH),
441 FLAG(cmd, PCI_HT_SEC_CMD_AS),
442 FLAG(cmd, PCI_HT_SEC_CMD_HIECE),
443 FLAG(cmd, PCI_HT_SEC_CMD_DUL));
444 lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR);
445 if (rid >= 0x22)
446 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
447 else
448 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
449 printf(fmt,
450 FLAG(lctr, PCI_HT_LCTR_CFLE),
451 FLAG(lctr, PCI_HT_LCTR_CST),
452 FLAG(lctr, PCI_HT_LCTR_CFE),
453 FLAG(lctr, PCI_HT_LCTR_LKFAIL),
454 FLAG(lctr, PCI_HT_LCTR_INIT),
455 FLAG(lctr, PCI_HT_LCTR_EOC),
456 FLAG(lctr, PCI_HT_LCTR_TXO),
457 (lctr & PCI_HT_LCTR_CRCERR) >> 8,
458 FLAG(lctr, PCI_HT_LCTR_ISOCEN),
459 FLAG(lctr, PCI_HT_LCTR_LSEN),
460 FLAG(lctr, PCI_HT_LCTR_EXTCTL),
461 FLAG(lctr, PCI_HT_LCTR_64B));
462 lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF);
463 if (rid >= 0x22)
464 fmt = "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
465 else
466 fmt = "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
467 printf(fmt,
468 ht_link_width(lcnf & PCI_HT_LCNF_MLWI),
469 ht_link_width((lcnf & PCI_HT_LCNF_MLWO) >> 4),
470 ht_link_width((lcnf & PCI_HT_LCNF_LWI) >> 8),
471 ht_link_width((lcnf & PCI_HT_LCNF_LWO) >> 12),
472 FLAG(lcnf, PCI_HT_LCNF_DFI),
473 FLAG(lcnf, PCI_HT_LCNF_DFO),
474 FLAG(lcnf, PCI_HT_LCNF_DFIE),
475 FLAG(lcnf, PCI_HT_LCNF_DFOE));
476 printf("\t\tRevision ID: %u.%02u\n",
477 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
478 if (rid < 0x22)
479 return;
480 lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER);
481 printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ));
482 printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
483 FLAG(lfrer, PCI_HT_LFRER_PROT),
484 FLAG(lfrer, PCI_HT_LFRER_OV),
485 FLAG(lfrer, PCI_HT_LFRER_EOC),
486 FLAG(lfrer, PCI_HT_LFRER_CTLT));
487 lfcap = get_conf_byte(d, where + PCI_HT_SEC_LFCAP);
488 printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
489 FLAG(lfcap, PCI_HT_LFCAP_200),
490 FLAG(lfcap, PCI_HT_LFCAP_300),
491 FLAG(lfcap, PCI_HT_LFCAP_400),
492 FLAG(lfcap, PCI_HT_LFCAP_500),
493 FLAG(lfcap, PCI_HT_LFCAP_600),
494 FLAG(lfcap, PCI_HT_LFCAP_800),
495 FLAG(lfcap, PCI_HT_LFCAP_1000),
496 FLAG(lfcap, PCI_HT_LFCAP_1200),
497 FLAG(lfcap, PCI_HT_LFCAP_1400),
498 FLAG(lfcap, PCI_HT_LFCAP_1600),
499 FLAG(lfcap, PCI_HT_LFCAP_VEND));
500 ftr = get_conf_word(d, where + PCI_HT_SEC_FTR);
501 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n",
502 FLAG(ftr, PCI_HT_FTR_ISOCFC),
503 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
504 FLAG(ftr, PCI_HT_FTR_CRCTM),
505 FLAG(ftr, PCI_HT_FTR_ECTLT),
506 FLAG(ftr, PCI_HT_FTR_64BA),
507 FLAG(ftr, PCI_HT_FTR_UIDRD),
508 FLAG(ftr, PCI_HT_SEC_FTR_EXTRS),
509 FLAG(ftr, PCI_HT_SEC_FTR_UCNFE));
510 if (ftr & PCI_HT_SEC_FTR_EXTRS)
511 {
512 eh = get_conf_word(d, where + PCI_HT_SEC_EH);
513 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
514 FLAG(eh, PCI_HT_EH_PFLE),
515 FLAG(eh, PCI_HT_EH_OFLE),
516 FLAG(eh, PCI_HT_EH_PFE),
517 FLAG(eh, PCI_HT_EH_OFE),
518 FLAG(eh, PCI_HT_EH_EOCFE),
519 FLAG(eh, PCI_HT_EH_RFE),
520 FLAG(eh, PCI_HT_EH_CRCFE),
521 FLAG(eh, PCI_HT_EH_SERRFE),
522 FLAG(eh, PCI_HT_EH_CF),
523 FLAG(eh, PCI_HT_EH_RE),
524 FLAG(eh, PCI_HT_EH_PNFE),
525 FLAG(eh, PCI_HT_EH_ONFE),
526 FLAG(eh, PCI_HT_EH_EOCNFE),
527 FLAG(eh, PCI_HT_EH_RNFE),
528 FLAG(eh, PCI_HT_EH_CRCNFE),
529 FLAG(eh, PCI_HT_EH_SERRNFE));
530 mbu = get_conf_byte(d, where + PCI_HT_SEC_MBU);
531 mlu = get_conf_byte(d, where + PCI_HT_SEC_MLU);
532 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
533 }
534 }
535
536 static void
cap_ht(struct device * d,int where,int cmd)537 cap_ht(struct device *d, int where, int cmd)
538 {
539 int type;
540
541 switch (cmd & PCI_HT_CMD_TYP_HI)
542 {
543 case PCI_HT_CMD_TYP_HI_PRI:
544 cap_ht_pri(d, where, cmd);
545 return;
546 case PCI_HT_CMD_TYP_HI_SEC:
547 cap_ht_sec(d, where, cmd);
548 return;
549 }
550
551 type = cmd & PCI_HT_CMD_TYP;
552 switch (type)
553 {
554 case PCI_HT_CMD_TYP_SW:
555 printf("HyperTransport: Switch\n");
556 break;
557 case PCI_HT_CMD_TYP_IDC:
558 printf("HyperTransport: Interrupt Discovery and Configuration\n");
559 break;
560 case PCI_HT_CMD_TYP_RID:
561 printf("HyperTransport: Revision ID: %u.%02u\n",
562 (cmd & PCI_HT_RID_MAJ) >> 5, (cmd & PCI_HT_RID_MIN));
563 break;
564 case PCI_HT_CMD_TYP_UIDC:
565 printf("HyperTransport: UnitID Clumping\n");
566 break;
567 case PCI_HT_CMD_TYP_ECSA:
568 printf("HyperTransport: Extended Configuration Space Access\n");
569 break;
570 case PCI_HT_CMD_TYP_AM:
571 printf("HyperTransport: Address Mapping\n");
572 break;
573 case PCI_HT_CMD_TYP_MSIM:
574 printf("HyperTransport: MSI Mapping Enable%c Fixed%c\n",
575 FLAG(cmd, PCI_HT_MSIM_CMD_EN),
576 FLAG(cmd, PCI_HT_MSIM_CMD_FIXD));
577 if (verbose >= 2 && !(cmd & PCI_HT_MSIM_CMD_FIXD))
578 {
579 u32 offl, offh;
580 if (!config_fetch(d, where + PCI_HT_MSIM_ADDR_LO, 8))
581 break;
582 offl = get_conf_long(d, where + PCI_HT_MSIM_ADDR_LO);
583 offh = get_conf_long(d, where + PCI_HT_MSIM_ADDR_HI);
584 printf("\t\tMapping Address Base: %016" PCI_U64_FMT_X "\n", ((u64)offh << 32) | (offl & ~0xfffff));
585 }
586 break;
587 case PCI_HT_CMD_TYP_DR:
588 printf("HyperTransport: DirectRoute\n");
589 break;
590 case PCI_HT_CMD_TYP_VCS:
591 printf("HyperTransport: VCSet\n");
592 break;
593 case PCI_HT_CMD_TYP_RM:
594 printf("HyperTransport: Retry Mode\n");
595 break;
596 case PCI_HT_CMD_TYP_X86:
597 printf("HyperTransport: X86 (reserved)\n");
598 break;
599 default:
600 printf("HyperTransport: #%02x\n", type >> 11);
601 }
602 }
603
604 static void
cap_msi(struct device * d,int where,int cap)605 cap_msi(struct device *d, int where, int cap)
606 {
607 int is64;
608 u32 t;
609 u16 w;
610
611 printf("MSI: Enable%c Count=%d/%d Maskable%c 64bit%c\n",
612 FLAG(cap, PCI_MSI_FLAGS_ENABLE),
613 1 << ((cap & PCI_MSI_FLAGS_QSIZE) >> 4),
614 1 << ((cap & PCI_MSI_FLAGS_QMASK) >> 1),
615 FLAG(cap, PCI_MSI_FLAGS_MASK_BIT),
616 FLAG(cap, PCI_MSI_FLAGS_64BIT));
617 if (verbose < 2)
618 return;
619 is64 = cap & PCI_MSI_FLAGS_64BIT;
620 if (!config_fetch(d, where + PCI_MSI_ADDRESS_LO, (is64 ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32) + 2 - PCI_MSI_ADDRESS_LO))
621 return;
622 printf("\t\tAddress: ");
623 if (is64)
624 {
625 t = get_conf_long(d, where + PCI_MSI_ADDRESS_HI);
626 w = get_conf_word(d, where + PCI_MSI_DATA_64);
627 printf("%08x", t);
628 }
629 else
630 w = get_conf_word(d, where + PCI_MSI_DATA_32);
631 t = get_conf_long(d, where + PCI_MSI_ADDRESS_LO);
632 printf("%08x Data: %04x\n", t, w);
633 if (cap & PCI_MSI_FLAGS_MASK_BIT)
634 {
635 u32 mask, pending;
636
637 if (is64)
638 {
639 if (!config_fetch(d, where + PCI_MSI_MASK_BIT_64, 8))
640 return;
641 mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_64);
642 pending = get_conf_long(d, where + PCI_MSI_PENDING_64);
643 }
644 else
645 {
646 if (!config_fetch(d, where + PCI_MSI_MASK_BIT_32, 8))
647 return;
648 mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_32);
649 pending = get_conf_long(d, where + PCI_MSI_PENDING_32);
650 }
651 printf("\t\tMasking: %08x Pending: %08x\n", mask, pending);
652 }
653 }
654
exp_downstream_port(int type)655 static int exp_downstream_port(int type)
656 {
657 return type == PCI_EXP_TYPE_ROOT_PORT ||
658 type == PCI_EXP_TYPE_DOWNSTREAM ||
659 type == PCI_EXP_TYPE_PCIE_BRIDGE; /* PCI/PCI-X to PCIe Bridge */
660 }
661
show_power_limit(int value,int scale)662 static void show_power_limit(int value, int scale)
663 {
664 static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 };
665
666 if (scale == 0 && value == 0xFF)
667 {
668 printf(">600W");
669 return;
670 }
671
672 if (scale == 0 && value >= 0xF0 && value <= 0xFE)
673 value = 250 + 25 * (value - 0xF0);
674
675 printf("%gW", value * scales[scale]);
676 }
677
latency_l0s(int value)678 static const char *latency_l0s(int value)
679 {
680 static const char * const latencies[] = { "<64ns", "<128ns", "<256ns", "<512ns", "<1us", "<2us", "<4us", "unlimited" };
681 return latencies[value];
682 }
683
latency_l1(int value)684 static const char *latency_l1(int value)
685 {
686 static const char * const latencies[] = { "<1us", "<2us", "<4us", "<8us", "<16us", "<32us", "<64us", "unlimited" };
687 return latencies[value];
688 }
689
cap_express_dev(struct device * d,int where,int type)690 static void cap_express_dev(struct device *d, int where, int type)
691 {
692 u32 t;
693 u16 w;
694
695 t = get_conf_long(d, where + PCI_EXP_DEVCAP);
696 printf("\t\tDevCap:\tMaxPayload %d bytes, PhantFunc %d",
697 128 << (t & PCI_EXP_DEVCAP_PAYLOAD),
698 (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1);
699 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END))
700 printf(", Latency L0s %s, L1 %s",
701 latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6),
702 latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9));
703 printf("\n");
704 printf("\t\t\tExtTag%c", FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
705 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) ||
706 (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
707 printf(" AttnBtn%c AttnInd%c PwrInd%c",
708 FLAG(t, PCI_EXP_DEVCAP_ATN_BUT),
709 FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND));
710 printf(" RBE%c",
711 FLAG(t, PCI_EXP_DEVCAP_RBE));
712 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_ROOT_INT_EP))
713 printf(" FLReset%c",
714 FLAG(t, PCI_EXP_DEVCAP_FLRESET));
715 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_UPSTREAM) ||
716 (type == PCI_EXP_TYPE_PCI_BRIDGE))
717 {
718 printf(" SlotPowerLimit ");
719 show_power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18, (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26);
720 }
721 printf(" TEE-IO%c", FLAG(t, PCI_EXP_DEVCAP_TEE_IO));
722 printf("\n");
723
724 w = get_conf_word(d, where + PCI_EXP_DEVCTL);
725 printf("\t\tDevCtl:\tCorrErr%c NonFatalErr%c FatalErr%c UnsupReq%c\n",
726 FLAG(w, PCI_EXP_DEVCTL_CERE),
727 FLAG(w, PCI_EXP_DEVCTL_NFERE),
728 FLAG(w, PCI_EXP_DEVCTL_FERE),
729 FLAG(w, PCI_EXP_DEVCTL_URRE));
730 printf("\t\t\tRlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c",
731 FLAG(w, PCI_EXP_DEVCTL_RELAXED),
732 FLAG(w, PCI_EXP_DEVCTL_EXT_TAG),
733 FLAG(w, PCI_EXP_DEVCTL_PHANTOM),
734 FLAG(w, PCI_EXP_DEVCTL_AUX_PME),
735 FLAG(w, PCI_EXP_DEVCTL_NOSNOOP));
736 if (type == PCI_EXP_TYPE_PCI_BRIDGE)
737 printf(" BrConfRtry%c", FLAG(w, PCI_EXP_DEVCTL_BCRE));
738 if (((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_ROOT_INT_EP)) &&
739 (t & PCI_EXP_DEVCAP_FLRESET))
740 printf(" FLReset%c", FLAG(w, PCI_EXP_DEVCTL_FLRESET));
741 printf("\n\t\t\tMaxPayload %d bytes, MaxReadReq %d bytes\n",
742 128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
743 128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12));
744
745 w = get_conf_word(d, where + PCI_EXP_DEVSTA);
746 printf("\t\tDevSta:\tCorrErr%c NonFatalErr%c FatalErr%c UnsupReq%c AuxPwr%c TransPend%c\n",
747 FLAG(w, PCI_EXP_DEVSTA_CED),
748 FLAG(w, PCI_EXP_DEVSTA_NFED),
749 FLAG(w, PCI_EXP_DEVSTA_FED),
750 FLAG(w, PCI_EXP_DEVSTA_URD),
751 FLAG(w, PCI_EXP_DEVSTA_AUXPD),
752 FLAG(w, PCI_EXP_DEVSTA_TRPND));
753 }
754
link_speed(int speed)755 static char *link_speed(int speed)
756 {
757 switch (speed)
758 {
759 case 1:
760 return "2.5GT/s";
761 case 2:
762 return "5GT/s";
763 case 3:
764 return "8GT/s";
765 case 4:
766 return "16GT/s";
767 case 5:
768 return "32GT/s";
769 case 6:
770 return "64GT/s";
771 case 8:
772 return "128GT/s";
773 default:
774 return "unknown";
775 }
776 }
777
link_compare(int type,int sta,int cap)778 static char *link_compare(int type, int sta, int cap)
779 {
780 if (sta > cap)
781 return " (overdriven)";
782 if (sta == cap)
783 return "";
784 if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_DOWNSTREAM) ||
785 (type == PCI_EXP_TYPE_PCIE_BRIDGE))
786 return "";
787 return " (downgraded)";
788 }
789
aspm_support(int code)790 static char *aspm_support(int code)
791 {
792 switch (code)
793 {
794 case 0:
795 return "not supported";
796 case 1:
797 return "L0s";
798 case 2:
799 return "L1";
800 case 3:
801 return "L0s L1";
802 default:
803 return "unknown";
804 }
805 }
806
aspm_enabled(int code)807 static const char *aspm_enabled(int code)
808 {
809 static const char * const desc[] = { "Disabled", "L0s Enabled", "L1 Enabled", "L0s L1 Enabled" };
810 return desc[code];
811 }
812
cap_express_link(struct device * d,int where,int type)813 static void cap_express_link(struct device *d, int where, int type)
814 {
815 u32 t, aspm, cap_speed, cap_width, sta_speed, sta_width;
816 u16 w;
817
818 t = get_conf_long(d, where + PCI_EXP_LNKCAP);
819 aspm = (t & PCI_EXP_LNKCAP_ASPM) >> 10;
820 cap_speed = t & PCI_EXP_LNKCAP_SPEED;
821 cap_width = (t & PCI_EXP_LNKCAP_WIDTH) >> 4;
822 printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s",
823 t >> 24,
824 link_speed(cap_speed), cap_width,
825 aspm_support(aspm));
826 if (aspm)
827 {
828 printf(", Exit Latency ");
829 if (aspm & 1)
830 printf("L0s %s", latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12));
831 if (aspm & 2)
832 printf("%sL1 %s", (aspm & 1) ? ", " : "",
833 latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
834 }
835 printf("\n");
836 printf("\t\t\tClockPM%c Surprise%c LLActRep%c BwNot%c ASPMOptComp%c\n",
837 FLAG(t, PCI_EXP_LNKCAP_CLOCKPM),
838 FLAG(t, PCI_EXP_LNKCAP_SURPRISE),
839 FLAG(t, PCI_EXP_LNKCAP_DLLA),
840 FLAG(t, PCI_EXP_LNKCAP_LBNC),
841 FLAG(t, PCI_EXP_LNKCAP_AOC));
842
843 w = get_conf_word(d, where + PCI_EXP_LNKCTL);
844 printf("\t\tLnkCtl:\tASPM %s;", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
845 if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
846 (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
847 printf(" RCB %d bytes,", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
848 printf(" LnkDisable%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c FltModeDis%c\n",
849 FLAG(w, PCI_EXP_LNKCTL_DISABLE),
850 FLAG(w, PCI_EXP_LNKCTL_CLOCK),
851 FLAG(w, PCI_EXP_LNKCTL_XSYNCH),
852 FLAG(w, PCI_EXP_LNKCTL_CLOCKPM),
853 FLAG(w, PCI_EXP_LNKCTL_HWAUTWD),
854 FLAG(w, PCI_EXP_LNKCTL_BWMIE),
855 FLAG(w, PCI_EXP_LNKCTL_AUTBWIE),
856 FLAG(w, PCI_EXP_LNKCTL_FLIT_MODE_DIS));
857
858 w = get_conf_word(d, where + PCI_EXP_LNKSTA);
859 sta_speed = w & PCI_EXP_LNKSTA_SPEED;
860 sta_width = (w & PCI_EXP_LNKSTA_WIDTH) >> 4;
861 printf("\t\tLnkSta:\tSpeed %s%s, Width x%d%s\n",
862 link_speed(sta_speed),
863 link_compare(type, sta_speed, cap_speed),
864 sta_width,
865 link_compare(type, sta_width, cap_width));
866 printf("\t\t\tTrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
867 FLAG(w, PCI_EXP_LNKSTA_TR_ERR),
868 FLAG(w, PCI_EXP_LNKSTA_TRAIN),
869 FLAG(w, PCI_EXP_LNKSTA_SL_CLK),
870 FLAG(w, PCI_EXP_LNKSTA_DL_ACT),
871 FLAG(w, PCI_EXP_LNKSTA_BWMGMT),
872 FLAG(w, PCI_EXP_LNKSTA_AUTBW));
873 }
874
indicator(int code)875 static const char *indicator(int code)
876 {
877 static const char * const names[] = { "Unknown", "On", "Blink", "Off" };
878 return names[code];
879 }
880
cap_express_slot(struct device * d,int where)881 static void cap_express_slot(struct device *d, int where)
882 {
883 u32 t;
884 u16 w;
885
886 t = get_conf_long(d, where + PCI_EXP_SLTCAP);
887 printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c\n",
888 FLAG(t, PCI_EXP_SLTCAP_ATNB),
889 FLAG(t, PCI_EXP_SLTCAP_PWRC),
890 FLAG(t, PCI_EXP_SLTCAP_MRL),
891 FLAG(t, PCI_EXP_SLTCAP_ATNI),
892 FLAG(t, PCI_EXP_SLTCAP_PWRI),
893 FLAG(t, PCI_EXP_SLTCAP_HPC),
894 FLAG(t, PCI_EXP_SLTCAP_HPS));
895 printf("\t\t\tSlot #%d, PowerLimit ",
896 (t & PCI_EXP_SLTCAP_PSN) >> 19);
897 show_power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15);
898 printf("; Interlock%c NoCompl%c\n",
899 FLAG(t, PCI_EXP_SLTCAP_INTERLOCK),
900 FLAG(t, PCI_EXP_SLTCAP_NOCMDCOMP));
901
902 w = get_conf_word(d, where + PCI_EXP_SLTCTL);
903 printf("\t\tSltCtl:\tEnable: AttnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c LinkChg%c\n",
904 FLAG(w, PCI_EXP_SLTCTL_ATNB),
905 FLAG(w, PCI_EXP_SLTCTL_PWRF),
906 FLAG(w, PCI_EXP_SLTCTL_MRLS),
907 FLAG(w, PCI_EXP_SLTCTL_PRSD),
908 FLAG(w, PCI_EXP_SLTCTL_CMDC),
909 FLAG(w, PCI_EXP_SLTCTL_HPIE),
910 FLAG(w, PCI_EXP_SLTCTL_LLCHG));
911 printf("\t\t\tControl: AttnInd %s, PwrInd %s, Power%c Interlock%c\n",
912 indicator((w & PCI_EXP_SLTCTL_ATNI) >> 6),
913 indicator((w & PCI_EXP_SLTCTL_PWRI) >> 8),
914 FLAG(w, PCI_EXP_SLTCTL_PWRC),
915 FLAG(w, PCI_EXP_SLTCTL_INTERLOCK));
916
917 w = get_conf_word(d, where + PCI_EXP_SLTSTA);
918 printf("\t\tSltSta:\tStatus: AttnBtn%c PowerFlt%c MRL%c CmdCplt%c PresDet%c Interlock%c\n",
919 FLAG(w, PCI_EXP_SLTSTA_ATNB),
920 FLAG(w, PCI_EXP_SLTSTA_PWRF),
921 FLAG(w, PCI_EXP_SLTSTA_MRL_ST),
922 FLAG(w, PCI_EXP_SLTSTA_CMDC),
923 FLAG(w, PCI_EXP_SLTSTA_PRES),
924 FLAG(w, PCI_EXP_SLTSTA_INTERLOCK));
925 printf("\t\t\tChanged: MRL%c PresDet%c LinkState%c\n",
926 FLAG(w, PCI_EXP_SLTSTA_MRLS),
927 FLAG(w, PCI_EXP_SLTSTA_PRSD),
928 FLAG(w, PCI_EXP_SLTSTA_LLCHG));
929 }
930
cap_express_root(struct device * d,int where)931 static void cap_express_root(struct device *d, int where)
932 {
933 u32 w;
934
935 w = get_conf_word(d, where + PCI_EXP_RTCAP);
936 printf("\t\tRootCap: CRSVisible%c\n",
937 FLAG(w, PCI_EXP_RTCAP_CRSVIS));
938
939 w = get_conf_word(d, where + PCI_EXP_RTCTL);
940 printf("\t\tRootCtl: ErrCorrectable%c ErrNon-Fatal%c ErrFatal%c PMEIntEna%c CRSVisible%c\n",
941 FLAG(w, PCI_EXP_RTCTL_SECEE),
942 FLAG(w, PCI_EXP_RTCTL_SENFEE),
943 FLAG(w, PCI_EXP_RTCTL_SEFEE),
944 FLAG(w, PCI_EXP_RTCTL_PMEIE),
945 FLAG(w, PCI_EXP_RTCTL_CRSVIS));
946
947 w = get_conf_long(d, where + PCI_EXP_RTSTA);
948 printf("\t\tRootSta: PME ReqID %04x, PMEStatus%c PMEPending%c\n",
949 w & PCI_EXP_RTSTA_PME_REQID,
950 FLAG(w, PCI_EXP_RTSTA_PME_STATUS),
951 FLAG(w, PCI_EXP_RTSTA_PME_PENDING));
952 }
953
cap_express_dev2_timeout_range(int type)954 static const char *cap_express_dev2_timeout_range(int type)
955 {
956 /* Decode Completion Timeout Ranges. */
957 switch (type)
958 {
959 case 0:
960 return "Not Supported";
961 case 1:
962 return "Range A";
963 case 2:
964 return "Range B";
965 case 3:
966 return "Range AB";
967 case 6:
968 return "Range BC";
969 case 7:
970 return "Range ABC";
971 case 14:
972 return "Range BCD";
973 case 15:
974 return "Range ABCD";
975 default:
976 return "Unknown";
977 }
978 }
979
cap_express_dev2_timeout_value(int type)980 static const char *cap_express_dev2_timeout_value(int type)
981 {
982 /* Decode Completion Timeout Value. */
983 switch (type)
984 {
985 case 0:
986 return "50us to 50ms";
987 case 1:
988 return "50us to 100us";
989 case 2:
990 return "1ms to 10ms";
991 case 5:
992 return "16ms to 55ms";
993 case 6:
994 return "65ms to 210ms";
995 case 9:
996 return "260ms to 900ms";
997 case 10:
998 return "1s to 3.5s";
999 case 13:
1000 return "4s to 13s";
1001 case 14:
1002 return "17s to 64s";
1003 default:
1004 return "Unknown";
1005 }
1006 }
1007
cap_express_devcap2_obff(int obff)1008 static const char *cap_express_devcap2_obff(int obff)
1009 {
1010 switch (obff)
1011 {
1012 case 1:
1013 return "Via message";
1014 case 2:
1015 return "Via WAKE#";
1016 case 3:
1017 return "Via message/WAKE#";
1018 default:
1019 return "Not Supported";
1020 }
1021 }
1022
cap_express_devcap2_epr(int epr)1023 static const char *cap_express_devcap2_epr(int epr)
1024 {
1025 switch (epr)
1026 {
1027 case 1:
1028 return "Dev Specific";
1029 case 2:
1030 return "Form Factor Dev Specific";
1031 case 3:
1032 return "Reserved";
1033 default:
1034 return "Not Supported";
1035 }
1036 }
1037
cap_express_devcap2_lncls(int lncls)1038 static const char *cap_express_devcap2_lncls(int lncls)
1039 {
1040 switch (lncls)
1041 {
1042 case 1:
1043 return "64byte cachelines";
1044 case 2:
1045 return "128byte cachelines";
1046 case 3:
1047 return "Reserved";
1048 default:
1049 return "Not Supported";
1050 }
1051 }
1052
cap_express_devcap2_tphcomp(int tph)1053 static const char *cap_express_devcap2_tphcomp(int tph)
1054 {
1055 switch (tph)
1056 {
1057 case 1:
1058 return "TPHComp+ ExtTPHComp-";
1059 case 2:
1060 /* Reserved; intentionally left blank */
1061 return "";
1062 case 3:
1063 return "TPHComp+ ExtTPHComp+";
1064 default:
1065 return "TPHComp- ExtTPHComp-";
1066 }
1067 }
1068
cap_express_devctl2_obff(int obff)1069 static const char *cap_express_devctl2_obff(int obff)
1070 {
1071 switch (obff)
1072 {
1073 case 0:
1074 return "Disabled";
1075 case 1:
1076 return "Via message A";
1077 case 2:
1078 return "Via message B";
1079 case 3:
1080 return "Via WAKE#";
1081 default:
1082 return "Unknown";
1083 }
1084 }
1085
1086 static int
device_has_memory_space_bar(struct device * d)1087 device_has_memory_space_bar(struct device *d)
1088 {
1089 struct pci_dev *p = d->dev;
1090 int i, found = 0;
1091
1092 for (i=0; i<6; i++)
1093 if (p->base_addr[i] || p->size[i])
1094 {
1095 if (!(p->base_addr[i] & PCI_BASE_ADDRESS_SPACE_IO))
1096 {
1097 found = 1;
1098 break;
1099 }
1100 }
1101 return found;
1102 }
1103
cap_express_dev2(struct device * d,int where,int type)1104 static void cap_express_dev2(struct device *d, int where, int type)
1105 {
1106 u32 l;
1107 u16 w;
1108 int has_mem_bar = device_has_memory_space_bar(d);
1109
1110 l = get_conf_long(d, where + PCI_EXP_DEVCAP2);
1111 printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c NROPrPrP%c LTR%c",
1112 cap_express_dev2_timeout_range(PCI_EXP_DEVCAP2_TIMEOUT_RANGE(l)),
1113 FLAG(l, PCI_EXP_DEVCAP2_TIMEOUT_DIS),
1114 FLAG(l, PCI_EXP_DEVCAP2_NROPRPRP),
1115 FLAG(l, PCI_EXP_DEVCAP2_LTR));
1116 printf("\n\t\t\t 10BitTagComp%c 10BitTagReq%c OBFF %s, ExtFmt%c EETLPPrefix%c",
1117 FLAG(l, PCI_EXP_DEVCAP2_10BIT_TAG_COMP),
1118 FLAG(l, PCI_EXP_DEVCAP2_10BIT_TAG_REQ),
1119 cap_express_devcap2_obff(PCI_EXP_DEVCAP2_OBFF(l)),
1120 FLAG(l, PCI_EXP_DEVCAP2_EXTFMT),
1121 FLAG(l, PCI_EXP_DEVCAP2_EE_TLP));
1122
1123 if (PCI_EXP_DEVCAP2_EE_TLP == (l & PCI_EXP_DEVCAP2_EE_TLP))
1124 {
1125 printf(", MaxEETLPPrefixes %d",
1126 PCI_EXP_DEVCAP2_MEE_TLP(l) ? PCI_EXP_DEVCAP2_MEE_TLP(l) : 4);
1127 }
1128
1129 printf("\n\t\t\t EmergencyPowerReduction %s, EmergencyPowerReductionInit%c",
1130 cap_express_devcap2_epr(PCI_EXP_DEVCAP2_EPR(l)),
1131 FLAG(l, PCI_EXP_DEVCAP2_EPR_INIT));
1132 printf("\n\t\t\t FRS%c", FLAG(l, PCI_EXP_DEVCAP2_FRS));
1133
1134 if (type == PCI_EXP_TYPE_ROOT_PORT)
1135 printf(" LN System CLS %s,",
1136 cap_express_devcap2_lncls(PCI_EXP_DEVCAP2_LN_CLS(l)));
1137
1138 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ENDPOINT)
1139 printf(" %s", cap_express_devcap2_tphcomp(PCI_EXP_DEVCAP2_TPH_COMP(l)));
1140
1141 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
1142 printf(" ARIFwd%c\n", FLAG(l, PCI_EXP_DEVCAP2_ARI));
1143 else
1144 printf("\n");
1145 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1146 type == PCI_EXP_TYPE_DOWNSTREAM || has_mem_bar)
1147 {
1148 printf("\t\t\t AtomicOpsCap:");
1149 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1150 type == PCI_EXP_TYPE_DOWNSTREAM)
1151 printf(" Routing%c", FLAG(l, PCI_EXP_DEVCAP2_ATOMICOP_ROUTING));
1152 if (type == PCI_EXP_TYPE_ROOT_PORT || has_mem_bar)
1153 printf(" 32bit%c 64bit%c 128bitCAS%c",
1154 FLAG(l, PCI_EXP_DEVCAP2_32BIT_ATOMICOP_COMP),
1155 FLAG(l, PCI_EXP_DEVCAP2_64BIT_ATOMICOP_COMP),
1156 FLAG(l, PCI_EXP_DEVCAP2_128BIT_CAS_COMP));
1157 printf("\n");
1158 }
1159
1160 w = get_conf_word(d, where + PCI_EXP_DEVCTL2);
1161 printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c",
1162 cap_express_dev2_timeout_value(PCI_EXP_DEVCTL2_TIMEOUT_VALUE(w)),
1163 FLAG(w, PCI_EXP_DEVCTL2_TIMEOUT_DIS));
1164 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
1165 printf(" ARIFwd%c\n", FLAG(w, PCI_EXP_DEVCTL2_ARI));
1166 else
1167 printf("\n");
1168 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1169 type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ENDPOINT ||
1170 type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END)
1171 {
1172 printf("\t\t\t AtomicOpsCtl:");
1173 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ENDPOINT ||
1174 type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END)
1175 printf(" ReqEn%c", FLAG(w, PCI_EXP_DEVCTL2_ATOMICOP_REQUESTER_EN));
1176 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1177 type == PCI_EXP_TYPE_DOWNSTREAM)
1178 printf(" EgressBlck%c", FLAG(w, PCI_EXP_DEVCTL2_ATOMICOP_EGRESS_BLOCK));
1179 printf("\n");
1180 }
1181 printf("\t\t\t IDOReq%c IDOCompl%c LTR%c EmergencyPowerReductionReq%c\n",
1182 FLAG(w, PCI_EXP_DEVCTL2_IDO_REQ_EN),
1183 FLAG(w, PCI_EXP_DEVCTL2_IDO_CMP_EN),
1184 FLAG(w, PCI_EXP_DEVCTL2_LTR),
1185 FLAG(w, PCI_EXP_DEVCTL2_EPR_REQ));
1186 printf("\t\t\t 10BitTagReq%c OBFF %s, EETLPPrefixBlk%c\n",
1187 FLAG(w, PCI_EXP_DEVCTL2_10BIT_TAG_REQ),
1188 cap_express_devctl2_obff(PCI_EXP_DEVCTL2_OBFF(w)),
1189 FLAG(w, PCI_EXP_DEVCTL2_EE_TLP_BLK));
1190 }
1191
cap_express_link2_speed_cap(int vector)1192 static const char *cap_express_link2_speed_cap(int vector)
1193 {
1194 /*
1195 * Per PCIe r5.0, sec 8.2.1, a device must support 2.5GT/s and is not
1196 * permitted to skip support for any data rates between 2.5GT/s and the
1197 * highest supported rate.
1198 */
1199 if (vector & 0x40)
1200 return "2.5-128GT/s";
1201 if (vector & 0x20)
1202 return "2.5-64GT/s";
1203 if (vector & 0x10)
1204 return "2.5-32GT/s";
1205 if (vector & 0x08)
1206 return "2.5-16GT/s";
1207 if (vector & 0x04)
1208 return "2.5-8GT/s";
1209 if (vector & 0x02)
1210 return "2.5-5GT/s";
1211 if (vector & 0x01)
1212 return "2.5GT/s";
1213
1214 return "Unknown";
1215 }
1216
cap_express_link2_speed(int type)1217 static const char *cap_express_link2_speed(int type)
1218 {
1219 switch (type)
1220 {
1221 case 0: /* hardwire to 0 means only the 2.5GT/s is supported */
1222 case 1:
1223 return "2.5GT/s";
1224 case 2:
1225 return "5GT/s";
1226 case 3:
1227 return "8GT/s";
1228 case 4:
1229 return "16GT/s";
1230 case 5:
1231 return "32GT/s";
1232 case 6:
1233 return "64GT/s";
1234 case 8:
1235 return "128GT/s";
1236 default:
1237 return "Unknown";
1238 }
1239 }
1240
cap_express_link2_deemphasis(int type)1241 static const char *cap_express_link2_deemphasis(int type)
1242 {
1243 switch (type)
1244 {
1245 case 0:
1246 return "-6dB";
1247 case 1:
1248 return "-3.5dB";
1249 default:
1250 return "Unknown";
1251 }
1252 }
1253
cap_express_link2_compliance_preset(int type)1254 static const char *cap_express_link2_compliance_preset(int type)
1255 {
1256 switch (type)
1257 {
1258 case 0:
1259 return "-6dB de-emphasis, 0dB preshoot";
1260 case 1:
1261 return "-3.5dB de-emphasis, 0dB preshoot";
1262 case 2:
1263 return "-4.4dB de-emphasis, 0dB preshoot";
1264 case 3:
1265 return "-2.5dB de-emphasis, 0dB preshoot";
1266 case 4:
1267 return "0dB de-emphasis, 0dB preshoot";
1268 case 5:
1269 return "0dB de-emphasis, 1.9dB preshoot";
1270 case 6:
1271 return "0dB de-emphasis, 2.5dB preshoot";
1272 case 7:
1273 return "-6.0dB de-emphasis, 3.5dB preshoot";
1274 case 8:
1275 return "-3.5dB de-emphasis, 3.5dB preshoot";
1276 case 9:
1277 return "0dB de-emphasis, 3.5dB preshoot";
1278 default:
1279 return "Unknown";
1280 }
1281 }
1282
cap_express_link2_transmargin(int type)1283 static const char *cap_express_link2_transmargin(int type)
1284 {
1285 switch (type)
1286 {
1287 case 0:
1288 return "Normal Operating Range";
1289 case 1:
1290 return "800-1200mV(full-swing)/400-700mV(half-swing)";
1291 case 2:
1292 case 3:
1293 case 4:
1294 case 5:
1295 return "200-400mV(full-swing)/100-200mV(half-swing)";
1296 default:
1297 return "Unknown";
1298 }
1299 }
1300
cap_express_link2_crosslink_res(int crosslink)1301 static const char *cap_express_link2_crosslink_res(int crosslink)
1302 {
1303 switch (crosslink)
1304 {
1305 case 0:
1306 return "unsupported";
1307 case 1:
1308 return "Upstream Port";
1309 case 2:
1310 return "Downstream Port";
1311 default:
1312 return "incomplete";
1313 }
1314 }
1315
cap_express_link2_component(int presence)1316 static const char *cap_express_link2_component(int presence)
1317 {
1318 switch (presence)
1319 {
1320 case 0:
1321 return "Link Down - Not Determined";
1322 case 1:
1323 return "Link Down - Not Present";
1324 case 2:
1325 return "Link Down - Present";
1326 case 4:
1327 return "Link Up - Present";
1328 case 5:
1329 return "Link Up - Present and DRS Received";
1330 default:
1331 return "Reserved";
1332 }
1333 }
1334
cap_express_link2(struct device * d,int where,int type)1335 static void cap_express_link2(struct device *d, int where, int type)
1336 {
1337 u32 l = 0;
1338 u16 w;
1339
1340 if (!((type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_LEG_END) &&
1341 (d->dev->dev != 0 || d->dev->func != 0))) {
1342 /* Link Capabilities 2 was reserved before PCIe r3.0 */
1343 l = get_conf_long(d, where + PCI_EXP_LNKCAP2);
1344 if (l) {
1345 printf("\t\tLnkCap2: Supported Link Speeds: %s, Crosslink%c "
1346 "Retimer%c 2Retimers%c DRS%c\n",
1347 cap_express_link2_speed_cap(PCI_EXP_LNKCAP2_SPEED(l)),
1348 FLAG(l, PCI_EXP_LNKCAP2_CROSSLINK),
1349 FLAG(l, PCI_EXP_LNKCAP2_RETIMER),
1350 FLAG(l, PCI_EXP_LNKCAP2_2RETIMERS),
1351 FLAG(l, PCI_EXP_LNKCAP2_DRS));
1352 }
1353
1354 w = get_conf_word(d, where + PCI_EXP_LNKCTL2);
1355 printf("\t\tLnkCtl2: Target Link Speed: %s, EnterCompliance%c SpeedDis%c",
1356 cap_express_link2_speed(PCI_EXP_LNKCTL2_SPEED(w)),
1357 FLAG(w, PCI_EXP_LNKCTL2_CMPLNC),
1358 FLAG(w, PCI_EXP_LNKCTL2_SPEED_DIS));
1359 if (type == PCI_EXP_TYPE_DOWNSTREAM)
1360 printf(", Selectable De-emphasis: %s",
1361 cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_DEEMPHASIS(w)));
1362 printf("\n"
1363 "\t\t\t Transmit Margin: %s, EnterModifiedCompliance%c ComplianceSOS%c\n"
1364 "\t\t\t Compliance Preset/De-emphasis: %s\n",
1365 cap_express_link2_transmargin(PCI_EXP_LNKCTL2_MARGIN(w)),
1366 FLAG(w, PCI_EXP_LNKCTL2_MOD_CMPLNC),
1367 FLAG(w, PCI_EXP_LNKCTL2_CMPLNC_SOS),
1368 cap_express_link2_compliance_preset(PCI_EXP_LNKCTL2_COM_DEEMPHASIS(w)));
1369 }
1370
1371 w = get_conf_word(d, where + PCI_EXP_LNKSTA2);
1372 printf("\t\tLnkSta2: Current De-emphasis Level: %s, EqualizationComplete%c EqualizationPhase1%c\n"
1373 "\t\t\t EqualizationPhase2%c EqualizationPhase3%c LinkEqualizationRequest%c\n"
1374 "\t\t\t Retimer%c 2Retimers%c CrosslinkRes: %s, FltMode%c",
1375 cap_express_link2_deemphasis(PCI_EXP_LINKSTA2_DEEMPHASIS(w)),
1376 FLAG(w, PCI_EXP_LINKSTA2_EQU_COMP),
1377 FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE1),
1378 FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE2),
1379 FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE3),
1380 FLAG(w, PCI_EXP_LINKSTA2_EQU_REQ),
1381 FLAG(w, PCI_EXP_LINKSTA2_RETIMER),
1382 FLAG(w, PCI_EXP_LINKSTA2_2RETIMERS),
1383 cap_express_link2_crosslink_res(PCI_EXP_LINKSTA2_CROSSLINK(w)),
1384 FLAG(w, PCI_EXP_LINKSTA2_FLIT_MODE));
1385
1386 if (exp_downstream_port(type) && (l & PCI_EXP_LNKCAP2_DRS)) {
1387 printf(", DRS%c\n"
1388 "\t\t\t DownstreamComp: %s\n",
1389 FLAG(w, PCI_EXP_LINKSTA2_DRS_RCVD),
1390 cap_express_link2_component(PCI_EXP_LINKSTA2_COMPONENT(w)));
1391 } else
1392 printf("\n");
1393 }
1394
cap_express_slot2(struct device * d UNUSED,int where UNUSED)1395 static void cap_express_slot2(struct device *d UNUSED, int where UNUSED)
1396 {
1397 /* No capabilities that require this field in PCIe rev2.0 spec. */
1398 }
1399
cap_express_link_rcd(struct device * d)1400 static void cap_express_link_rcd(struct device *d)
1401 {
1402 u32 t, aspm, cap_speed, cap_width, sta_speed, sta_width;
1403 u16 w;
1404 struct pci_dev *pdev = d->dev;
1405
1406 if (!pdev->rcd_link_cap)
1407 return;
1408
1409 t = pdev->rcd_link_cap;
1410 aspm = (t & PCI_EXP_LNKCAP_ASPM) >> 10;
1411 cap_speed = t & PCI_EXP_LNKCAP_SPEED;
1412 cap_width = (t & PCI_EXP_LNKCAP_WIDTH) >> 4;
1413 printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s",
1414 t >> 24,
1415 link_speed(cap_speed), cap_width,
1416 aspm_support(aspm));
1417 if (aspm)
1418 {
1419 printf(", Exit Latency ");
1420 if (aspm & 1)
1421 printf("L0s %s", latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12));
1422 if (aspm & 2)
1423 printf("%sL1 %s", (aspm & 1) ? ", " : "",
1424 latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
1425 }
1426 printf("\n");
1427 printf("\t\t\tClockPM%c Surprise%c LLActRep%c BwNot%c ASPMOptComp%c\n",
1428 FLAG(t, PCI_EXP_LNKCAP_CLOCKPM),
1429 FLAG(t, PCI_EXP_LNKCAP_SURPRISE),
1430 FLAG(t, PCI_EXP_LNKCAP_DLLA),
1431 FLAG(t, PCI_EXP_LNKCAP_LBNC),
1432 FLAG(t, PCI_EXP_LNKCAP_AOC));
1433
1434 w = pdev->rcd_link_ctrl;
1435 printf("\t\tLnkCtl:\tASPM %s;", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
1436 printf(" Disabled%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
1437 FLAG(w, PCI_EXP_LNKCTL_DISABLE),
1438 FLAG(w, PCI_EXP_LNKCTL_CLOCK),
1439 FLAG(w, PCI_EXP_LNKCTL_XSYNCH),
1440 FLAG(w, PCI_EXP_LNKCTL_CLOCKPM),
1441 FLAG(w, PCI_EXP_LNKCTL_HWAUTWD),
1442 FLAG(w, PCI_EXP_LNKCTL_BWMIE),
1443 FLAG(w, PCI_EXP_LNKCTL_AUTBWIE));
1444
1445 w = pdev->rcd_link_status;
1446 sta_speed = w & PCI_EXP_LNKSTA_SPEED;
1447 sta_width = (w & PCI_EXP_LNKSTA_WIDTH) >> 4;
1448 printf("\t\tLnkSta:\tSpeed %s%s, Width x%d%s\n",
1449 link_speed(sta_speed),
1450 link_compare(PCI_EXP_TYPE_ROOT_INT_EP, sta_speed, cap_speed),
1451 sta_width,
1452 link_compare(PCI_EXP_TYPE_ROOT_INT_EP, sta_width, cap_width));
1453 printf("\t\t\tTrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
1454 FLAG(w, PCI_EXP_LNKSTA_TR_ERR),
1455 FLAG(w, PCI_EXP_LNKSTA_TRAIN),
1456 FLAG(w, PCI_EXP_LNKSTA_SL_CLK),
1457 FLAG(w, PCI_EXP_LNKSTA_DL_ACT),
1458 FLAG(w, PCI_EXP_LNKSTA_BWMGMT),
1459 FLAG(w, PCI_EXP_LNKSTA_AUTBW));
1460 }
1461
1462 static int
cap_express(struct device * d,int where,int cap)1463 cap_express(struct device *d, int where, int cap)
1464 {
1465 int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4;
1466 int size;
1467 int slot = 0;
1468 int link = 1;
1469
1470 printf("Express ");
1471 if (verbose >= 2)
1472 printf("(v%d) ", cap & PCI_EXP_FLAGS_VERS);
1473 switch (type)
1474 {
1475 case PCI_EXP_TYPE_ENDPOINT:
1476 printf("Endpoint");
1477 break;
1478 case PCI_EXP_TYPE_LEG_END:
1479 printf("Legacy Endpoint");
1480 break;
1481 case PCI_EXP_TYPE_ROOT_PORT:
1482 slot = cap & PCI_EXP_FLAGS_SLOT;
1483 printf("Root Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1484 break;
1485 case PCI_EXP_TYPE_UPSTREAM:
1486 printf("Upstream Port");
1487 break;
1488 case PCI_EXP_TYPE_DOWNSTREAM:
1489 slot = cap & PCI_EXP_FLAGS_SLOT;
1490 printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1491 break;
1492 case PCI_EXP_TYPE_PCI_BRIDGE:
1493 printf("PCI-Express to PCI/PCI-X Bridge");
1494 break;
1495 case PCI_EXP_TYPE_PCIE_BRIDGE:
1496 slot = cap & PCI_EXP_FLAGS_SLOT;
1497 printf("PCI/PCI-X to PCI-Express Bridge (Slot%c)",
1498 FLAG(cap, PCI_EXP_FLAGS_SLOT));
1499 break;
1500 case PCI_EXP_TYPE_ROOT_INT_EP:
1501 link = 0;
1502 printf("Root Complex Integrated Endpoint");
1503 break;
1504 case PCI_EXP_TYPE_ROOT_EC:
1505 link = 0;
1506 printf("Root Complex Event Collector");
1507 break;
1508 default:
1509 printf("Unknown type %d", type);
1510 }
1511 printf(", IntMsgNum %d", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
1512 if (cap & PCI_EXP_FLAGS_FLIT_MODE)
1513 printf(", FLIT Mode Supported\n");
1514 else
1515 printf("\n");
1516
1517 if (verbose < 2)
1518 return type;
1519
1520 size = 16;
1521 if (slot)
1522 size = 24;
1523 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC)
1524 size = 32;
1525 if (!config_fetch(d, where + PCI_EXP_DEVCAP, size))
1526 return type;
1527
1528 cap_express_dev(d, where, type);
1529 if (link)
1530 cap_express_link(d, where, type);
1531 else if (d->dev->rcd_link_cap)
1532 cap_express_link_rcd(d);
1533
1534 if (slot)
1535 cap_express_slot(d, where);
1536 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC)
1537 cap_express_root(d, where);
1538
1539 if ((cap & PCI_EXP_FLAGS_VERS) < 2)
1540 return type;
1541
1542 size = 16;
1543 if (slot)
1544 size = 24;
1545 if (!config_fetch(d, where + PCI_EXP_DEVCAP2, size))
1546 return type;
1547
1548 cap_express_dev2(d, where, type);
1549 if (link)
1550 cap_express_link2(d, where, type);
1551 if (slot)
1552 cap_express_slot2(d, where);
1553 return type;
1554 }
1555
1556 static void
cap_msix(struct device * d,int where,int cap)1557 cap_msix(struct device *d, int where, int cap)
1558 {
1559 u32 off;
1560
1561 printf("MSI-X: Enable%c Count=%d Masked%c\n",
1562 FLAG(cap, PCI_MSIX_ENABLE),
1563 (cap & PCI_MSIX_TABSIZE) + 1,
1564 FLAG(cap, PCI_MSIX_MASK));
1565 if (verbose < 2 || !config_fetch(d, where + PCI_MSIX_TABLE, 8))
1566 return;
1567
1568 off = get_conf_long(d, where + PCI_MSIX_TABLE);
1569 printf("\t\tVector table: BAR=%d offset=%08x\n",
1570 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1571 off = get_conf_long(d, where + PCI_MSIX_PBA);
1572 printf("\t\tPBA: BAR=%d offset=%08x\n",
1573 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1574 }
1575
1576 static void
cap_slotid(int cap)1577 cap_slotid(int cap)
1578 {
1579 int esr = cap & 0xff;
1580 int chs = cap >> 8;
1581
1582 printf("Slot ID: %d slots, First%c, chassis %02x\n",
1583 esr & PCI_SID_ESR_NSLOTS,
1584 FLAG(esr, PCI_SID_ESR_FIC),
1585 chs);
1586 }
1587
1588 static void
cap_ssvid(struct device * d,int where)1589 cap_ssvid(struct device *d, int where)
1590 {
1591 u16 subsys_v, subsys_d;
1592 char ssnamebuf[256];
1593
1594 if (!config_fetch(d, where, 8))
1595 return;
1596 subsys_v = get_conf_word(d, where + PCI_SSVID_VENDOR);
1597 subsys_d = get_conf_word(d, where + PCI_SSVID_DEVICE);
1598 printf("Subsystem: %s\n",
1599 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
1600 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1601 d->dev->vendor_id, d->dev->device_id, subsys_v, subsys_d));
1602 }
1603
1604 static void
cap_debug_port(int cap)1605 cap_debug_port(int cap)
1606 {
1607 int bar = cap >> 13;
1608 int pos = cap & 0x1fff;
1609 printf("Debug port: BAR=%d offset=%04x\n", bar, pos);
1610 }
1611
1612 static void
cap_af(struct device * d,int where)1613 cap_af(struct device *d, int where)
1614 {
1615 u8 reg;
1616
1617 printf("PCI Advanced Features\n");
1618 if (verbose < 2 || !config_fetch(d, where + PCI_AF_CAP, 3))
1619 return;
1620
1621 reg = get_conf_byte(d, where + PCI_AF_CAP);
1622 printf("\t\tAFCap: TP%c FLR%c\n", FLAG(reg, PCI_AF_CAP_TP),
1623 FLAG(reg, PCI_AF_CAP_FLR));
1624 reg = get_conf_byte(d, where + PCI_AF_CTRL);
1625 printf("\t\tAFCtrl: FLR%c\n", FLAG(reg, PCI_AF_CTRL_FLR));
1626 reg = get_conf_byte(d, where + PCI_AF_STATUS);
1627 printf("\t\tAFStatus: TP%c\n", FLAG(reg, PCI_AF_STATUS_TP));
1628 }
1629
1630 static void
cap_sata_hba(struct device * d,int where,int cap)1631 cap_sata_hba(struct device *d, int where, int cap)
1632 {
1633 u32 bars;
1634 int bar;
1635
1636 printf("SATA HBA v%d.%d", BITS(cap, 4, 4), BITS(cap, 0, 4));
1637 if (verbose < 2 || !config_fetch(d, where + PCI_SATA_HBA_BARS, 4))
1638 {
1639 printf("\n");
1640 return;
1641 }
1642
1643 bars = get_conf_long(d, where + PCI_SATA_HBA_BARS);
1644 bar = BITS(bars, 0, 4);
1645 if (bar >= 4 && bar <= 9)
1646 printf(" BAR%d Offset=%08x\n", bar - 4, BITS(bars, 4, 20));
1647 else if (bar == 15)
1648 printf(" InCfgSpace\n");
1649 else
1650 printf(" BAR??%d\n", bar);
1651 }
1652
cap_ea_property(int p,int is_secondary)1653 static const char *cap_ea_property(int p, int is_secondary)
1654 {
1655 switch (p) {
1656 case 0x00:
1657 return "memory space, non-prefetchable";
1658 case 0x01:
1659 return "memory space, prefetchable";
1660 case 0x02:
1661 return "I/O space";
1662 case 0x03:
1663 return "VF memory space, prefetchable";
1664 case 0x04:
1665 return "VF memory space, non-prefetchable";
1666 case 0x05:
1667 return "allocation behind bridge, non-prefetchable memory";
1668 case 0x06:
1669 return "allocation behind bridge, prefetchable memory";
1670 case 0x07:
1671 return "allocation behind bridge, I/O space";
1672 case 0xfd:
1673 return "memory space resource unavailable for use";
1674 case 0xfe:
1675 return "I/O space resource unavailable for use";
1676 case 0xff:
1677 if (is_secondary)
1678 return "entry unavailable for use, PrimaryProperties should be used";
1679 else
1680 return "entry unavailable for use";
1681 default:
1682 return NULL;
1683 }
1684 }
1685
cap_ea(struct device * d,int where,int cap)1686 static void cap_ea(struct device *d, int where, int cap)
1687 {
1688 int entry;
1689 int entry_base = where + 4;
1690 int num_entries = BITS(cap, 0, 6);
1691 u8 htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1692
1693 printf("Enhanced Allocation (EA): NumEntries=%u", num_entries);
1694 if (htype == PCI_HEADER_TYPE_BRIDGE) {
1695 byte fixed_sub, fixed_sec;
1696
1697 entry_base += 4;
1698 if (!config_fetch(d, where + 4, 2)) {
1699 printf("\n");
1700 return;
1701 }
1702 fixed_sec = get_conf_byte(d, where + PCI_EA_CAP_TYPE1_SECONDARY);
1703 fixed_sub = get_conf_byte(d, where + PCI_EA_CAP_TYPE1_SUBORDINATE);
1704 printf(", secondary=%d, subordinate=%d", fixed_sec, fixed_sub);
1705 }
1706 printf("\n");
1707 if (verbose < 2)
1708 return;
1709
1710 for (entry = 0; entry < num_entries; entry++) {
1711 int max_offset_high_pos, has_base_high, has_max_offset_high;
1712 u32 entry_header;
1713 u32 base, max_offset;
1714 int es, bei, pp, sp;
1715 const char *prop_text;
1716
1717 if (!config_fetch(d, entry_base, 4))
1718 return;
1719 entry_header = get_conf_long(d, entry_base);
1720 es = BITS(entry_header, 0, 3);
1721 bei = BITS(entry_header, 4, 4);
1722 pp = BITS(entry_header, 8, 8);
1723 sp = BITS(entry_header, 16, 8);
1724 if (!config_fetch(d, entry_base + 4, es * 4))
1725 return;
1726 printf("\t\tEntry %u: Enable%c Writable%c EntrySize=%u\n", entry,
1727 FLAG(entry_header, PCI_EA_CAP_ENT_ENABLE),
1728 FLAG(entry_header, PCI_EA_CAP_ENT_WRITABLE), es);
1729 printf("\t\t\t BAR Equivalent Indicator: ");
1730 switch (bei) {
1731 case 0:
1732 case 1:
1733 case 2:
1734 case 3:
1735 case 4:
1736 case 5:
1737 printf("BAR %u", bei);
1738 break;
1739 case 6:
1740 printf("resource behind function");
1741 break;
1742 case 7:
1743 printf("not indicated");
1744 break;
1745 case 8:
1746 printf("expansion ROM");
1747 break;
1748 case 9:
1749 case 10:
1750 case 11:
1751 case 12:
1752 case 13:
1753 case 14:
1754 printf("VF-BAR %u", bei - 9);
1755 break;
1756 default:
1757 printf("reserved");
1758 break;
1759 }
1760 printf("\n");
1761
1762 prop_text = cap_ea_property(pp, 0);
1763 printf("\t\t\t PrimaryProperties: ");
1764 if (prop_text)
1765 printf("%s\n", prop_text);
1766 else
1767 printf("[%02x]\n", pp);
1768
1769 prop_text = cap_ea_property(sp, 1);
1770 printf("\t\t\t SecondaryProperties: ");
1771 if (prop_text)
1772 printf("%s\n", prop_text);
1773 else
1774 printf("[%02x]\n", sp);
1775
1776 base = get_conf_long(d, entry_base + 4);
1777 has_base_high = ((base & 2) != 0);
1778 base &= ~3;
1779
1780 max_offset = get_conf_long(d, entry_base + 8);
1781 has_max_offset_high = ((max_offset & 2) != 0);
1782 max_offset |= 3;
1783 max_offset_high_pos = entry_base + 12;
1784
1785 printf("\t\t\t Base: ");
1786 if (has_base_high) {
1787 u32 base_high = get_conf_long(d, entry_base + 12);
1788
1789 printf("%x", base_high);
1790 max_offset_high_pos += 4;
1791 }
1792 printf("%08x\n", base);
1793
1794 printf("\t\t\t MaxOffset: ");
1795 if (has_max_offset_high) {
1796 u32 max_offset_high = get_conf_long(d, max_offset_high_pos);
1797
1798 printf("%x", max_offset_high);
1799 }
1800 printf("%08x\n", max_offset);
1801
1802 entry_base += 4 + 4 * es;
1803 }
1804 }
1805
1806 void
show_caps(struct device * d,int where)1807 show_caps(struct device *d, int where)
1808 {
1809 int can_have_ext_caps = 0;
1810 int type = -1;
1811
1812 if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST)
1813 {
1814 byte been_there[256];
1815 where = get_conf_byte(d, where) & ~3;
1816 memset(been_there, 0, 256);
1817 while (where)
1818 {
1819 int id, next, cap;
1820 printf("\tCapabilities: ");
1821 if (!config_fetch(d, where, 4))
1822 {
1823 puts("<access denied>");
1824 break;
1825 }
1826 id = get_conf_byte(d, where + PCI_CAP_LIST_ID);
1827 next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT) & ~3;
1828 cap = get_conf_word(d, where + PCI_CAP_FLAGS);
1829 printf("[%02x] ", where);
1830 if (been_there[where]++)
1831 {
1832 printf("<chain looped>\n");
1833 break;
1834 }
1835 if (id == 0xff)
1836 {
1837 printf("<chain broken>\n");
1838 break;
1839 }
1840 switch (id)
1841 {
1842 case PCI_CAP_ID_NULL:
1843 printf("Null\n");
1844 break;
1845 case PCI_CAP_ID_PM:
1846 cap_pm(d, where, cap);
1847 break;
1848 case PCI_CAP_ID_AGP:
1849 cap_agp(d, where, cap);
1850 break;
1851 case PCI_CAP_ID_VPD:
1852 cap_vpd(d);
1853 break;
1854 case PCI_CAP_ID_SLOTID:
1855 cap_slotid(cap);
1856 break;
1857 case PCI_CAP_ID_MSI:
1858 cap_msi(d, where, cap);
1859 break;
1860 case PCI_CAP_ID_CHSWP:
1861 printf("CompactPCI hot-swap <?>\n");
1862 break;
1863 case PCI_CAP_ID_PCIX:
1864 cap_pcix(d, where);
1865 can_have_ext_caps = 1;
1866 break;
1867 case PCI_CAP_ID_HT:
1868 cap_ht(d, where, cap);
1869 break;
1870 case PCI_CAP_ID_VNDR:
1871 show_vendor_caps(d, where, cap);
1872 break;
1873 case PCI_CAP_ID_DBG:
1874 cap_debug_port(cap);
1875 break;
1876 case PCI_CAP_ID_CCRC:
1877 printf("CompactPCI central resource control <?>\n");
1878 break;
1879 case PCI_CAP_ID_HOTPLUG:
1880 printf("Hot-plug capable\n");
1881 break;
1882 case PCI_CAP_ID_SSVID:
1883 cap_ssvid(d, where);
1884 break;
1885 case PCI_CAP_ID_AGP3:
1886 printf("AGP3 <?>\n");
1887 break;
1888 case PCI_CAP_ID_SECURE:
1889 printf("Secure device <?>\n");
1890 break;
1891 case PCI_CAP_ID_EXP:
1892 type = cap_express(d, where, cap);
1893 can_have_ext_caps = 1;
1894 break;
1895 case PCI_CAP_ID_MSIX:
1896 cap_msix(d, where, cap);
1897 break;
1898 case PCI_CAP_ID_SATA:
1899 cap_sata_hba(d, where, cap);
1900 break;
1901 case PCI_CAP_ID_AF:
1902 cap_af(d, where);
1903 break;
1904 case PCI_CAP_ID_EA:
1905 cap_ea(d, where, cap);
1906 break;
1907 default:
1908 printf("Capability ID %#02x [%04x]\n", id, cap);
1909 }
1910 where = next;
1911 }
1912 }
1913 if (can_have_ext_caps)
1914 show_ext_caps(d, type);
1915 }
1916