| /llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/ |
| H A D | vec-move-03.ll | 1 ; Test vector stores.
5 ; Test v16i8 stores.
14 ; Test v8i16 stores.
23 ; Test v4i32 stores.
32 ; Test v2i64 stores.
41 ; Test v4f32 stores.
50 ; Test v2f64 stores.
113 ; Test v2i8 stores.
122 ; Test v4i8 stores.
131 ; Test v8i8 stores.
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| H A D | vec-eswap-02.ll | 1 ; Test stores of element-swapped vector elements.
5 ; Test v16i8 stores.
19 ; Test v8i16 stores.
31 ; Test v4i32 stores.
42 ; Test v2i64 stores.
53 ; Test v4f32 stores.
64 ; Test v2f64 stores.
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| H A D | vec-bswap-02.ll | 1 ; Test stores of byte-swapped vector elements.
9 ; Test v8i16 stores.
19 ; Test v4i32 stores.
29 ; Test v2i64 stores.
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| /llvm-project-15.0.7/llvm/test/Transforms/LowerMatrixIntrinsics/ |
| H A D | remarks-inlining.ll | 50 ; CHECK-LABEL: remark: load.h:41:43: Lowered with 0 stores, 10 loads, 0 compute ops, 0 exposed tran…
53 ; CHECK-LABEL: remark: load.h:41:43: Lowered with 0 stores, 10 loads, 0 compute ops, 0 exposed tran…
56 ; CHECK-LABEL: remark: load.h:41:11: Lowered with 0 stores, 1 loads, 0 compute ops, 0 exposed trans…
59 ; CHECK-LABEL: remark: assign.h:32:43: Lowered with 0 stores, 10 loads, 0 compute ops, 0 exposed tr…
62 ; CHECK-LABEL: remark: assign.h:32:43: Lowered with 0 stores, 10 loads, 0 compute ops, 0 exposed tr…
65 ; CHECK-LABEL: remark: toplevel.c:410:0: Lowered with 10 stores, 20 loads, 10 compute ops, 0 expose…
72 ; CHECK-LABEL: remark: toplevel.c:510:0: Lowered with 2 stores, 1 loads, 4 compute ops, 1 exposed t…
77 ; CHECK-LABEL: remark: add.h:66:11: Lowered with 0 stores, 0 loads, 10 compute ops, 0 exposed trans…
82 ; CHECK-LABEL: remark: store.h:10:11: Lowered with 10 stores, 0 loads, 0 compute ops, 0 exposed tra…
87 ; CHECK-LABEL: remark: store.h:66:11: Lowered with 2 stores, 0 loads, 0 compute ops, 0 exposed tran…
[all …]
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| H A D | remarks.ll | 7 ; CHECK-LABEL: remark: test.h:40:20: Lowered with 6 stores, 6 loads, 24 compute ops
18 ; CHECK-LABEL: remark: test.h:50:20: Lowered with 2 stores, 12 loads, 22 compute ops
32 ; CHECK-LABEL: remark: test.h:60:20: Lowered with 6 stores, 6 loads, 0 compute ops
42 ; CHECK-LABEL: remark: test.h:70:20: Lowered with 6 stores, 6 loads, 0 compute ops
53 ; CHECK-LABEL: remark: test.h:80:20: Lowered with 6 stores, 6 loads, 12 compute ops
71 ; CHECK-LABEL: remark: test.h:90:20: Lowered with 6 stores, 6 loads, 12 compute ops
80 ; CHECK-NEXT: remark: test.h:90:20: Lowered with 2 stores, 12 loads, 22 compute ops
101 ; CHECK-LABEL: remark: test.h:100:20: Lowered with 6 stores, 6 loads, 12 compute ops
118 ; CHECK-LABEL: remark: test.h:30:20: Lowered with 10 stores, 9 loads, 30 compute ops
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| H A D | remarks-shared-subtrees.ll | 16 ; YAML-NEXT: - String: ' stores, '
25 ; YAML-NEXT: - String: ' stores, '
46 ; YAML-NEXT: - String: ' stores, '
55 ; YAML-NEXT: - String: ' stores, '
73 ; STDERR-LABEL: remark: test.cpp:35:71: Lowered with 4 stores, 0 loads, 0 compute ops,
74 ; STDERR-NEXT: additionally 0 stores, 4 loads, 16 compute ops are shared with other expressions
81 ; STDERR-LABEL: remark: test.cpp:35:45: Lowered with 30 stores, 45 loads, 120 compute ops,
82 ; STDERR-NEXT: additionally 0 stores, 4 loads, 16 compute ops are shared with other expressions
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| /llvm-project-15.0.7/llvm/test/Instrumentation/MemorySanitizer/ |
| H A D | check-constant-shadow.ll | 20 ; This function stores known initialized value.
21 ; Expect 2 stores: one for the shadow (0), one for the value (42), but no origin.
37 ; This function stores known uninitialized value.
38 ; Expect 3 stores: shadow, value and origin.
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| H A D | store-long-origin.ll | 8 ; Test origin for longer stores.
29 ; Two 4-byte origin stores
46 ; Three 4-byte origin stores
64 ; 8-byte + 4-byte origin stores
81 ; 3 8-byte origin stores
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| /llvm-project-15.0.7/llvm/docs/ |
| H A D | Atomics.rst | 36 pair of volatile stores. On the other hand, a non-volatile non-atomic load can
54 because any optimization dealing with stores needs to be aware of it.
101 For cases where simple loads and stores are not sufficient, LLVM provides
196 stores.)
203 rematerializing a load, and turning loads and stores into a memcpy
252 other memory with normal loads and stores.
350 operations and SequentiallyConsistent stores require Release
354 fence after the stores; which is preferred varies by architecture.
396 * DSE: Unordered stores can be DSE'ed like normal stores. Monotonic stores can
404 atomic loads and stores.
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| /llvm-project-15.0.7/llvm/test/Transforms/DeadStoreElimination/ |
| H A D | out-of-bounds-stores.ll | 6 ; Out-of-bounds stores can be considered killing any other stores to the same
30 ; stores to a larger object, followed by an out-of-bounds store.
31 ; FIXME: the 2 inbounds stores could be removed by applying the same
58 ; Make sure that out-of-bound stores are not considered killing other stores to
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| H A D | atomic.ll | 7 ; Basic correctness tests for atomic stores.
173 ; Monotonic atomicrmw should not block eliminating no-aliasing stores.
186 ; Be conservative, do not eliminate stores across atomic operations > monotonic.
200 ; Be conservative, do not eliminate may-alias stores.
214 ; Be conservative, do not eliminate aliasing stores.
242 ; Monotonic cmpxchg should not block DSE for non-aliasing stores.
269 ; Be conservative, do not eliminate may-alias stores.
283 ; Be conservative, do not eliminate alias stores.
299 ; We can optimize unordered atomic loads or stores.
309 ; We can optimize unordered atomic loads or stores.
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| H A D | merge-stores-big-endian.ll | 21 ;; We should be able to merge these four stores with the i32 above
45 ;; We should be able to merge these two stores with the i64 one above
70 ;; We should be able to merge all these stores with the i64 one above
95 ;; We should be able to merge all these stores with the i64 one above
119 ;; We should be able to merge all these stores with the i64 one above
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| H A D | stats.ll | 35 ; CHECK: 1 dse - Number of stores deleted
36 ; CHECK: 3 dse - Number of stores remaining after DSE
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| /llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/AArch64/ |
| H A D | scalarize-store-with-predication.ll | 9 ; configuration where masked loads/stores are legal -- e.g. AArch64 with SVE.
11 ; possibility of superfluous loads/stores which could result in miscompiles.
13 ; stores are predicated properly.
16 ; architecture with masked loads/stores, but we use SVE for testing purposes
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| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/ |
| H A D | merge-store.ll | 38 ; PR21711 - Merge vector stores into wider vector stores.
40 ; On Cyclone, the stores should not get merged into a 16-byte store because
41 ; unaligned 16-byte stores are slow. This test would infinite loop when
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| H A D | sve-pred-non-temporal-ldst-addressing-mode-reg-reg.ll | 3 ; 2-lane non-temporal load/stores
33 ; 4-lane non-temporal load/stores.
64 ; 8-lane non-temporal load/stores.
108 ; 16-lane non-temporal load/stores.
140 ; 2-element non-temporal stores.
144 ; 4-element non-temporal stores.
148 ; 8-element non-temporal stores.
153 ; 16-element non-temporal stores.
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| H A D | ldst-opt-zr-clobber.mir | 8 # Check that write of xzr doesn't inhibit pairing of xzr stores since
11 # between stores.
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| H A D | sdag-store-merging-bug.ll | 6 ; The only way I could trigger stores with mismatching types getting merged was
7 ; via the aarch64 slow-misaligned-128store code splitting stores earlier.
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| /llvm-project-15.0.7/llvm/test/Transforms/GVNHoist/ |
| H A D | pr29031.ll | 3 ; Check that the stores are not hoisted: it is invalid to hoist stores if they
5 ; that do not execute the stores.
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| /llvm-project-15.0.7/llvm/test/Verifier/ |
| H A D | invariant.group.ll | 3 ; CHECK: invariant.group metadata is only for loads and stores
5 ; CHECK-NEXT: invariant.group metadata is only for loads and stores
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| /llvm-project-15.0.7/llvm/test/CodeGen/ARM/ |
| H A D | prera-ldst-insertpt.mir | 42 ; Make sure we move the paired stores next to each other, and
55 ; Make sure we move the paired stores next to each other.
82 ; Make sure we move the paired stores next to each other, and
107 ; Make sure we move the paired stores next to each other.
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| /llvm-project-15.0.7/llvm/test/CodeGen/Mips/tailcall/ |
| H A D | tail-call-arguments-clobber.ll | 10 ; Test that the scheduler does not order loads and stores of arguments that
16 ; loads and stores.
20 ; stores
44 ; stores
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| /llvm-project-15.0.7/mlir/lib/Dialect/Affine/Transforms/ |
| H A D | LoopFusion.cpp | 116 SmallVector<Operation *, 4> stores; member
132 for (auto *storeOpInst : stores) { in getStoreOpCount()
142 for (auto *storeOpInst : stores) { in getStoreOpsForMemref()
164 for (auto *storeOpInst : stores) { in getLoadAndStoreMemrefSet()
532 llvm::append_range(node->stores, stores); in addToNode()
538 node->stores.clear(); in clearNodeLoadAndStores()
712 for (auto *storeOpInst : node->stores) { in gatherEscapingMemrefs()
761 node.stores.push_back(opInst); in init()
777 node.stores.push_back(&op); in init()
824 if (!node.stores.empty()) in init()
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| /llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/ |
| H A D | atomics.ll | 8 ; The SLPVectorizer should not vectorize atomic stores and it should not
9 ; schedule regular stores around atomic stores.
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| /llvm-project-15.0.7/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/ |
| H A D | insertion-point.ll | 7 ; inserted at the position of the first load in the chain, and stores should be
64 ; Here we have four stores, with an aliasing load before the last one. We can
65 ; vectorize the first three stores as <3 x float>, but this vectorized store must
88 ; Here we have four stores, with an aliasing load before the last one. We
89 ; could vectorize two of the stores before the load (although we currently
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