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/llvm-project-15.0.7/llvm/test/MC/VE/
H A DSRL.s6 # CHECK-INST: srl %s11, %s11, %s11
8 srl %s11, %s11, %s11 label
10 # CHECK-INST: srl %s11, %s11, 63
12 srl %s11, %s11, 63 label
14 # CHECK-INST: srl %s11, %s11, 127
16 srl %s11, %s11, 127 label
18 # CHECK-INST: srl %s11, %s11, 64
20 srl %s11, %s11, 64 label
22 # CHECK-INST: srl %s11, (32)1, 64
24 srl %s11, (32)1, 64 label
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/
H A Dbitreverse.ll10 ; MIPS32-NEXT: srl $1, $4, 24
15 ; MIPS32-NEXT: srl $2, $4, 8
21 ; MIPS32-NEXT: srl $1, $1, 4
28 ; MIPS32-NEXT: srl $1, $1, 2
35 ; MIPS32-NEXT: srl $1, $1, 1
85 ; MIPS32-NEXT: srl $2, $5, 8
91 ; MIPS32-NEXT: srl $1, $1, 4
98 ; MIPS32-NEXT: srl $1, $1, 2
105 ; MIPS32-NEXT: srl $1, $1, 1
115 ; MIPS32-NEXT: srl $3, $3, 8
[all …]
H A Dctpop.ll7 ; MIPS32-NEXT: srl $1, $4, 1
12 ; MIPS32-NEXT: srl $1, $2, 2
18 ; MIPS32-NEXT: srl $1, $2, 4
26 ; MIPS32-NEXT: srl $2, $1, 24
39 ; MIPS32-NEXT: srl $1, $4, 1
44 ; MIPS32-NEXT: srl $1, $2, 2
50 ; MIPS32-NEXT: srl $1, $2, 4
58 ; MIPS32-NEXT: srl $2, $1, 24
59 ; MIPS32-NEXT: srl $1, $5, 1
62 ; MIPS32-NEXT: srl $1, $5, 2
[all …]
H A Dbswap.ll10 ; MIPS32-NEXT: srl $1, $4, 24
15 ; MIPS32-NEXT: srl $2, $4, 8
37 ; MIPS32-NEXT: srl $1, $5, 24
42 ; MIPS32-NEXT: srl $2, $5, 8
46 ; MIPS32-NEXT: srl $1, $4, 24
51 ; MIPS32-NEXT: srl $3, $4, 8
H A Dstore_split_because_of_memsize_or_align.ll35 ; MIPS32-NEXT: srl $1, $5, 8
37 ; MIPS32-NEXT: srl $1, $5, 16
45 ; MIPS32R6-NEXT: srl $1, $5, 16
59 ; MIPS32-NEXT: srl $1, $5, 16
67 ; MIPS32R6-NEXT: srl $1, $5, 16
81 ; MIPS32-NEXT: srl $1, $5, 16
89 ; MIPS32R6-NEXT: srl $1, $5, 16
103 ; MIPS32-NEXT: srl $1, $5, 16
211 ; MIPS32-NEXT: srl $1, $7, 8
297 ; MIPS32-NEXT: srl $1, $7, 8
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/
H A Drotations32.s24 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
27 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
31 # CHECK-32: srl $4, $4, 31 # encoding: [0x00,0x04,0x27,0xc2]
36 # CHECK-32: srl $4, $5, 31 # encoding: [0x00,0x05,0x27,0xc2]
41 # CHECK-32: srl $4, $4, 30 # encoding: [0x00,0x04,0x27,0x82]
46 # CHECK-32: srl $4, $5, 30 # encoding: [0x00,0x05,0x27,0x82]
63 # CHECK-32: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
66 # CHECK-32: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
69 # CHECK-32: srl $1, $4, 1 # encoding: [0x00,0x04,0x08,0x42]
74 # CHECK-32: srl $1, $5, 1 # encoding: [0x00,0x05,0x08,0x42]
[all …]
H A Dmicromips-shift-instructions.s14 # CHECK-EL: srl $4, $3, 7 # encoding: [0x83,0x00,0x40,0x38]
26 # CHECK-EL: srl $3, $3, 7 # encoding: [0x63,0x00,0x40,0x38]
34 # CHECK-EB: srl $4, $3, 7 # encoding: [0x00,0x83,0x38,0x40]
46 # CHECK-EB: srl $3, $3, 7 # encoding: [0x00,0x63,0x38,0x40]
51 srl $4, $3, 7
57 srl $2, $3, $5
60 srl $2, $3
63 srl $3, 7
H A Drotations64.s24 # CHECK-64: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
27 # CHECK-64: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
31 # CHECK-64: srl $4, $4, 31 # encoding: [0x00,0x04,0x27,0xc2]
36 # CHECK-64: srl $4, $5, 31 # encoding: [0x00,0x05,0x27,0xc2]
41 # CHECK-64: srl $4, $4, 30 # encoding: [0x00,0x04,0x27,0x82]
46 # CHECK-64: srl $4, $5, 30 # encoding: [0x00,0x05,0x27,0x82]
63 # CHECK-64: srl $4, $4, 0 # encoding: [0x00,0x04,0x20,0x02]
66 # CHECK-64: srl $4, $5, 0 # encoding: [0x00,0x05,0x20,0x02]
69 # CHECK-64: srl $1, $4, 1 # encoding: [0x00,0x04,0x08,0x42]
74 # CHECK-64: srl $1, $5, 1 # encoding: [0x00,0x05,0x08,0x42]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dshift-and-i64-ubfe.ll17 %srl = lshr i64 %ld.64, 31
18 %bit = and i64 %srl, 1
36 %bit = and i64 %srl, 1
52 %bit = and i64 %srl, 1
68 %bit = and i64 %srl, 1
85 %bit = and i64 %srl, 1
102 %bit = and i64 %srl, 1
118 %bit = and i64 %srl, 3
169 %bit = and i64 %srl, 3
387 %srl.srl32 = lshr i64 %srl, 32
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dis_fpclass.ll16 ; CHECK-NEXT: srl %r2, 28
27 ; CHECK-NEXT: srl %r2, 28
40 ; CHECK-NEXT: srl %r2, 28
51 ; CHECK-NEXT: srl %r2, 28
62 ; CHECK-NEXT: srl %r2, 28
73 ; CHECK-NEXT: srl %r2, 28
84 ; CHECK-NEXT: srl %r2, 28
95 ; CHECK-NEXT: srl %r2, 28
106 ; CHECK-NEXT: srl %r2, 28
117 ; CHECK-NEXT: srl %r2, 28
[all …]
H A Dshift-02.ll10 ; CHECK-NEXT: srl %r2, 1
20 ; CHECK-NEXT: srl %r2, 31
40 ; CHECK-NEXT: srl %r2, 0(%r3)
51 ; CHECK-NEXT: srl %r2, 0(%r3)
61 ; CHECK-NEXT: srl %r2, 10(%r3)
72 ; CHECK-NEXT: srl %r2, 10(%r3)
85 ; CHECK-NEXT: srl %r2, 4095(%r3)
97 ; CHECK-NEXT: srl %r2, 0(%r3)
109 ; CHECK-NEXT: srl %r2, 0(%r3)
121 ; CHECK-NEXT: srl %r2, 0(%r1)
H A Dsetcc-02.ll11 ; CHECK-NEXT: srl %r2, 31
24 ; CHECK-NEXT: srl %r2, 31
36 ; CHECK-NEXT: srl %r2, 31
49 ; CHECK-NEXT: srl %r2, 31
85 ; CHECK-NEXT: srl %r2, 31
97 ; CHECK-NEXT: srl %r2, 31
133 ; CHECK-NEXT: srl %r2, 31
157 ; CHECK-NEXT: srl %r2, 31
169 ; CHECK-NEXT: srl %r2, 31
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Drotl-rotr.ll22 ; RV32I-NEXT: srl a0, a0, a2
54 ; RV32I-NEXT: srl a1, a0, a1
96 ; RV32I-NEXT: srl a3, a6, a3
102 ; RV32I-NEXT: srl a3, a4, a6
110 ; RV32I-NEXT: srl a6, a0, a6
130 ; RV64I-NEXT: srl a0, a0, a2
194 ; RV32I-NEXT: srl a0, a1, a5
197 ; RV32I-NEXT: srl a0, a4, a2
219 ; RV32I-NEXT: srl a4, a4, a7
225 ; RV32I-NEXT: srl a1, a1, a2
[all …]
H A Dshifts.ll19 ; RV32I-NEXT: srl a0, a1, a3
23 ; RV32I-NEXT: srl a0, a0, a2
28 ; RV32I-NEXT: srl a1, a1, a2
33 ; RV64I-NEXT: srl a0, a0, a1
51 ; RV64I-NEXT: srl a0, a0, a1
67 ; RV32I-NEXT: srl a0, a0, a2
114 ; RV32I-NEXT: srl a3, a4, a3
165 ; RV32I-NEXT: srl a7, t2, a7
172 ; RV32I-NEXT: srl a7, t5, a2
183 ; RV32I-NEXT: srl a7, a4, t3
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dcountleading.ll23 ; MIPS4-NEXT: srl $1, $4, 1
25 ; MIPS4-NEXT: srl $2, $1, 2
27 ; MIPS4-NEXT: srl $2, $1, 4
35 ; MIPS4-NEXT: srl $5, $1, 8
37 ; MIPS4-NEXT: srl $5, $1, 16
39 ; MIPS4-NEXT: srl $5, $1, 1
43 ; MIPS4-NEXT: srl $1, $1, 2
46 ; MIPS4-NEXT: srl $3, $1, 4
73 ; MIPS4-NEXT: srl $2, $1, 1
75 ; MIPS4-NEXT: srl $2, $1, 2
[all …]
H A Dfunnel-shift-rot.ll24 ; CHECK-NEXT: srl $2, $2, 5
34 ; CHECK-NEXT: srl $1, $5, 29
37 ; CHECK-NEXT: srl $1, $4, 29
163 ; CHECK-NEXT: srl $1, $5, 29
165 ; CHECK-NEXT: srl $2, $4, 29
169 ; CHECK-NEXT: srl $1, $6, 29
172 ; CHECK-NEXT: srl $1, $7, 29
189 ; CHECK-NEXT: srl $2, $2, 3
200 ; CHECK-NEXT: srl $2, $4, 3
324 ; CHECK-NEXT: srl $3, $5, 3
[all …]
H A Dbittest.ll153 ; MIPS-NEXT: srl $1, $1, 16
172 ; MIPS64-NEXT: srl $1, $1, 16
214 ; MIPS-NEXT: srl $2, $1, 31
231 ; MIPS64-NEXT: srl $1, $1, 31
254 ; MM32R3-NEXT: srl $2, $2, 31
259 ; MM32R6-NEXT: srl $2, $2, 31
397 ; MIPS-NEXT: srl $1, $1, 16
461 ; MIPS-NEXT: srl $3, $1, 31
504 ; MM32R3-NEXT: srl $3, $2, 31
511 ; MM32R6-NEXT: srl $3, $2, 31
[all …]
H A Dfunnel-shift.ll28 ; CHECK-NEXT: srl $2, $1, 16
38 ; CHECK-NEXT: srl $2, $5, 1
76 ; CHECK-BE-NEXT: srl $2, $3, 5
82 ; CHECK-BE-NEXT: srl $5, $16, 5
86 ; CHECK-BE-NEXT: srl $6, $18, 1
92 ; CHECK-BE-NEXT: srl $4, $5, 1
127 ; CHECK-LE-NEXT: srl $1, $2, 5
203 ; CHECK-NEXT: srl $1, $5, 23
216 ; CHECK-NEXT: srl $1, $5, 23
448 ; CHECK-NEXT: srl $1, $5, 9
[all …]
H A Dsrem-seteq-illegal-types.ll50 ; MIPSEL-NEXT: srl $2, $1, 4
51 ; MIPSEL-NEXT: srl $1, $1, 7
72 ; MIPS64EL-NEXT: srl $4, $2, 4
73 ; MIPS64EL-NEXT: srl $2, $2, 7
94 ; MIPSEL-NEXT: srl $1, $1, 9
108 ; MIPS64EL-NEXT: srl $2, $2, 9
/llvm-project-15.0.7/llvm/test/CodeGen/LoongArch/ir-instruction/
H A Dlshr.ll22 ; LA32-NEXT: srl.w $a0, $a0, $a1
28 ; LA64-NEXT: srl.d $a0, $a0, $a1
38 ; LA32-NEXT: srl.w $a0, $a0, $a1
44 ; LA64-NEXT: srl.d $a0, $a0, $a1
53 ; LA32-NEXT: srl.w $a0, $a0, $a1
58 ; LA64-NEXT: srl.w $a0, $a0, $a1
70 ; LA32-NEXT: srl.w $a0, $a0, $a2
75 ; LA32-NEXT: srl.w $a5, $a1, $a3
78 ; LA32-NEXT: srl.w $a1, $a1, $a2
85 ; LA64-NEXT: srl.d $a0, $a0, $a1
/llvm-project-15.0.7/llvm/test/CodeGen/VE/Packed/
H A Dvp_fdiv.ll10 ; CHECK-NEXT: srl %s1, %s1, 1
17 ; CHECK-NEXT: srl %s0, %s0, 1
30 ; CHECK-NEXT: srl %s0, %s0, 32
37 ; CHECK-NEXT: srl %s0, %s0, 1
41 ; CHECK-NEXT: srl %s1, %s1, 1
59 ; CHECK-NEXT: srl %s0, %s0, 32
66 ; CHECK-NEXT: srl %s0, %s0, 1
70 ; CHECK-NEXT: srl %s1, %s1, 1
/llvm-project-15.0.7/llvm/test/CodeGen/VE/Scalar/
H A Dright_shift.ll51 ; CHECK-NEXT: srl %s0, %s0, %s1
65 ; CHECK-NEXT: srl %s0, %s0, %s1
79 ; CHECK-NEXT: srl %s0, %s0, %s1
88 ; CHECK-NEXT: srl %s0, %s0, %s1
136 ; CHECK-NEXT: srl %s0, %s0, 5
147 ; CHECK-NEXT: srl %s0, %s0, 5
158 ; CHECK-NEXT: srl %s0, %s0, 5
167 ; CHECK-NEXT: srl %s0, %s0, 5
/llvm-project-15.0.7/llvm/test/CodeGen/LoongArch/
H A Dshift-masked-shamt.ll43 ; LA32-NEXT: srl.w $a0, $a0, $a1
48 ; LA64-NEXT: srl.w $a0, $a0, $a1
59 ; LA32-NEXT: srl.w $a0, $a0, $a1
65 ; LA64-NEXT: srl.w $a0, $a0, $a1
126 ; LA32-NEXT: srl.w $a0, $a0, $a1
132 ; LA64-NEXT: srl.w $a0, $a0, $a1
165 ; LA32-NEXT: srl.w $a3, $a3, $a5
198 ; LA32-NEXT: srl.w $a0, $a0, $a2
203 ; LA32-NEXT: srl.w $a5, $a1, $a3
206 ; LA32-NEXT: srl.w $a1, $a1, $a2
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dicmp-shift-opt.ll38 %srl = lshr i128 %a, 17
39 %cmp = icmp eq i128 %srl, 0
50 %srl = lshr i128 %a, 17
51 %cmp = icmp ne i128 %srl, 0
109 %srl.b = lshr i64 %b, 47
110 %or.0 = or i64 %shl.a, %srl.b
128 %srl.b = lshr i64 %b, 47
129 %or.0 = or i64 %shl.a, %srl.b
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dcombine-srl.ll7 ; fold (srl 0, x) -> 0
22 ; fold (srl x, c >= size(x)) -> undef
47 ; fold (srl x, 0) -> x
56 ; if (srl x, c) is known to be zero, return 0
89 ; fold (srl (srl x, c1), c2) -> (srl x, (add c1, c2))
129 ; fold (srl (srl x, c1), c2) -> 0
160 ; fold (srl (trunc (srl x, c1)), c2) -> (trunc (srl x, (add c1, c2)))
237 ; fold (srl (trunc (srl x, c1)), c2) -> 0
274 ; fold (srl (shl x, c), c) -> (and x, cst2)
306 ; fold (srl (sra X, Y), 31) -> (srl X, 31)
[all …]

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