1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=mipsel -mcpu=mips32   < %s | FileCheck -check-prefixes=MIPS-GT-R1,MIPS32-R1-R2 %s
3; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck -check-prefixes=MIPS-GT-R1,MIPS32-R1-R2 %s
4; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | FileCheck -check-prefixes=MIPS-GT-R1,MIPS32-R6 %s
5; RUN: llc -march=mips64el -mcpu=mips64   < %s | FileCheck -check-prefixes=MIPS-GT-R1,MIPS64-GT-R1 %s
6; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefixes=MIPS-GT-R1,MIPS64-GT-R1 %s
7; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck -check-prefixes=MIPS-GT-R1,MIPS64-GT-R1 %s
8; RUN: llc -march=mips64el -mcpu=mips4    < %s | FileCheck -check-prefixes=MIPS4 %s
9
10; Prefixes:
11;   ALL      - All
12;   MIPS-GT-R1 - MIPS32r1/MIPS64r1 and above
13;   MIPS64-GT-R1 - MIPS64r1 and above
14
15define i32 @ctlz_i32(i32 signext %X) nounwind readnone {
16; MIPS-GT-R1-LABEL: ctlz_i32:
17; MIPS-GT-R1:       # %bb.0: # %entry
18; MIPS-GT-R1-NEXT:    jr $ra
19; MIPS-GT-R1-NEXT:    clz $2, $4
20;
21; MIPS4-LABEL: ctlz_i32:
22; MIPS4:       # %bb.0: # %entry
23; MIPS4-NEXT:    srl $1, $4, 1
24; MIPS4-NEXT:    or $1, $4, $1
25; MIPS4-NEXT:    srl $2, $1, 2
26; MIPS4-NEXT:    or $1, $1, $2
27; MIPS4-NEXT:    srl $2, $1, 4
28; MIPS4-NEXT:    lui $3, 21845
29; MIPS4-NEXT:    lui $4, 13107
30; MIPS4-NEXT:    lui $5, 3855
31; MIPS4-NEXT:    or $1, $1, $2
32; MIPS4-NEXT:    ori $2, $5, 3855
33; MIPS4-NEXT:    ori $4, $4, 13107
34; MIPS4-NEXT:    ori $3, $3, 21845
35; MIPS4-NEXT:    srl $5, $1, 8
36; MIPS4-NEXT:    or $1, $1, $5
37; MIPS4-NEXT:    srl $5, $1, 16
38; MIPS4-NEXT:    nor $1, $1, $5
39; MIPS4-NEXT:    srl $5, $1, 1
40; MIPS4-NEXT:    and $3, $5, $3
41; MIPS4-NEXT:    subu $1, $1, $3
42; MIPS4-NEXT:    and $3, $1, $4
43; MIPS4-NEXT:    srl $1, $1, 2
44; MIPS4-NEXT:    and $1, $1, $4
45; MIPS4-NEXT:    addu $1, $3, $1
46; MIPS4-NEXT:    srl $3, $1, 4
47; MIPS4-NEXT:    addu $1, $1, $3
48; MIPS4-NEXT:    and $1, $1, $2
49; MIPS4-NEXT:    sll $2, $1, 8
50; MIPS4-NEXT:    addu $2, $2, $1
51; MIPS4-NEXT:    sll $3, $1, 16
52; MIPS4-NEXT:    addu $2, $3, $2
53; MIPS4-NEXT:    sll $1, $1, 24
54; MIPS4-NEXT:    addu $1, $1, $2
55; MIPS4-NEXT:    jr $ra
56; MIPS4-NEXT:    srl $2, $1, 24
57entry:
58  %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %X, i1 true)
59  ret i32 %tmp1
60}
61
62declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone
63
64define i32 @ctlo_i32(i32 signext %X) nounwind readnone {
65; MIPS-GT-R1-LABEL: ctlo_i32:
66; MIPS-GT-R1:       # %bb.0: # %entry
67; MIPS-GT-R1-NEXT:    jr $ra
68; MIPS-GT-R1-NEXT:    clo $2, $4
69;
70; MIPS4-LABEL: ctlo_i32:
71; MIPS4:       # %bb.0: # %entry
72; MIPS4-NEXT:    not $1, $4
73; MIPS4-NEXT:    srl $2, $1, 1
74; MIPS4-NEXT:    or $1, $1, $2
75; MIPS4-NEXT:    srl $2, $1, 2
76; MIPS4-NEXT:    or $1, $1, $2
77; MIPS4-NEXT:    lui $2, 21845
78; MIPS4-NEXT:    lui $3, 13107
79; MIPS4-NEXT:    lui $4, 3855
80; MIPS4-NEXT:    srl $5, $1, 4
81; MIPS4-NEXT:    ori $4, $4, 3855
82; MIPS4-NEXT:    ori $3, $3, 13107
83; MIPS4-NEXT:    ori $2, $2, 21845
84; MIPS4-NEXT:    or $1, $1, $5
85; MIPS4-NEXT:    srl $5, $1, 8
86; MIPS4-NEXT:    or $1, $1, $5
87; MIPS4-NEXT:    srl $5, $1, 16
88; MIPS4-NEXT:    nor $1, $1, $5
89; MIPS4-NEXT:    srl $5, $1, 1
90; MIPS4-NEXT:    and $2, $5, $2
91; MIPS4-NEXT:    subu $1, $1, $2
92; MIPS4-NEXT:    and $2, $1, $3
93; MIPS4-NEXT:    srl $1, $1, 2
94; MIPS4-NEXT:    and $1, $1, $3
95; MIPS4-NEXT:    addu $1, $2, $1
96; MIPS4-NEXT:    srl $2, $1, 4
97; MIPS4-NEXT:    addu $1, $1, $2
98; MIPS4-NEXT:    and $1, $1, $4
99; MIPS4-NEXT:    sll $2, $1, 8
100; MIPS4-NEXT:    addu $2, $2, $1
101; MIPS4-NEXT:    sll $3, $1, 16
102; MIPS4-NEXT:    addu $2, $3, $2
103; MIPS4-NEXT:    sll $1, $1, 24
104; MIPS4-NEXT:    addu $1, $1, $2
105; MIPS4-NEXT:    jr $ra
106; MIPS4-NEXT:    srl $2, $1, 24
107entry:
108  %neg = xor i32 %X, -1
109  %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %neg, i1 true)
110  ret i32 %tmp1
111}
112
113define i64 @ctlz_i64(i64 %X) nounwind readnone {
114; MIPS32-R1-R2-LABEL: ctlz_i64:
115; MIPS32-R1-R2:       # %bb.0: # %entry
116; MIPS32-R1-R2-NEXT:    clz $1, $5
117; MIPS32-R1-R2-NEXT:    clz $2, $4
118; MIPS32-R1-R2-NEXT:    addiu $2, $2, 32
119; MIPS32-R1-R2-NEXT:    movn $2, $1, $5
120; MIPS32-R1-R2-NEXT:    jr $ra
121; MIPS32-R1-R2-NEXT:    addiu $3, $zero, 0
122;
123; MIPS32-R6-LABEL: ctlz_i64:
124; MIPS32-R6:       # %bb.0: # %entry
125; MIPS32-R6-NEXT:    clz $1, $5
126; MIPS32-R6-NEXT:    selnez $1, $1, $5
127; MIPS32-R6-NEXT:    clz $2, $4
128; MIPS32-R6-NEXT:    addiu $2, $2, 32
129; MIPS32-R6-NEXT:    seleqz $2, $2, $5
130; MIPS32-R6-NEXT:    or $2, $1, $2
131; MIPS32-R6-NEXT:    jr $ra
132; MIPS32-R6-NEXT:    addiu $3, $zero, 0
133;
134; MIPS64-GT-R1-LABEL: ctlz_i64:
135; MIPS64-GT-R1:       # %bb.0: # %entry
136; MIPS64-GT-R1-NEXT:    jr $ra
137; MIPS64-GT-R1-NEXT:    dclz $2, $4
138;
139; MIPS4-LABEL: ctlz_i64:
140; MIPS4:       # %bb.0: # %entry
141; MIPS4-NEXT:    dsrl $1, $4, 1
142; MIPS4-NEXT:    or $1, $4, $1
143; MIPS4-NEXT:    dsrl $2, $1, 2
144; MIPS4-NEXT:    or $1, $1, $2
145; MIPS4-NEXT:    dsrl $2, $1, 4
146; MIPS4-NEXT:    or $1, $1, $2
147; MIPS4-NEXT:    lui $2, 13107
148; MIPS4-NEXT:    dsrl $3, $1, 8
149; MIPS4-NEXT:    daddiu $2, $2, 13107
150; MIPS4-NEXT:    or $1, $1, $3
151; MIPS4-NEXT:    dsll $2, $2, 16
152; MIPS4-NEXT:    lui $3, 3855
153; MIPS4-NEXT:    daddiu $3, $3, 3855
154; MIPS4-NEXT:    dsll $3, $3, 16
155; MIPS4-NEXT:    daddiu $3, $3, 3855
156; MIPS4-NEXT:    daddiu $2, $2, 13107
157; MIPS4-NEXT:    lui $4, 21845
158; MIPS4-NEXT:    daddiu $4, $4, 21845
159; MIPS4-NEXT:    dsll $4, $4, 16
160; MIPS4-NEXT:    dsrl $5, $1, 16
161; MIPS4-NEXT:    or $1, $1, $5
162; MIPS4-NEXT:    dsll $2, $2, 16
163; MIPS4-NEXT:    dsll $3, $3, 16
164; MIPS4-NEXT:    lui $5, 257
165; MIPS4-NEXT:    daddiu $5, $5, 257
166; MIPS4-NEXT:    dsll $5, $5, 16
167; MIPS4-NEXT:    daddiu $5, $5, 257
168; MIPS4-NEXT:    dsll $5, $5, 16
169; MIPS4-NEXT:    dsrl $6, $1, 32
170; MIPS4-NEXT:    daddiu $5, $5, 257
171; MIPS4-NEXT:    daddiu $3, $3, 3855
172; MIPS4-NEXT:    daddiu $2, $2, 13107
173; MIPS4-NEXT:    daddiu $4, $4, 21845
174; MIPS4-NEXT:    dsll $4, $4, 16
175; MIPS4-NEXT:    daddiu $4, $4, 21845
176; MIPS4-NEXT:    nor $1, $1, $6
177; MIPS4-NEXT:    dsrl $6, $1, 1
178; MIPS4-NEXT:    and $4, $6, $4
179; MIPS4-NEXT:    dsubu $1, $1, $4
180; MIPS4-NEXT:    and $4, $1, $2
181; MIPS4-NEXT:    dsrl $1, $1, 2
182; MIPS4-NEXT:    and $1, $1, $2
183; MIPS4-NEXT:    daddu $1, $4, $1
184; MIPS4-NEXT:    dsrl $2, $1, 4
185; MIPS4-NEXT:    daddu $1, $1, $2
186; MIPS4-NEXT:    and $1, $1, $3
187; MIPS4-NEXT:    dmult $1, $5
188; MIPS4-NEXT:    mflo $1
189; MIPS4-NEXT:    jr $ra
190; MIPS4-NEXT:    dsrl $2, $1, 56
191entry:
192  %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true)
193  ret i64 %tmp1
194}
195
196declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
197
198define i64 @ctlo_i64(i64 %X) nounwind readnone {
199; MIPS32-R1-R2-LABEL: ctlo_i64:
200; MIPS32-R1-R2:       # %bb.0: # %entry
201; MIPS32-R1-R2-NEXT:    not $1, $5
202; MIPS32-R1-R2-NEXT:    clo $3, $5
203; MIPS32-R1-R2-NEXT:    clo $2, $4
204; MIPS32-R1-R2-NEXT:    addiu $2, $2, 32
205; MIPS32-R1-R2-NEXT:    movn $2, $3, $1
206; MIPS32-R1-R2-NEXT:    jr $ra
207; MIPS32-R1-R2-NEXT:    addiu $3, $zero, 0
208;
209; MIPS32-R6-LABEL: ctlo_i64:
210; MIPS32-R6:       # %bb.0: # %entry
211; MIPS32-R6-NEXT:    not $1, $5
212; MIPS32-R6-NEXT:    clo $2, $5
213; MIPS32-R6-NEXT:    selnez $2, $2, $1
214; MIPS32-R6-NEXT:    clo $3, $4
215; MIPS32-R6-NEXT:    addiu $3, $3, 32
216; MIPS32-R6-NEXT:    seleqz $1, $3, $1
217; MIPS32-R6-NEXT:    or $2, $2, $1
218; MIPS32-R6-NEXT:    jr $ra
219; MIPS32-R6-NEXT:    addiu $3, $zero, 0
220;
221; MIPS64-GT-R1-LABEL: ctlo_i64:
222; MIPS64-GT-R1:       # %bb.0: # %entry
223; MIPS64-GT-R1-NEXT:    jr $ra
224; MIPS64-GT-R1-NEXT:    dclo $2, $4
225;
226; MIPS4-LABEL: ctlo_i64:
227; MIPS4:       # %bb.0: # %entry
228; MIPS4-NEXT:    daddiu $1, $zero, -1
229; MIPS4-NEXT:    xor $1, $4, $1
230; MIPS4-NEXT:    dsrl $2, $1, 1
231; MIPS4-NEXT:    or $1, $1, $2
232; MIPS4-NEXT:    dsrl $2, $1, 2
233; MIPS4-NEXT:    or $1, $1, $2
234; MIPS4-NEXT:    dsrl $2, $1, 4
235; MIPS4-NEXT:    lui $3, 13107
236; MIPS4-NEXT:    or $1, $1, $2
237; MIPS4-NEXT:    daddiu $2, $3, 13107
238; MIPS4-NEXT:    dsrl $3, $1, 8
239; MIPS4-NEXT:    dsll $2, $2, 16
240; MIPS4-NEXT:    lui $4, 3855
241; MIPS4-NEXT:    daddiu $4, $4, 3855
242; MIPS4-NEXT:    dsll $4, $4, 16
243; MIPS4-NEXT:    or $1, $1, $3
244; MIPS4-NEXT:    daddiu $3, $4, 3855
245; MIPS4-NEXT:    daddiu $2, $2, 13107
246; MIPS4-NEXT:    lui $4, 21845
247; MIPS4-NEXT:    daddiu $4, $4, 21845
248; MIPS4-NEXT:    dsll $4, $4, 16
249; MIPS4-NEXT:    daddiu $4, $4, 21845
250; MIPS4-NEXT:    dsrl $5, $1, 16
251; MIPS4-NEXT:    dsll $2, $2, 16
252; MIPS4-NEXT:    dsll $3, $3, 16
253; MIPS4-NEXT:    lui $6, 257
254; MIPS4-NEXT:    daddiu $6, $6, 257
255; MIPS4-NEXT:    dsll $6, $6, 16
256; MIPS4-NEXT:    daddiu $6, $6, 257
257; MIPS4-NEXT:    dsll $6, $6, 16
258; MIPS4-NEXT:    or $1, $1, $5
259; MIPS4-NEXT:    daddiu $5, $6, 257
260; MIPS4-NEXT:    daddiu $3, $3, 3855
261; MIPS4-NEXT:    daddiu $2, $2, 13107
262; MIPS4-NEXT:    dsll $4, $4, 16
263; MIPS4-NEXT:    daddiu $4, $4, 21845
264; MIPS4-NEXT:    dsrl $6, $1, 32
265; MIPS4-NEXT:    nor $1, $1, $6
266; MIPS4-NEXT:    dsrl $6, $1, 1
267; MIPS4-NEXT:    and $4, $6, $4
268; MIPS4-NEXT:    dsubu $1, $1, $4
269; MIPS4-NEXT:    and $4, $1, $2
270; MIPS4-NEXT:    dsrl $1, $1, 2
271; MIPS4-NEXT:    and $1, $1, $2
272; MIPS4-NEXT:    daddu $1, $4, $1
273; MIPS4-NEXT:    dsrl $2, $1, 4
274; MIPS4-NEXT:    daddu $1, $1, $2
275; MIPS4-NEXT:    and $1, $1, $3
276; MIPS4-NEXT:    dmult $1, $5
277; MIPS4-NEXT:    mflo $1
278; MIPS4-NEXT:    jr $ra
279; MIPS4-NEXT:    dsrl $2, $1, 56
280entry:
281  %neg = xor i64 %X, -1
282  %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true)
283  ret i64 %tmp1
284}
285