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Searched refs:splats (Results 1 – 24 of 24) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dsplat-for-size.ll91 ; AVX can't do integer splats, so fake it: use vmovddup to splat 64-bit value.
169 ; AVX can't do integer splats, so fake it: use vbroadcastss to splat 32-bit value.
202 ; AVX can't do integer splats, so fake it: use vbroadcastss to splat 32-bit value.
241 ; AVX can't do integer splats, and there's no broadcast fakery for 16-bit. Could use pshuflw, etc?
272 ; AVX can't do integer splats, and there's no broadcast fakery for 16-bit. Could use pshuflw, etc?
311 ; AVX can't do integer splats, and there's no broadcast fakery for 8-bit. Could use pshufb, etc?
342 ; AVX can't do integer splats, and there's no broadcast fakery for 8-bit. Could use pshufb, etc?
/llvm-project-15.0.7/clang/test/Sema/
H A Dext_vector_casts.c97 static void splats(int i, long l, __uint128_t t, float f, double d) { in splats() function
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dpr25157-peephole.ll5 ; Verify peephole simplification of splats and swaps. Bugpoint-reduced
/llvm-project-15.0.7/llvm/test/CodeGen/WebAssembly/
H A Dsimd-shift-complex-splats.ll4 ; values that are more complex than plain splats.
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/AArch64/
H A Dshuffle-load.ll5 ; isLegalBroadcastLoad method. The tests use vector loads and splats,
6 ; as opposed to scalar loads, inserts and splats as that is how
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-vector-splat.ll96 ;; Promote splats of smaller illegal integer vector types
193 ;; Widen/split splats of wide vector types.
591 ; This guards optimizations that rely on splats of 1 being generated as a ptrue
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dvec-perm-02.ll1 ; Test replications of a scalar register value, represented as splats.
H A Dvec-perm-03.ll1 ; Test replications of a scalar memory value, represented as splats.
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/AArch64/
H A Dsplat-loads.ll6 ; This checks that we we prefer splats rather than load vectors + shuffles.
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dbroadcast.ll129 ; TODO: Multiple uses triggers the transform at %t4, but we should sink/scalarize/CSE the splats?
H A Dbroadcast-inseltpoison.ll129 ; TODO: Multiple uses triggers the transform at %t4, but we should sink/scalarize/CSE the splats?
H A Dshift.ll882 ; (X <<nuw C1) >>u C2 --> X >>u (C2-C1) with splats
H A Dand.ll822 ; vector splats work too
H A Dvec_shuffle-inseltpoison.ll140 ; Redundant vector splats should be removed. Radar 8597790.
H A Dvec_shuffle.ll140 ; Redundant vector splats should be removed. Radar 8597790.
/llvm-project-15.0.7/clang/include/clang/AST/
H A DOperationKinds.def188 /// vector of that element type. Fills all elements ("splats") with
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/
H A Dcmp-vec-fast-path.ll2 ; Check that cmp's of scalable vector splats are simplified
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dlookahead.ll712 ; This checks that we we prefer splats rather than reverse load vectors + shuffles.
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dvmov.ll609 ; Use vmov.f32 to materialize f32 immediate splats
/llvm-project-15.0.7/clang/include/clang/Basic/
H A Darm_neon.td229 // sudot splats the second vector and then calls vusdot
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/
H A Dfixed-vectors-setcc-int-vp.ll8 ; for ISD::SETCC, e.g., splats aren't moved to the RHS.
H A Dsetcc-integer.ll3209 ; Check a setcc with two constant splats, which would previously get stuck in
H A Dsetcc-int-vp.ll8 ; for ISD::SETCC, e.g., splats aren't moved to the RHS.
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrVSX.td4099 // Endianness-neutral patterns for const splats with ISA 3.0 instructions.