1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -passes=instcombine -S | FileCheck %s 3 4define <4 x i32> @lshr_non_splat_vector(<4 x i32> %A) { 5; CHECK-LABEL: @lshr_non_splat_vector( 6; CHECK-NEXT: [[B:%.*]] = lshr <4 x i32> [[A:%.*]], <i32 32, i32 1, i32 2, i32 3> 7; CHECK-NEXT: ret <4 x i32> [[B]] 8; 9 %B = lshr <4 x i32> %A, <i32 32, i32 1, i32 2, i32 3> 10 ret <4 x i32> %B 11} 12 13define <4 x i32> @shl_non_splat_vector(<4 x i32> %A) { 14; CHECK-LABEL: @shl_non_splat_vector( 15; CHECK-NEXT: [[B:%.*]] = shl <4 x i32> [[A:%.*]], <i32 32, i32 1, i32 2, i32 3> 16; CHECK-NEXT: ret <4 x i32> [[B]] 17; 18 %B = shl <4 x i32> %A, <i32 32, i32 1, i32 2, i32 3> 19 ret <4 x i32> %B 20} 21 22define i32 @test6(i32 %A) { 23; CHECK-LABEL: @test6( 24; CHECK-NEXT: [[C:%.*]] = mul i32 [[A:%.*]], 6 25; CHECK-NEXT: ret i32 [[C]] 26; 27 %B = shl i32 %A, 1 ;; convert to an mul instruction 28 %C = mul i32 %B, 3 29 ret i32 %C 30} 31 32define i32 @test6a(i32 %A) { 33; CHECK-LABEL: @test6a( 34; CHECK-NEXT: [[C:%.*]] = mul i32 [[A:%.*]], 6 35; CHECK-NEXT: ret i32 [[C]] 36; 37 %B = mul i32 %A, 3 38 %C = shl i32 %B, 1 ;; convert to an mul instruction 39 ret i32 %C 40} 41 42;; (A << 5) << 3 === A << 8 == 0 43define i8 @test8(i8 %A) { 44; CHECK-LABEL: @test8( 45; CHECK-NEXT: ret i8 0 46; 47 %B = shl i8 %A, 5 48 %C = shl i8 %B, 3 49 ret i8 %C 50} 51 52;; (A << 7) >> 7 === A & 1 53define i8 @test9(i8 %A) { 54; CHECK-LABEL: @test9( 55; CHECK-NEXT: [[B:%.*]] = and i8 [[A:%.*]], 1 56; CHECK-NEXT: ret i8 [[B]] 57; 58 %B = shl i8 %A, 7 59 %C = lshr i8 %B, 7 60 ret i8 %C 61} 62 63;; (A >> 7) << 7 === A & 128 64 65define i8 @test10(i8 %A) { 66; CHECK-LABEL: @test10( 67; CHECK-NEXT: [[B:%.*]] = and i8 [[A:%.*]], -128 68; CHECK-NEXT: ret i8 [[B]] 69; 70 %B = lshr i8 %A, 7 71 %C = shl i8 %B, 7 72 ret i8 %C 73} 74 75;; Allow the simplification when the lshr shift is exact. 76define i8 @test10a(i8 %A) { 77; CHECK-LABEL: @test10a( 78; CHECK-NEXT: ret i8 [[A:%.*]] 79; 80 %B = lshr exact i8 %A, 7 81 %C = shl i8 %B, 7 82 ret i8 %C 83} 84 85;; (A >> 3) << 4 === (A & 0x1F) << 1 86define i8 @test11(i8 %x) { 87; CHECK-LABEL: @test11( 88; CHECK-NEXT: [[TMP1:%.*]] = mul i8 [[X:%.*]], 6 89; CHECK-NEXT: [[C:%.*]] = and i8 [[TMP1]], -16 90; CHECK-NEXT: ret i8 [[C]] 91; 92 %a = mul i8 %x, 3 93 %B = lshr i8 %a, 3 94 %C = shl i8 %B, 4 95 ret i8 %C 96} 97 98;; Allow the simplification in InstCombine when the lshr shift is exact. 99define i8 @test11a(i8 %A) { 100; CHECK-LABEL: @test11a( 101; CHECK-NEXT: [[C:%.*]] = mul i8 [[A:%.*]], 6 102; CHECK-NEXT: ret i8 [[C]] 103; 104 %a = mul i8 %A, 3 105 %B = lshr exact i8 %a, 3 106 %C = shl i8 %B, 4 107 ret i8 %C 108} 109 110;; (A >> 8) << 8 === A & -256 111define i32 @test12(i32 %A) { 112; CHECK-LABEL: @test12( 113; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], -256 114; CHECK-NEXT: ret i32 [[TMP1]] 115; 116 %B = ashr i32 %A, 8 117 %C = shl i32 %B, 8 118 ret i32 %C 119} 120 121;; ((A >>s 6) << 6 === (A & FFFFFFC0) 122define i8 @shishi(i8 %x) { 123; CHECK-LABEL: @shishi( 124; CHECK-NEXT: [[A:%.*]] = ashr i8 [[X:%.*]], 6 125; CHECK-NEXT: [[B:%.*]] = and i8 [[X]], -64 126; CHECK-NEXT: [[EXTRA_USE_OF_A:%.*]] = mul nsw i8 [[A]], 5 127; CHECK-NEXT: [[R:%.*]] = sdiv i8 [[EXTRA_USE_OF_A]], [[B]] 128; CHECK-NEXT: ret i8 [[R]] 129; 130 %a = ashr i8 %x, 6 131 %b = shl i8 %a, 6 132 %extra_use_of_a = mul i8 %a, 5 133 %r = sdiv i8 %extra_use_of_a, %b 134 ret i8 %r 135} 136 137;; (A >> 3) << 4 === (A & -8) * 2 138define i8 @test13(i8 %x) { 139; CHECK-LABEL: @test13( 140; CHECK-NEXT: [[TMP1:%.*]] = mul i8 [[X:%.*]], 6 141; CHECK-NEXT: [[C:%.*]] = and i8 [[TMP1]], -16 142; CHECK-NEXT: ret i8 [[C]] 143; 144 %a = mul i8 %x, 3 145 %B = ashr i8 %a, 3 146 %C = shl i8 %B, 4 147 ret i8 %C 148} 149 150define i8 @test13a(i8 %A) { 151; CHECK-LABEL: @test13a( 152; CHECK-NEXT: [[C:%.*]] = mul i8 [[A:%.*]], 6 153; CHECK-NEXT: ret i8 [[C]] 154; 155 %a = mul i8 %A, 3 156 %B = ashr exact i8 %a, 3 157 %C = shl i8 %B, 4 158 ret i8 %C 159} 160 161;; D = ((B | 1234) << 4) === ((B << 4)|(1234 << 4) 162define i32 @test14(i32 %A) { 163; CHECK-LABEL: @test14( 164; CHECK-NEXT: [[B:%.*]] = and i32 [[A:%.*]], -19760 165; CHECK-NEXT: [[C:%.*]] = or i32 [[B]], 19744 166; CHECK-NEXT: ret i32 [[C]] 167; 168 %B = lshr i32 %A, 4 169 %C = or i32 %B, 1234 170 %D = shl i32 %C, 4 171 ret i32 %D 172} 173 174;; D = ((B | 1234) << 4) === ((B << 4)|(1234 << 4) 175define i32 @test14a(i32 %A) { 176; CHECK-LABEL: @test14a( 177; CHECK-NEXT: [[C:%.*]] = and i32 [[A:%.*]], 77 178; CHECK-NEXT: ret i32 [[C]] 179; 180 %B = shl i32 %A, 4 181 %C = and i32 %B, 1234 182 %D = lshr i32 %C, 4 183 ret i32 %D 184} 185 186define i32 @test15(i1 %C) { 187; CHECK-LABEL: @test15( 188; CHECK-NEXT: [[A:%.*]] = select i1 [[C:%.*]], i32 12, i32 4 189; CHECK-NEXT: ret i32 [[A]] 190; 191 %A = select i1 %C, i32 3, i32 1 192 %V = shl i32 %A, 2 193 ret i32 %V 194} 195 196define i32 @test15a(i1 %C) { 197; CHECK-LABEL: @test15a( 198; CHECK-NEXT: [[V:%.*]] = select i1 [[C:%.*]], i32 512, i32 128 199; CHECK-NEXT: ret i32 [[V]] 200; 201 %A = select i1 %C, i8 3, i8 1 202 %shift.upgrd.4 = zext i8 %A to i32 203 %V = shl i32 64, %shift.upgrd.4 204 ret i32 %V 205} 206 207define i1 @test16(i32 %X) { 208; CHECK-LABEL: @test16( 209; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 16 210; CHECK-NEXT: [[I_7:%.*]] = icmp ne i32 [[TMP1]], 0 211; CHECK-NEXT: ret i1 [[I_7]] 212; 213 %i.3 = ashr i32 %X, 4 214 %i.6 = and i32 %i.3, 1 215 %i.7 = icmp ne i32 %i.6, 0 216 ret i1 %i.7 217} 218 219define i1 @test17(i32 %A) { 220; CHECK-LABEL: @test17( 221; CHECK-NEXT: [[B_MASK:%.*]] = and i32 [[A:%.*]], -8 222; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[B_MASK]], 9872 223; CHECK-NEXT: ret i1 [[C]] 224; 225 %B = lshr i32 %A, 3 226 %C = icmp eq i32 %B, 1234 227 ret i1 %C 228} 229 230define <2 x i1> @test17vec(<2 x i32> %A) { 231; CHECK-LABEL: @test17vec( 232; CHECK-NEXT: [[B_MASK:%.*]] = and <2 x i32> [[A:%.*]], <i32 -8, i32 -8> 233; CHECK-NEXT: [[C:%.*]] = icmp eq <2 x i32> [[B_MASK]], <i32 9872, i32 9872> 234; CHECK-NEXT: ret <2 x i1> [[C]] 235; 236 %B = lshr <2 x i32> %A, <i32 3, i32 3> 237 %C = icmp eq <2 x i32> %B, <i32 1234, i32 1234> 238 ret <2 x i1> %C 239} 240 241define i1 @test18(i8 %A) { 242; CHECK-LABEL: @test18( 243; CHECK-NEXT: ret i1 false 244; 245 %B = lshr i8 %A, 7 246 ;; false 247 %C = icmp eq i8 %B, 123 248 ret i1 %C 249} 250 251define i1 @test19(i32 %A) { 252; CHECK-LABEL: @test19( 253; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[A:%.*]], 4 254; CHECK-NEXT: ret i1 [[C]] 255; 256 %B = ashr i32 %A, 2 257 ;; (X & -4) == 0 258 %C = icmp eq i32 %B, 0 259 ret i1 %C 260} 261 262define <2 x i1> @test19vec(<2 x i32> %A) { 263; CHECK-LABEL: @test19vec( 264; CHECK-NEXT: [[C:%.*]] = icmp ult <2 x i32> [[A:%.*]], <i32 4, i32 4> 265; CHECK-NEXT: ret <2 x i1> [[C]] 266; 267 %B = ashr <2 x i32> %A, <i32 2, i32 2> 268 %C = icmp eq <2 x i32> %B, zeroinitializer 269 ret <2 x i1> %C 270} 271 272;; X >u ~4 273define i1 @test19a(i32 %A) { 274; CHECK-LABEL: @test19a( 275; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[A:%.*]], -5 276; CHECK-NEXT: ret i1 [[C]] 277; 278 %B = ashr i32 %A, 2 279 %C = icmp eq i32 %B, -1 280 ret i1 %C 281} 282 283define <2 x i1> @test19a_vec(<2 x i32> %A) { 284; CHECK-LABEL: @test19a_vec( 285; CHECK-NEXT: [[C:%.*]] = icmp ugt <2 x i32> [[A:%.*]], <i32 -5, i32 -5> 286; CHECK-NEXT: ret <2 x i1> [[C]] 287; 288 %B = ashr <2 x i32> %A, <i32 2, i32 2> 289 %C = icmp eq <2 x i32> %B, <i32 -1, i32 -1> 290 ret <2 x i1> %C 291} 292 293define i1 @test20(i8 %A) { 294; CHECK-LABEL: @test20( 295; CHECK-NEXT: ret i1 false 296; 297 %B = ashr i8 %A, 7 298 ;; false 299 %C = icmp eq i8 %B, 123 300 ret i1 %C 301} 302 303define i1 @test21(i8 %A) { 304; CHECK-LABEL: @test21( 305; CHECK-NEXT: [[B_MASK:%.*]] = and i8 [[A:%.*]], 15 306; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[B_MASK]], 8 307; CHECK-NEXT: ret i1 [[C]] 308; 309 %B = shl i8 %A, 4 310 %C = icmp eq i8 %B, -128 311 ret i1 %C 312} 313 314define i1 @test22(i8 %A) { 315; CHECK-LABEL: @test22( 316; CHECK-NEXT: [[B_MASK:%.*]] = and i8 [[A:%.*]], 15 317; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[B_MASK]], 0 318; CHECK-NEXT: ret i1 [[C]] 319; 320 %B = shl i8 %A, 4 321 %C = icmp eq i8 %B, 0 322 ret i1 %C 323} 324 325define i8 @test23(i32 %A) { 326; CHECK-LABEL: @test23( 327; CHECK-NEXT: [[D:%.*]] = trunc i32 [[A:%.*]] to i8 328; CHECK-NEXT: ret i8 [[D]] 329; 330 ;; casts not needed 331 %B = shl i32 %A, 24 332 %C = ashr i32 %B, 24 333 %D = trunc i32 %C to i8 334 ret i8 %D 335} 336 337define i8 @test24(i8 %X) { 338; CHECK-LABEL: @test24( 339; CHECK-NEXT: [[Z:%.*]] = and i8 [[X:%.*]], 3 340; CHECK-NEXT: ret i8 [[Z]] 341; 342 %Y = and i8 %X, -5 343 %Z = shl i8 %Y, 5 344 %Q = ashr i8 %Z, 5 345 ret i8 %Q 346} 347 348;; handle casts between shifts. 349define i32 @test26(i32 %A) { 350; CHECK-LABEL: @test26( 351; CHECK-NEXT: [[B:%.*]] = and i32 [[A:%.*]], -2 352; CHECK-NEXT: ret i32 [[B]] 353; 354 %B = lshr i32 %A, 1 355 %C = bitcast i32 %B to i32 356 %D = shl i32 %C, 1 357 ret i32 %D 358} 359 360 361define i1 @test27(i32 %x) nounwind { 362; CHECK-LABEL: @test27( 363; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 8 364; CHECK-NEXT: [[Z:%.*]] = icmp ne i32 [[TMP1]], 0 365; CHECK-NEXT: ret i1 [[Z]] 366; 367 %y = lshr i32 %x, 3 368 %z = trunc i32 %y to i1 369 ret i1 %z 370} 371 372define i1 @test28(i8 %x) { 373; CHECK-LABEL: @test28( 374; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[X:%.*]], 0 375; CHECK-NEXT: ret i1 [[CMP]] 376; 377 %shr = lshr i8 %x, 7 378 %cmp = icmp ne i8 %shr, 0 379 ret i1 %cmp 380} 381 382define <2 x i1> @test28vec(<2 x i8> %x) { 383; CHECK-LABEL: @test28vec( 384; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i8> [[X:%.*]], zeroinitializer 385; CHECK-NEXT: ret <2 x i1> [[CMP]] 386; 387 %shr = lshr <2 x i8> %x, <i8 7, i8 7> 388 %cmp = icmp ne <2 x i8> %shr, zeroinitializer 389 ret <2 x i1> %cmp 390} 391 392define i8 @test28a(i8 %x, i8 %y) { 393; CHECK-LABEL: @test28a( 394; CHECK-NEXT: entry: 395; CHECK-NEXT: [[I1:%.*]] = lshr i8 [[X:%.*]], 7 396; CHECK-NEXT: [[COND1_NOT:%.*]] = icmp sgt i8 [[X]], -1 397; CHECK-NEXT: br i1 [[COND1_NOT]], label [[BB2:%.*]], label [[BB1:%.*]] 398; CHECK: bb1: 399; CHECK-NEXT: ret i8 [[I1]] 400; CHECK: bb2: 401; CHECK-NEXT: [[I2:%.*]] = add i8 [[I1]], [[Y:%.*]] 402; CHECK-NEXT: ret i8 [[I2]] 403; 404entry: 405; This shouldn't be transformed. 406 %i1 = lshr i8 %x, 7 407 %cond1 = icmp ne i8 %i1, 0 408 br i1 %cond1, label %bb1, label %bb2 409bb1: 410 ret i8 %i1 411bb2: 412 %i2 = add i8 %i1, %y 413 ret i8 %i2 414} 415 416define i32 @test29(i64 %d18) { 417; CHECK-LABEL: @test29( 418; CHECK-NEXT: entry: 419; CHECK-NEXT: [[SUM_SHIFT:%.*]] = lshr i64 [[D18:%.*]], 63 420; CHECK-NEXT: [[I101:%.*]] = trunc i64 [[SUM_SHIFT]] to i32 421; CHECK-NEXT: ret i32 [[I101]] 422; 423entry: 424 %i916 = lshr i64 %d18, 32 425 %i917 = trunc i64 %i916 to i32 426 %i10 = lshr i32 %i917, 31 427 ret i32 %i10 428} 429 430define <2 x i32> @test29_uniform(<2 x i64> %d18) { 431; CHECK-LABEL: @test29_uniform( 432; CHECK-NEXT: entry: 433; CHECK-NEXT: [[SUM_SHIFT:%.*]] = lshr <2 x i64> [[D18:%.*]], <i64 63, i64 63> 434; CHECK-NEXT: [[I101:%.*]] = trunc <2 x i64> [[SUM_SHIFT]] to <2 x i32> 435; CHECK-NEXT: ret <2 x i32> [[I101]] 436; 437entry: 438 %i916 = lshr <2 x i64> %d18, <i64 32, i64 32> 439 %i917 = trunc <2 x i64> %i916 to <2 x i32> 440 %i10 = lshr <2 x i32> %i917, <i32 31, i32 31> 441 ret <2 x i32> %i10 442} 443 444define <2 x i32> @test29_nonuniform(<2 x i64> %d18) { 445; CHECK-LABEL: @test29_nonuniform( 446; CHECK-NEXT: entry: 447; CHECK-NEXT: [[I916:%.*]] = lshr <2 x i64> [[D18:%.*]], <i64 32, i64 15> 448; CHECK-NEXT: [[I917:%.*]] = trunc <2 x i64> [[I916]] to <2 x i32> 449; CHECK-NEXT: [[I10:%.*]] = lshr <2 x i32> [[I917]], <i32 31, i32 22> 450; CHECK-NEXT: ret <2 x i32> [[I10]] 451; 452entry: 453 %i916 = lshr <2 x i64> %d18, <i64 32, i64 15> 454 %i917 = trunc <2 x i64> %i916 to <2 x i32> 455 %i10 = lshr <2 x i32> %i917, <i32 31, i32 22> 456 ret <2 x i32> %i10 457} 458 459define <2 x i32> @test29_poison(<2 x i64> %d18) { 460; CHECK-LABEL: @test29_poison( 461; CHECK-NEXT: entry: 462; CHECK-NEXT: [[I916:%.*]] = lshr <2 x i64> [[D18:%.*]], <i64 32, i64 poison> 463; CHECK-NEXT: [[I917:%.*]] = trunc <2 x i64> [[I916]] to <2 x i32> 464; CHECK-NEXT: [[I10:%.*]] = lshr <2 x i32> [[I917]], <i32 31, i32 poison> 465; CHECK-NEXT: ret <2 x i32> [[I10]] 466; 467entry: 468 %i916 = lshr <2 x i64> %d18, <i64 32, i64 poison> 469 %i917 = trunc <2 x i64> %i916 to <2 x i32> 470 %i10 = lshr <2 x i32> %i917, <i32 31, i32 poison> 471 ret <2 x i32> %i10 472} 473 474define i32 @test30(i32 %A, i32 %B, i32 %C) { 475; CHECK-LABEL: @test30( 476; CHECK-NEXT: [[X1:%.*]] = and i32 [[A:%.*]], [[B:%.*]] 477; CHECK-NEXT: [[Z:%.*]] = shl i32 [[X1]], [[C:%.*]] 478; CHECK-NEXT: ret i32 [[Z]] 479; 480 %X = shl i32 %A, %C 481 %Y = shl i32 %B, %C 482 %Z = and i32 %X, %Y 483 ret i32 %Z 484} 485 486define i32 @test31(i32 %A, i32 %B, i32 %C) { 487; CHECK-LABEL: @test31( 488; CHECK-NEXT: [[X1:%.*]] = or i32 [[A:%.*]], [[B:%.*]] 489; CHECK-NEXT: [[Z:%.*]] = lshr i32 [[X1]], [[C:%.*]] 490; CHECK-NEXT: ret i32 [[Z]] 491; 492 %X = lshr i32 %A, %C 493 %Y = lshr i32 %B, %C 494 %Z = or i32 %X, %Y 495 ret i32 %Z 496} 497 498define i32 @test32(i32 %A, i32 %B, i32 %C) { 499; CHECK-LABEL: @test32( 500; CHECK-NEXT: [[X1:%.*]] = xor i32 [[A:%.*]], [[B:%.*]] 501; CHECK-NEXT: [[Z:%.*]] = ashr i32 [[X1]], [[C:%.*]] 502; CHECK-NEXT: ret i32 [[Z]] 503; 504 %X = ashr i32 %A, %C 505 %Y = ashr i32 %B, %C 506 %Z = xor i32 %X, %Y 507 ret i32 %Z 508} 509 510define i1 @test33(i32 %X) { 511; CHECK-LABEL: @test33( 512; CHECK-NEXT: [[I1_MASK:%.*]] = and i32 [[X:%.*]], 16777216 513; CHECK-NEXT: [[I2:%.*]] = icmp ne i32 [[I1_MASK]], 0 514; CHECK-NEXT: ret i1 [[I2]] 515; 516 %i1 = shl i32 %X, 7 517 %i2 = icmp slt i32 %i1, 0 518 ret i1 %i2 519} 520 521define <2 x i1> @test33vec(<2 x i32> %X) { 522; CHECK-LABEL: @test33vec( 523; CHECK-NEXT: [[I1_MASK:%.*]] = and <2 x i32> [[X:%.*]], <i32 16777216, i32 16777216> 524; CHECK-NEXT: [[I2:%.*]] = icmp ne <2 x i32> [[I1_MASK]], zeroinitializer 525; CHECK-NEXT: ret <2 x i1> [[I2]] 526; 527 %i1 = shl <2 x i32> %X, <i32 7, i32 7> 528 %i2 = icmp slt <2 x i32> %i1, zeroinitializer 529 ret <2 x i1> %i2 530} 531 532define i1 @test34(i32 %X) { 533; CHECK-LABEL: @test34( 534; CHECK-NEXT: ret i1 false 535; 536 %i1 = lshr i32 %X, 7 537 %i2 = icmp slt i32 %i1, 0 538 ret i1 %i2 539} 540 541define i1 @test35(i32 %X) { 542; CHECK-LABEL: @test35( 543; CHECK-NEXT: [[I2:%.*]] = icmp slt i32 [[X:%.*]], 0 544; CHECK-NEXT: ret i1 [[I2]] 545; 546 %i1 = ashr i32 %X, 7 547 %i2 = icmp slt i32 %i1, 0 548 ret i1 %i2 549} 550 551define <2 x i1> @test35vec(<2 x i32> %X) { 552; CHECK-LABEL: @test35vec( 553; CHECK-NEXT: [[I2:%.*]] = icmp slt <2 x i32> [[X:%.*]], zeroinitializer 554; CHECK-NEXT: ret <2 x i1> [[I2]] 555; 556 %i1 = ashr <2 x i32> %X, <i32 7, i32 7> 557 %i2 = icmp slt <2 x i32> %i1, zeroinitializer 558 ret <2 x i1> %i2 559} 560 561define i128 @test36(i128 %A, i128 %B) { 562; CHECK-LABEL: @test36( 563; CHECK-NEXT: [[I231:%.*]] = or i128 [[B:%.*]], [[A:%.*]] 564; CHECK-NEXT: [[INS:%.*]] = and i128 [[I231]], 18446744073709551615 565; CHECK-NEXT: ret i128 [[INS]] 566; 567 %i27 = shl i128 %A, 64 568 %i23 = shl i128 %B, 64 569 %ins = or i128 %i23, %i27 570 %i45 = lshr i128 %ins, 64 571 ret i128 %i45 572} 573 574define i64 @test37(i128 %A, i32 %B) { 575; CHECK-LABEL: @test37( 576; CHECK-NEXT: [[I22:%.*]] = zext i32 [[B:%.*]] to i128 577; CHECK-NEXT: [[I23:%.*]] = shl nuw nsw i128 [[I22]], 32 578; CHECK-NEXT: [[INS:%.*]] = or i128 [[I23]], [[A:%.*]] 579; CHECK-NEXT: [[I46:%.*]] = trunc i128 [[INS]] to i64 580; CHECK-NEXT: ret i64 [[I46]] 581; 582 %i27 = shl i128 %A, 64 583 %i22 = zext i32 %B to i128 584 %i23 = shl i128 %i22, 96 585 %ins = or i128 %i23, %i27 586 %i45 = lshr i128 %ins, 64 587 %i46 = trunc i128 %i45 to i64 588 ret i64 %i46 589} 590 591define <2 x i32> @shl_nuw_nsw_splat_vec(<2 x i8> %x) { 592; CHECK-LABEL: @shl_nuw_nsw_splat_vec( 593; CHECK-NEXT: [[T2:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32> 594; CHECK-NEXT: [[T3:%.*]] = shl nuw nsw <2 x i32> [[T2]], <i32 17, i32 17> 595; CHECK-NEXT: ret <2 x i32> [[T3]] 596; 597 %t2 = zext <2 x i8> %x to <2 x i32> 598 %t3 = shl <2 x i32> %t2, <i32 17, i32 17> 599 ret <2 x i32> %t3 600} 601 602define i32 @test38(i32 %x) nounwind readnone { 603; CHECK-LABEL: @test38( 604; CHECK-NEXT: [[REM1:%.*]] = and i32 [[X:%.*]], 31 605; CHECK-NEXT: [[SHL:%.*]] = shl i32 1, [[REM1]] 606; CHECK-NEXT: ret i32 [[SHL]] 607; 608 %rem = srem i32 %x, 32 609 %shl = shl i32 1, %rem 610 ret i32 %shl 611} 612 613define <2 x i32> @test38_uniform(<2 x i32> %x) nounwind readnone { 614; CHECK-LABEL: @test38_uniform( 615; CHECK-NEXT: [[REM1:%.*]] = and <2 x i32> [[X:%.*]], <i32 31, i32 31> 616; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i32> <i32 1, i32 1>, [[REM1]] 617; CHECK-NEXT: ret <2 x i32> [[SHL]] 618; 619 %rem = srem <2 x i32> %x, <i32 32, i32 32> 620 %shl = shl <2 x i32> <i32 1, i32 1>, %rem 621 ret <2 x i32> %shl 622} 623 624define <3 x i32> @test38_nonuniform(<3 x i32> %x) nounwind readnone { 625; CHECK-LABEL: @test38_nonuniform( 626; CHECK-NEXT: [[REM1:%.*]] = and <3 x i32> [[X:%.*]], <i32 31, i32 15, i32 0> 627; CHECK-NEXT: [[SHL:%.*]] = shl <3 x i32> <i32 1, i32 1, i32 1>, [[REM1]] 628; CHECK-NEXT: ret <3 x i32> [[SHL]] 629; 630 %rem = srem <3 x i32> %x, <i32 32, i32 16, i32 1> 631 %shl = shl <3 x i32> <i32 1, i32 1, i32 1>, %rem 632 ret <3 x i32> %shl 633} 634 635define <2 x i32> @test38_poison(<2 x i32> %x) nounwind readnone { 636; CHECK-LABEL: @test38_poison( 637; CHECK-NEXT: ret <2 x i32> poison 638; 639 %rem = srem <2 x i32> %x, <i32 32, i32 poison> 640 %shl = shl <2 x i32> <i32 1, i32 1>, %rem 641 ret <2 x i32> %shl 642} 643 644; <rdar://problem/8756731> 645define i8 @test39(i32 %a0) { 646; CHECK-LABEL: @test39( 647; CHECK-NEXT: entry: 648; CHECK-NEXT: [[I4:%.*]] = trunc i32 [[A0:%.*]] to i8 649; CHECK-NEXT: [[I5:%.*]] = shl i8 [[I4]], 5 650; CHECK-NEXT: [[I49:%.*]] = shl i8 [[I4]], 6 651; CHECK-NEXT: [[I50:%.*]] = and i8 [[I49]], 64 652; CHECK-NEXT: [[I51:%.*]] = xor i8 [[I50]], [[I5]] 653; CHECK-NEXT: [[TMP0:%.*]] = lshr exact i8 [[I5]], 3 654; CHECK-NEXT: [[I54:%.*]] = and i8 [[TMP0]], 16 655; CHECK-NEXT: [[I551:%.*]] = or i8 [[I54]], [[I51]] 656; CHECK-NEXT: ret i8 [[I551]] 657; 658entry: 659 %i4 = trunc i32 %a0 to i8 660 %i5 = shl i8 %i4, 5 661 %i48 = and i8 %i5, 32 662 %i49 = lshr i8 %i48, 5 663 %i50 = mul i8 %i49, 64 664 %i51 = xor i8 %i50, %i5 665 %i52 = and i8 %i51, -128 666 %i53 = lshr i8 %i52, 7 667 %i54 = mul i8 %i53, 16 668 %i55 = xor i8 %i54, %i51 669 ret i8 %i55 670} 671 672define i32 @test42(i32 %a, i32 %b) nounwind { 673; CHECK-LABEL: @test42( 674; CHECK-NEXT: [[DIV:%.*]] = lshr exact i32 4096, [[B:%.*]] 675; CHECK-NEXT: [[DIV2:%.*]] = udiv i32 [[A:%.*]], [[DIV]] 676; CHECK-NEXT: ret i32 [[DIV2]] 677; 678 %div = lshr i32 4096, %b ; must be exact otherwise we'd divide by zero 679 %div2 = udiv i32 %a, %div 680 ret i32 %div2 681} 682 683define <2 x i32> @test42vec(<2 x i32> %a, <2 x i32> %b) { 684; CHECK-LABEL: @test42vec( 685; CHECK-NEXT: [[DIV:%.*]] = lshr exact <2 x i32> <i32 4096, i32 4096>, [[B:%.*]] 686; CHECK-NEXT: [[DIV2:%.*]] = udiv <2 x i32> [[A:%.*]], [[DIV]] 687; CHECK-NEXT: ret <2 x i32> [[DIV2]] 688; 689 %div = lshr <2 x i32> <i32 4096, i32 4096>, %b ; must be exact otherwise we'd divide by zero 690 %div2 = udiv <2 x i32> %a, %div 691 ret <2 x i32> %div2 692} 693 694define i32 @test43(i32 %a, i32 %b) nounwind { 695; CHECK-LABEL: @test43( 696; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[B:%.*]], 12 697; CHECK-NEXT: [[DIV21:%.*]] = lshr i32 [[A:%.*]], [[TMP1]] 698; CHECK-NEXT: ret i32 [[DIV21]] 699; 700 %div = shl i32 4096, %b ; must be exact otherwise we'd divide by zero 701 %div2 = udiv i32 %a, %div 702 ret i32 %div2 703} 704 705define i32 @test44(i32 %a) nounwind { 706; CHECK-LABEL: @test44( 707; CHECK-NEXT: [[Y:%.*]] = shl i32 [[A:%.*]], 5 708; CHECK-NEXT: ret i32 [[Y]] 709; 710 %y = shl nuw i32 %a, 1 711 %z = shl i32 %y, 4 712 ret i32 %z 713} 714 715define i32 @test45(i32 %a) nounwind { 716; CHECK-LABEL: @test45( 717; CHECK-NEXT: [[Y:%.*]] = lshr i32 [[A:%.*]], 5 718; CHECK-NEXT: ret i32 [[Y]] 719; 720 %y = lshr exact i32 %a, 1 721 %z = lshr i32 %y, 4 722 ret i32 %z 723} 724 725; (X >>?exact C1) << C2 --> X >>?exact (C1-C2) 726 727define i32 @test46(i32 %a) { 728; CHECK-LABEL: @test46( 729; CHECK-NEXT: [[Z:%.*]] = ashr exact i32 [[A:%.*]], 2 730; CHECK-NEXT: ret i32 [[Z]] 731; 732 %y = ashr exact i32 %a, 3 733 %z = shl i32 %y, 1 734 ret i32 %z 735} 736 737; (X >>?exact C1) << C2 --> X >>?exact (C1-C2) 738 739define <2 x i32> @test46_splat_vec(<2 x i32> %a) { 740; CHECK-LABEL: @test46_splat_vec( 741; CHECK-NEXT: [[Z:%.*]] = ashr exact <2 x i32> [[A:%.*]], <i32 2, i32 2> 742; CHECK-NEXT: ret <2 x i32> [[Z]] 743; 744 %y = ashr exact <2 x i32> %a, <i32 3, i32 3> 745 %z = shl <2 x i32> %y, <i32 1, i32 1> 746 ret <2 x i32> %z 747} 748 749; (X >>?exact C1) << C2 --> X >>?exact (C1-C2) 750 751define i8 @test47(i8 %a) { 752; CHECK-LABEL: @test47( 753; CHECK-NEXT: [[Z:%.*]] = lshr exact i8 [[A:%.*]], 2 754; CHECK-NEXT: ret i8 [[Z]] 755; 756 %y = lshr exact i8 %a, 3 757 %z = shl i8 %y, 1 758 ret i8 %z 759} 760 761; (X >>?exact C1) << C2 --> X >>?exact (C1-C2) 762 763define <2 x i8> @test47_splat_vec(<2 x i8> %a) { 764; CHECK-LABEL: @test47_splat_vec( 765; CHECK-NEXT: [[Z:%.*]] = lshr exact <2 x i8> [[A:%.*]], <i8 2, i8 2> 766; CHECK-NEXT: ret <2 x i8> [[Z]] 767; 768 %y = lshr exact <2 x i8> %a, <i8 3, i8 3> 769 %z = shl <2 x i8> %y, <i8 1, i8 1> 770 ret <2 x i8> %z 771} 772 773; (X >>u,exact C1) << C2 --> X << (C2-C1) when C2 > C1 774 775define i32 @test48(i32 %x) { 776; CHECK-LABEL: @test48( 777; CHECK-NEXT: [[B:%.*]] = shl i32 [[X:%.*]], 2 778; CHECK-NEXT: ret i32 [[B]] 779; 780 %A = lshr exact i32 %x, 1 781 %B = shl i32 %A, 3 782 ret i32 %B 783} 784 785; Verify that wrap flags are preserved from the original 'shl'. 786 787define i32 @test48_nuw_nsw(i32 %x) { 788; CHECK-LABEL: @test48_nuw_nsw( 789; CHECK-NEXT: [[B:%.*]] = shl nuw nsw i32 [[X:%.*]], 2 790; CHECK-NEXT: ret i32 [[B]] 791; 792 %A = lshr exact i32 %x, 1 793 %B = shl nuw nsw i32 %A, 3 794 ret i32 %B 795} 796 797; (X >>u,exact C1) << C2 --> X << (C2-C1) when splatted C2 > C1 798 799define <2 x i32> @test48_splat_vec(<2 x i32> %x) { 800; CHECK-LABEL: @test48_splat_vec( 801; CHECK-NEXT: [[B:%.*]] = shl nuw nsw <2 x i32> [[X:%.*]], <i32 2, i32 2> 802; CHECK-NEXT: ret <2 x i32> [[B]] 803; 804 %A = lshr exact <2 x i32> %x, <i32 1, i32 1> 805 %B = shl nsw nuw <2 x i32> %A, <i32 3, i32 3> 806 ret <2 x i32> %B 807} 808 809; (X >>s,exact C1) << C2 --> X << (C2-C1) when C2 > C1 810 811define i32 @test49(i32 %x) { 812; CHECK-LABEL: @test49( 813; CHECK-NEXT: [[B:%.*]] = shl i32 [[X:%.*]], 2 814; CHECK-NEXT: ret i32 [[B]] 815; 816 %A = ashr exact i32 %x, 1 817 %B = shl i32 %A, 3 818 ret i32 %B 819} 820 821; Verify that wrap flags are preserved from the original 'shl'. 822 823define i32 @test49_nuw_nsw(i32 %x) { 824; CHECK-LABEL: @test49_nuw_nsw( 825; CHECK-NEXT: [[B:%.*]] = shl nuw nsw i32 [[X:%.*]], 2 826; CHECK-NEXT: ret i32 [[B]] 827; 828 %A = ashr exact i32 %x, 1 829 %B = shl nuw nsw i32 %A, 3 830 ret i32 %B 831} 832 833; (X >>s,exact C1) << C2 --> X << (C2-C1) when splatted C2 > C1 834 835define <2 x i32> @test49_splat_vec(<2 x i32> %x) { 836; CHECK-LABEL: @test49_splat_vec( 837; CHECK-NEXT: [[B:%.*]] = shl nuw nsw <2 x i32> [[X:%.*]], <i32 2, i32 2> 838; CHECK-NEXT: ret <2 x i32> [[B]] 839; 840 %A = ashr exact <2 x i32> %x, <i32 1, i32 1> 841 %B = shl nsw nuw <2 x i32> %A, <i32 3, i32 3> 842 ret <2 x i32> %B 843} 844 845; (X <<nsw C1) >>s C2 --> X >>s (C2-C1) 846 847define i32 @test50(i32 %x) { 848; CHECK-LABEL: @test50( 849; CHECK-NEXT: [[B:%.*]] = ashr i32 [[X:%.*]], 2 850; CHECK-NEXT: ret i32 [[B]] 851; 852 %A = shl nsw i32 %x, 1 853 %B = ashr i32 %A, 3 854 ret i32 %B 855} 856 857; (X <<nsw C1) >>s C2 --> X >>s (C2-C1) 858; Also, check that exact is propagated. 859 860define <2 x i32> @test50_splat_vec(<2 x i32> %x) { 861; CHECK-LABEL: @test50_splat_vec( 862; CHECK-NEXT: [[B:%.*]] = ashr exact <2 x i32> [[X:%.*]], <i32 2, i32 2> 863; CHECK-NEXT: ret <2 x i32> [[B]] 864; 865 %A = shl nsw <2 x i32> %x, <i32 1, i32 1> 866 %B = ashr exact <2 x i32> %A, <i32 3, i32 3> 867 ret <2 x i32> %B 868} 869 870; (X <<nuw C1) >>u C2 --> X >>u (C2-C1) 871 872define i32 @test51(i32 %x) { 873; CHECK-LABEL: @test51( 874; CHECK-NEXT: [[B:%.*]] = lshr i32 [[X:%.*]], 2 875; CHECK-NEXT: ret i32 [[B]] 876; 877 %A = shl nuw i32 %x, 1 878 %B = lshr i32 %A, 3 879 ret i32 %B 880} 881 882; (X <<nuw C1) >>u C2 --> X >>u (C2-C1) with splats 883; Also, check that exact is propagated. 884 885define <2 x i32> @test51_splat_vec(<2 x i32> %x) { 886; CHECK-LABEL: @test51_splat_vec( 887; CHECK-NEXT: [[B:%.*]] = lshr exact <2 x i32> [[X:%.*]], <i32 2, i32 2> 888; CHECK-NEXT: ret <2 x i32> [[B]] 889; 890 %A = shl nuw <2 x i32> %x, <i32 1, i32 1> 891 %B = lshr exact <2 x i32> %A, <i32 3, i32 3> 892 ret <2 x i32> %B 893} 894 895; (X << C1) >>u C2 --> X >>u (C2-C1) & (-1 >> C2) 896; Also, check that exact is propagated. 897 898define i32 @test51_no_nuw(i32 %x) { 899; CHECK-LABEL: @test51_no_nuw( 900; CHECK-NEXT: [[TMP1:%.*]] = lshr exact i32 [[X:%.*]], 2 901; CHECK-NEXT: [[B:%.*]] = and i32 [[TMP1]], 536870911 902; CHECK-NEXT: ret i32 [[B]] 903; 904 %A = shl i32 %x, 1 905 %B = lshr exact i32 %A, 3 906 ret i32 %B 907} 908 909; (X << C1) >>u C2 --> X >>u (C2-C1) & (-1 >> C2) 910 911define <2 x i32> @test51_no_nuw_splat_vec(<2 x i32> %x) { 912; CHECK-LABEL: @test51_no_nuw_splat_vec( 913; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 2, i32 2> 914; CHECK-NEXT: [[B:%.*]] = and <2 x i32> [[TMP1]], <i32 536870911, i32 536870911> 915; CHECK-NEXT: ret <2 x i32> [[B]] 916; 917 %A = shl <2 x i32> %x, <i32 1, i32 1> 918 %B = lshr <2 x i32> %A, <i32 3, i32 3> 919 ret <2 x i32> %B 920} 921 922; (X <<nsw C1) >>s C2 --> X <<nsw (C1 - C2) 923 924define i32 @test52(i32 %x) { 925; CHECK-LABEL: @test52( 926; CHECK-NEXT: [[B:%.*]] = shl nsw i32 [[X:%.*]], 2 927; CHECK-NEXT: ret i32 [[B]] 928; 929 %A = shl nsw i32 %x, 3 930 %B = ashr i32 %A, 1 931 ret i32 %B 932} 933 934; (X <<nsw C1) >>s C2 --> X <<nsw (C1 - C2) 935 936define <2 x i32> @test52_splat_vec(<2 x i32> %x) { 937; CHECK-LABEL: @test52_splat_vec( 938; CHECK-NEXT: [[B:%.*]] = shl nsw <2 x i32> [[X:%.*]], <i32 2, i32 2> 939; CHECK-NEXT: ret <2 x i32> [[B]] 940; 941 %A = shl nsw <2 x i32> %x, <i32 3, i32 3> 942 %B = ashr <2 x i32> %A, <i32 1, i32 1> 943 ret <2 x i32> %B 944} 945 946; (X <<nuw C1) >>u C2 --> X <<nuw (C1 - C2) 947 948define i32 @test53(i32 %x) { 949; CHECK-LABEL: @test53( 950; CHECK-NEXT: [[B:%.*]] = shl nuw i32 [[X:%.*]], 2 951; CHECK-NEXT: ret i32 [[B]] 952; 953 %A = shl nuw i32 %x, 3 954 %B = lshr i32 %A, 1 955 ret i32 %B 956} 957 958; (X <<nuw C1) >>u C2 --> X <<nuw (C1 - C2) 959 960define <2 x i32> @test53_splat_vec(<2 x i32> %x) { 961; CHECK-LABEL: @test53_splat_vec( 962; CHECK-NEXT: [[B:%.*]] = shl nuw <2 x i32> [[X:%.*]], <i32 2, i32 2> 963; CHECK-NEXT: ret <2 x i32> [[B]] 964; 965 %A = shl nuw <2 x i32> %x, <i32 3, i32 3> 966 %B = lshr <2 x i32> %A, <i32 1, i32 1> 967 ret <2 x i32> %B 968} 969 970; (X << C1) >>u C2 --> X << (C1 - C2) & (-1 >> C2) 971 972define i8 @test53_no_nuw(i8 %x) { 973; CHECK-LABEL: @test53_no_nuw( 974; CHECK-NEXT: [[TMP1:%.*]] = shl i8 [[X:%.*]], 2 975; CHECK-NEXT: [[B:%.*]] = and i8 [[TMP1]], 124 976; CHECK-NEXT: ret i8 [[B]] 977; 978 %A = shl i8 %x, 3 979 %B = lshr i8 %A, 1 980 ret i8 %B 981} 982 983; (X << C1) >>u C2 --> X << (C1 - C2) & (-1 >> C2) 984 985define <2 x i8> @test53_no_nuw_splat_vec(<2 x i8> %x) { 986; CHECK-LABEL: @test53_no_nuw_splat_vec( 987; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i8> [[X:%.*]], <i8 2, i8 2> 988; CHECK-NEXT: [[B:%.*]] = and <2 x i8> [[TMP1]], <i8 124, i8 124> 989; CHECK-NEXT: ret <2 x i8> [[B]] 990; 991 %A = shl <2 x i8> %x, <i8 3, i8 3> 992 %B = lshr <2 x i8> %A, <i8 1, i8 1> 993 ret <2 x i8> %B 994} 995 996define i32 @test54(i32 %x) { 997; CHECK-LABEL: @test54( 998; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 3 999; CHECK-NEXT: [[AND:%.*]] = and i32 [[TMP1]], 16 1000; CHECK-NEXT: ret i32 [[AND]] 1001; 1002 %shr2 = lshr i32 %x, 1 1003 %shl = shl i32 %shr2, 4 1004 %and = and i32 %shl, 16 1005 ret i32 %and 1006} 1007 1008define <2 x i32> @test54_splat_vec(<2 x i32> %x) { 1009; CHECK-LABEL: @test54_splat_vec( 1010; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i32> [[X:%.*]], <i32 3, i32 3> 1011; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[TMP1]], <i32 16, i32 16> 1012; CHECK-NEXT: ret <2 x i32> [[AND]] 1013; 1014 %shr2 = lshr <2 x i32> %x, <i32 1, i32 1> 1015 %shl = shl <2 x i32> %shr2, <i32 4, i32 4> 1016 %and = and <2 x i32> %shl, <i32 16, i32 16> 1017 ret <2 x i32> %and 1018} 1019 1020define i32 @test55(i32 %x) { 1021; CHECK-LABEL: @test55( 1022; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 3 1023; CHECK-NEXT: [[OR:%.*]] = or i32 [[TMP1]], 8 1024; CHECK-NEXT: ret i32 [[OR]] 1025; 1026 %shr2 = lshr i32 %x, 1 1027 %shl = shl i32 %shr2, 4 1028 %or = or i32 %shl, 8 1029 ret i32 %or 1030} 1031 1032define i32 @test56(i32 %x) { 1033; CHECK-LABEL: @test56( 1034; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 3 1035; CHECK-NEXT: [[SHL:%.*]] = and i32 [[TMP1]], -16 1036; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], 7 1037; CHECK-NEXT: ret i32 [[OR]] 1038; 1039 %shr2 = lshr i32 %x, 1 1040 %shl = shl i32 %shr2, 4 1041 %or = or i32 %shl, 7 1042 ret i32 %or 1043} 1044 1045define i32 @test57(i32 %x) { 1046; CHECK-LABEL: @test57( 1047; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 3 1048; CHECK-NEXT: [[SHL:%.*]] = and i32 [[TMP1]], -16 1049; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], 7 1050; CHECK-NEXT: ret i32 [[OR]] 1051; 1052 %shr = ashr i32 %x, 1 1053 %shl = shl i32 %shr, 4 1054 %or = or i32 %shl, 7 1055 ret i32 %or 1056} 1057 1058define i32 @test58(i32 %x) { 1059; CHECK-LABEL: @test58( 1060; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 3 1061; CHECK-NEXT: [[OR:%.*]] = or i32 [[TMP1]], 1 1062; CHECK-NEXT: ret i32 [[OR]] 1063; 1064 %shr = ashr i32 %x, 4 1065 %shl = shl i32 %shr, 1 1066 %or = or i32 %shl, 1 1067 ret i32 %or 1068} 1069 1070define <2 x i32> @test58_splat_vec(<2 x i32> %x) { 1071; CHECK-LABEL: @test58_splat_vec( 1072; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i32> [[X:%.*]], <i32 3, i32 3> 1073; CHECK-NEXT: [[OR:%.*]] = or <2 x i32> [[TMP1]], <i32 1, i32 1> 1074; CHECK-NEXT: ret <2 x i32> [[OR]] 1075; 1076 %shr = ashr <2 x i32> %x, <i32 4, i32 4> 1077 %shl = shl <2 x i32> %shr, <i32 1, i32 1> 1078 %or = or <2 x i32> %shl, <i32 1, i32 1> 1079 ret <2 x i32> %or 1080} 1081 1082define i32 @test59(i32 %x) { 1083; CHECK-LABEL: @test59( 1084; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 3 1085; CHECK-NEXT: [[SHL:%.*]] = and i32 [[TMP1]], -4 1086; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], 2 1087; CHECK-NEXT: ret i32 [[OR]] 1088; 1089 %shr = ashr i32 %x, 4 1090 %shl = shl i32 %shr, 1 1091 %or = or i32 %shl, 2 1092 ret i32 %or 1093} 1094 1095; propagate "exact" trait 1096define i32 @test60(i32 %x) { 1097; CHECK-LABEL: @test60( 1098; CHECK-NEXT: [[SHL:%.*]] = ashr exact i32 [[X:%.*]], 3 1099; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], 1 1100; CHECK-NEXT: ret i32 [[OR]] 1101; 1102 %shr = ashr exact i32 %x, 4 1103 %shl = shl i32 %shr, 1 1104 %or = or i32 %shl, 1 1105 ret i32 %or 1106} 1107 1108; PR17026 1109define void @test61(i128 %arg, i1 %c1, i1 %c2, i1 %c3, i1 %c4) { 1110; CHECK-LABEL: @test61( 1111; CHECK-NEXT: bb: 1112; CHECK-NEXT: br i1 [[C1:%.*]], label [[BB1:%.*]], label [[BB12:%.*]] 1113; CHECK: bb1: 1114; CHECK-NEXT: br label [[BB2:%.*]] 1115; CHECK: bb2: 1116; CHECK-NEXT: br i1 [[C2:%.*]], label [[BB3:%.*]], label [[BB7:%.*]] 1117; CHECK: bb3: 1118; CHECK-NEXT: br label [[BB8:%.*]] 1119; CHECK: bb7: 1120; CHECK-NEXT: br i1 [[C3:%.*]], label [[BB8]], label [[BB2]] 1121; CHECK: bb8: 1122; CHECK-NEXT: br i1 undef, label [[BB11:%.*]], label [[BB12]] 1123; CHECK: bb11: 1124; CHECK-NEXT: br i1 [[C4:%.*]], label [[BB1]], label [[BB12]] 1125; CHECK: bb12: 1126; CHECK-NEXT: ret void 1127; 1128bb: 1129 br i1 %c1, label %bb1, label %bb12 1130 1131bb1: ; preds = %bb11, %bb 1132 br label %bb2 1133 1134bb2: ; preds = %bb7, %bb1 1135 br i1 %c2, label %bb3, label %bb7 1136 1137bb3: ; preds = %bb2 1138 %i = lshr i128 %arg, 36893488147419103232 1139 %i4 = shl i128 %i, 0 1140 %i5 = or i128 %i4, 0 1141 %i6 = trunc i128 %i5 to i16 1142 br label %bb8 1143 1144bb7: ; preds = %bb2 1145 br i1 %c3, label %bb8, label %bb2 1146 1147bb8: ; preds = %bb7, %bb3 1148 %i9 = phi i16 [ %i6, %bb3 ], [ poison, %bb7 ] 1149 %i10 = icmp eq i16 %i9, 0 1150 br i1 %i10, label %bb11, label %bb12 1151 1152bb11: ; preds = %bb8 1153 br i1 %c4, label %bb1, label %bb12 1154 1155bb12: ; preds = %bb11, %bb8, %bb 1156 ret void 1157} 1158 1159define i32 @test62(i32 %a) { 1160; CHECK-LABEL: @test62( 1161; CHECK-NEXT: ret i32 poison 1162; 1163 %b = ashr i32 %a, 32 ; shift all bits out 1164 ret i32 %b 1165} 1166 1167define <4 x i32> @test62_splat_vector(<4 x i32> %a) { 1168; CHECK-LABEL: @test62_splat_vector( 1169; CHECK-NEXT: ret <4 x i32> poison 1170; 1171 %b = ashr <4 x i32> %a, <i32 32, i32 32, i32 32, i32 32> ; shift all bits out 1172 ret <4 x i32> %b 1173} 1174 1175define <4 x i32> @test62_non_splat_vector(<4 x i32> %a) { 1176; CHECK-LABEL: @test62_non_splat_vector( 1177; CHECK-NEXT: [[B:%.*]] = ashr <4 x i32> [[A:%.*]], <i32 32, i32 0, i32 1, i32 2> 1178; CHECK-NEXT: ret <4 x i32> [[B]] 1179; 1180 %b = ashr <4 x i32> %a, <i32 32, i32 0, i32 1, i32 2> ; shift all bits out 1181 ret <4 x i32> %b 1182} 1183 1184define <2 x i65> @test_63(<2 x i64> %t) { 1185; CHECK-LABEL: @test_63( 1186; CHECK-NEXT: [[A:%.*]] = zext <2 x i64> [[T:%.*]] to <2 x i65> 1187; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i65> [[A]], <i65 33, i65 33> 1188; CHECK-NEXT: [[B:%.*]] = ashr exact <2 x i65> [[SEXT]], <i65 33, i65 33> 1189; CHECK-NEXT: ret <2 x i65> [[B]] 1190; 1191 %a = zext <2 x i64> %t to <2 x i65> 1192 %sext = shl <2 x i65> %a, <i65 33, i65 33> 1193 %b = ashr <2 x i65> %sext, <i65 33, i65 33> 1194 ret <2 x i65> %b 1195} 1196 1197define i32 @test_shl_zext_bool(i1 %t) { 1198; CHECK-LABEL: @test_shl_zext_bool( 1199; CHECK-NEXT: [[SHL:%.*]] = select i1 [[T:%.*]], i32 4, i32 0 1200; CHECK-NEXT: ret i32 [[SHL]] 1201; 1202 %ext = zext i1 %t to i32 1203 %shl = shl i32 %ext, 2 1204 ret i32 %shl 1205} 1206 1207define <2 x i32> @test_shl_zext_bool_splat(<2 x i1> %t) { 1208; CHECK-LABEL: @test_shl_zext_bool_splat( 1209; CHECK-NEXT: [[SHL:%.*]] = select <2 x i1> [[T:%.*]], <2 x i32> <i32 8, i32 8>, <2 x i32> zeroinitializer 1210; CHECK-NEXT: ret <2 x i32> [[SHL]] 1211; 1212 %ext = zext <2 x i1> %t to <2 x i32> 1213 %shl = shl <2 x i32> %ext, <i32 3, i32 3> 1214 ret <2 x i32> %shl 1215} 1216 1217define <2 x i32> @test_shl_zext_bool_vec(<2 x i1> %t) { 1218; CHECK-LABEL: @test_shl_zext_bool_vec( 1219; CHECK-NEXT: [[SHL:%.*]] = select <2 x i1> [[T:%.*]], <2 x i32> <i32 4, i32 8>, <2 x i32> zeroinitializer 1220; CHECK-NEXT: ret <2 x i32> [[SHL]] 1221; 1222 %ext = zext <2 x i1> %t to <2 x i32> 1223 %shl = shl <2 x i32> %ext, <i32 2, i32 3> 1224 ret <2 x i32> %shl 1225} 1226 1227define i32 @test_shl_zext_bool_not_constant(i1 %cmp, i32 %shamt) { 1228; CHECK-LABEL: @test_shl_zext_bool_not_constant( 1229; CHECK-NEXT: [[CONV3:%.*]] = zext i1 [[CMP:%.*]] to i32 1230; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[CONV3]], [[SHAMT:%.*]] 1231; CHECK-NEXT: ret i32 [[SHL]] 1232; 1233 %conv3 = zext i1 %cmp to i32 1234 %shl = shl i32 %conv3, %shamt 1235 ret i32 %shl 1236} 1237 1238define i64 @shl_zext(i32 %t) { 1239; CHECK-LABEL: @shl_zext( 1240; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[T:%.*]], 8 1241; CHECK-NEXT: [[SHL:%.*]] = zext i32 [[TMP1]] to i64 1242; CHECK-NEXT: ret i64 [[SHL]] 1243; 1244 %and = and i32 %t, 16777215 1245 %ext = zext i32 %and to i64 1246 %shl = shl i64 %ext, 8 1247 ret i64 %shl 1248} 1249 1250declare void @use(i64) 1251 1252define i64 @shl_zext_extra_use(i32 %t) { 1253; CHECK-LABEL: @shl_zext_extra_use( 1254; CHECK-NEXT: [[AND:%.*]] = and i32 [[T:%.*]], 16777215 1255; CHECK-NEXT: [[EXT:%.*]] = zext i32 [[AND]] to i64 1256; CHECK-NEXT: call void @use(i64 [[EXT]]) 1257; CHECK-NEXT: [[SHL:%.*]] = shl nuw nsw i64 [[EXT]], 8 1258; CHECK-NEXT: ret i64 [[SHL]] 1259; 1260 %and = and i32 %t, 16777215 1261 %ext = zext i32 %and to i64 1262 call void @use(i64 %ext) 1263 %shl = shl i64 %ext, 8 1264 ret i64 %shl 1265} 1266 1267 1268define <2 x i64> @shl_zext_splat_vec(<2 x i32> %t) { 1269; CHECK-LABEL: @shl_zext_splat_vec( 1270; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i32> [[T:%.*]], <i32 8, i32 8> 1271; CHECK-NEXT: [[SHL:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64> 1272; CHECK-NEXT: ret <2 x i64> [[SHL]] 1273; 1274 %and = and <2 x i32> %t, <i32 16777215, i32 16777215> 1275 %ext = zext <2 x i32> %and to <2 x i64> 1276 %shl = shl <2 x i64> %ext, <i64 8, i64 8> 1277 ret <2 x i64> %shl 1278} 1279 1280define i64 @shl_zext_mul(i32 %t) { 1281; CHECK-LABEL: @shl_zext_mul( 1282; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[T:%.*]], 16777215 1283; CHECK-NEXT: [[EXT:%.*]] = zext i32 [[MUL]] to i64 1284; CHECK-NEXT: [[SHL:%.*]] = shl nuw i64 [[EXT]], 32 1285; CHECK-NEXT: ret i64 [[SHL]] 1286; 1287 %mul = mul i32 %t, 16777215 1288 %ext = zext i32 %mul to i64 1289 %shl = shl i64 %ext, 32 1290 ret i64 %shl 1291} 1292 1293define <3 x i17> @shl_zext_mul_splat(<3 x i5> %t) { 1294; CHECK-LABEL: @shl_zext_mul_splat( 1295; CHECK-NEXT: [[MUL:%.*]] = mul <3 x i5> [[T:%.*]], <i5 13, i5 13, i5 13> 1296; CHECK-NEXT: [[EXT:%.*]] = zext <3 x i5> [[MUL]] to <3 x i17> 1297; CHECK-NEXT: [[SHL:%.*]] = shl nuw <3 x i17> [[EXT]], <i17 12, i17 12, i17 12> 1298; CHECK-NEXT: ret <3 x i17> [[SHL]] 1299; 1300 %mul = mul <3 x i5> %t, <i5 13, i5 13, i5 13> 1301 %ext = zext <3 x i5> %mul to <3 x i17> 1302 %shl = shl <3 x i17> %ext, <i17 12, i17 12, i17 12> 1303 ret <3 x i17> %shl 1304} 1305 1306define i64 @shl_zext_mul_low_shift_amount(i32 %t) { 1307; CHECK-LABEL: @shl_zext_mul_low_shift_amount( 1308; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[T:%.*]], 16777215 1309; CHECK-NEXT: [[EXT:%.*]] = zext i32 [[MUL]] to i64 1310; CHECK-NEXT: [[SHL:%.*]] = shl nuw nsw i64 [[EXT]], 31 1311; CHECK-NEXT: ret i64 [[SHL]] 1312; 1313 %mul = mul i32 %t, 16777215 1314 %ext = zext i32 %mul to i64 1315 %shl = shl i64 %ext, 31 1316 ret i64 %shl 1317} 1318 1319define i64 @shl_zext_mul_extra_use1(i32 %t) { 1320; CHECK-LABEL: @shl_zext_mul_extra_use1( 1321; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[T:%.*]], 16777215 1322; CHECK-NEXT: [[EXT:%.*]] = zext i32 [[MUL]] to i64 1323; CHECK-NEXT: call void @use(i64 [[EXT]]) 1324; CHECK-NEXT: [[SHL:%.*]] = shl nuw i64 [[EXT]], 32 1325; CHECK-NEXT: ret i64 [[SHL]] 1326; 1327 %mul = mul i32 %t, 16777215 1328 %ext = zext i32 %mul to i64 1329 call void @use(i64 %ext) 1330 %shl = shl i64 %ext, 32 1331 ret i64 %shl 1332} 1333 1334declare void @use_i32(i32) 1335 1336define i64 @shl_zext_mul_extra_use2(i32 %t) { 1337; CHECK-LABEL: @shl_zext_mul_extra_use2( 1338; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[T:%.*]], 16777215 1339; CHECK-NEXT: call void @use_i32(i32 [[MUL]]) 1340; CHECK-NEXT: [[EXT:%.*]] = zext i32 [[MUL]] to i64 1341; CHECK-NEXT: [[SHL:%.*]] = shl nuw i64 [[EXT]], 32 1342; CHECK-NEXT: ret i64 [[SHL]] 1343; 1344 %mul = mul i32 %t, 16777215 1345 call void @use_i32(i32 %mul) 1346 %ext = zext i32 %mul to i64 1347 %shl = shl i64 %ext, 32 1348 ret i64 %shl 1349} 1350 1351define <2 x i8> @ashr_demanded_bits_splat(<2 x i8> %x) { 1352; CHECK-LABEL: @ashr_demanded_bits_splat( 1353; CHECK-NEXT: [[SHR:%.*]] = ashr <2 x i8> [[X:%.*]], <i8 7, i8 7> 1354; CHECK-NEXT: ret <2 x i8> [[SHR]] 1355; 1356 %and = and <2 x i8> %x, <i8 128, i8 128> 1357 %shr = ashr <2 x i8> %and, <i8 7, i8 7> 1358 ret <2 x i8> %shr 1359} 1360 1361define <2 x i8> @lshr_demanded_bits_splat(<2 x i8> %x) { 1362; CHECK-LABEL: @lshr_demanded_bits_splat( 1363; CHECK-NEXT: [[SHR:%.*]] = lshr <2 x i8> [[X:%.*]], <i8 7, i8 7> 1364; CHECK-NEXT: ret <2 x i8> [[SHR]] 1365; 1366 %and = and <2 x i8> %x, <i8 128, i8 128> 1367 %shr = lshr <2 x i8> %and, <i8 7, i8 7> 1368 ret <2 x i8> %shr 1369} 1370 1371; Make sure known bits works correctly with non power of 2 bit widths. 1372define i7 @test65(i7 %a, i7 %b) { 1373; CHECK-LABEL: @test65( 1374; CHECK-NEXT: ret i7 0 1375; 1376 %shiftamt = and i7 %b, 6 ; this ensures the shift amount is even and less than the bit width. 1377 %x = lshr i7 42, %shiftamt ; 42 has a zero in every even numbered bit and a one in every odd bit. 1378 %y = and i7 %x, 1 ; this extracts the lsb which should be 0 because we shifted an even number of bits and all even bits of the shift input are 0. 1379 ret i7 %y 1380} 1381 1382define i32 @shl_select_add_true(i32 %x, i1 %cond) { 1383; CHECK-LABEL: @shl_select_add_true( 1384; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1 1385; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 14 1386; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] 1387; CHECK-NEXT: ret i32 [[TMP3]] 1388; 1389 %1 = add i32 %x, 7 1390 %2 = select i1 %cond, i32 %1, i32 %x 1391 %3 = shl i32 %2, 1 1392 ret i32 %3 1393} 1394 1395define i32 @shl_select_add_false(i32 %x, i1 %cond) { 1396; CHECK-LABEL: @shl_select_add_false( 1397; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1 1398; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 14 1399; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]] 1400; CHECK-NEXT: ret i32 [[TMP3]] 1401; 1402 %1 = add i32 %x, 7 1403 %2 = select i1 %cond, i32 %x, i32 %1 1404 %3 = shl i32 %2, 1 1405 ret i32 %3 1406} 1407 1408define i32 @shl_select_and_true(i32 %x, i1 %cond) { 1409; CHECK-LABEL: @shl_select_and_true( 1410; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1 1411; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 14 1412; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] 1413; CHECK-NEXT: ret i32 [[TMP3]] 1414; 1415 %1 = and i32 %x, 7 1416 %2 = select i1 %cond, i32 %1, i32 %x 1417 %3 = shl i32 %2, 1 1418 ret i32 %3 1419} 1420 1421define i32 @shl_select_and_false(i32 %x, i1 %cond) { 1422; CHECK-LABEL: @shl_select_and_false( 1423; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1 1424; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 14 1425; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]] 1426; CHECK-NEXT: ret i32 [[TMP3]] 1427; 1428 %1 = and i32 %x, 7 1429 %2 = select i1 %cond, i32 %x, i32 %1 1430 %3 = shl i32 %2, 1 1431 ret i32 %3 1432} 1433 1434define i32 @lshr_select_and_true(i32 %x, i1 %cond) { 1435; CHECK-LABEL: @lshr_select_and_true( 1436; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1 1437; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 3 1438; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] 1439; CHECK-NEXT: ret i32 [[TMP3]] 1440; 1441 %1 = and i32 %x, 7 1442 %2 = select i1 %cond, i32 %1, i32 %x 1443 %3 = lshr i32 %2, 1 1444 ret i32 %3 1445} 1446 1447define i32 @lshr_select_and_false(i32 %x, i1 %cond) { 1448; CHECK-LABEL: @lshr_select_and_false( 1449; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1 1450; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 3 1451; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]] 1452; CHECK-NEXT: ret i32 [[TMP3]] 1453; 1454 %1 = and i32 %x, 7 1455 %2 = select i1 %cond, i32 %x, i32 %1 1456 %3 = lshr i32 %2, 1 1457 ret i32 %3 1458} 1459 1460define i32 @ashr_select_and_true(i32 %x, i1 %cond) { 1461; CHECK-LABEL: @ashr_select_and_true( 1462; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 1 1463; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -1073741821 1464; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] 1465; CHECK-NEXT: ret i32 [[TMP3]] 1466; 1467 %1 = and i32 %x, 2147483655 1468 %2 = select i1 %cond, i32 %1, i32 %x 1469 %3 = ashr i32 %2, 1 1470 ret i32 %3 1471} 1472 1473define i32 @ashr_select_and_false(i32 %x, i1 %cond) { 1474; CHECK-LABEL: @ashr_select_and_false( 1475; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 1 1476; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -1073741821 1477; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]] 1478; CHECK-NEXT: ret i32 [[TMP3]] 1479; 1480 %1 = and i32 %x, 2147483655 1481 %2 = select i1 %cond, i32 %x, i32 %1 1482 %3 = ashr i32 %2, 1 1483 ret i32 %3 1484} 1485 1486define i32 @shl_select_or_true(i32 %x, i1 %cond) { 1487; CHECK-LABEL: @shl_select_or_true( 1488; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1 1489; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 14 1490; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] 1491; CHECK-NEXT: ret i32 [[TMP3]] 1492; 1493 %1 = or i32 %x, 7 1494 %2 = select i1 %cond, i32 %1, i32 %x 1495 %3 = shl i32 %2, 1 1496 ret i32 %3 1497} 1498 1499define i32 @shl_select_or_false(i32 %x, i1 %cond) { 1500; CHECK-LABEL: @shl_select_or_false( 1501; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1 1502; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 14 1503; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]] 1504; CHECK-NEXT: ret i32 [[TMP3]] 1505; 1506 %1 = or i32 %x, 7 1507 %2 = select i1 %cond, i32 %x, i32 %1 1508 %3 = shl i32 %2, 1 1509 ret i32 %3 1510} 1511 1512define i32 @lshr_select_or_true(i32 %x, i1 %cond) { 1513; CHECK-LABEL: @lshr_select_or_true( 1514; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1 1515; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 3 1516; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] 1517; CHECK-NEXT: ret i32 [[TMP3]] 1518; 1519 %1 = or i32 %x, 7 1520 %2 = select i1 %cond, i32 %1, i32 %x 1521 %3 = lshr i32 %2, 1 1522 ret i32 %3 1523} 1524 1525define i32 @lshr_select_or_false(i32 %x, i1 %cond) { 1526; CHECK-LABEL: @lshr_select_or_false( 1527; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1 1528; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 3 1529; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]] 1530; CHECK-NEXT: ret i32 [[TMP3]] 1531; 1532 %1 = or i32 %x, 7 1533 %2 = select i1 %cond, i32 %x, i32 %1 1534 %3 = lshr i32 %2, 1 1535 ret i32 %3 1536} 1537 1538define i32 @ashr_select_or_true(i32 %x, i1 %cond) { 1539; CHECK-LABEL: @ashr_select_or_true( 1540; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 1 1541; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 3 1542; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] 1543; CHECK-NEXT: ret i32 [[TMP3]] 1544; 1545 %1 = or i32 %x, 7 1546 %2 = select i1 %cond, i32 %1, i32 %x 1547 %3 = ashr i32 %2, 1 1548 ret i32 %3 1549} 1550 1551define i32 @ashr_select_or_false(i32 %x, i1 %cond) { 1552; CHECK-LABEL: @ashr_select_or_false( 1553; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 1 1554; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 3 1555; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]] 1556; CHECK-NEXT: ret i32 [[TMP3]] 1557; 1558 %1 = or i32 %x, 7 1559 %2 = select i1 %cond, i32 %x, i32 %1 1560 %3 = ashr i32 %2, 1 1561 ret i32 %3 1562} 1563 1564define i32 @shl_select_xor_true(i32 %x, i1 %cond) { 1565; CHECK-LABEL: @shl_select_xor_true( 1566; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1 1567; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 14 1568; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] 1569; CHECK-NEXT: ret i32 [[TMP3]] 1570; 1571 %1 = xor i32 %x, 7 1572 %2 = select i1 %cond, i32 %1, i32 %x 1573 %3 = shl i32 %2, 1 1574 ret i32 %3 1575} 1576 1577define i32 @shl_select_xor_false(i32 %x, i1 %cond) { 1578; CHECK-LABEL: @shl_select_xor_false( 1579; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 1 1580; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 14 1581; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]] 1582; CHECK-NEXT: ret i32 [[TMP3]] 1583; 1584 %1 = xor i32 %x, 7 1585 %2 = select i1 %cond, i32 %x, i32 %1 1586 %3 = shl i32 %2, 1 1587 ret i32 %3 1588} 1589 1590define i32 @lshr_select_xor_true(i32 %x, i1 %cond) { 1591; CHECK-LABEL: @lshr_select_xor_true( 1592; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1 1593; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 3 1594; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] 1595; CHECK-NEXT: ret i32 [[TMP3]] 1596; 1597 %1 = xor i32 %x, 7 1598 %2 = select i1 %cond, i32 %1, i32 %x 1599 %3 = lshr i32 %2, 1 1600 ret i32 %3 1601} 1602 1603define i32 @lshr_select_xor_false(i32 %x, i1 %cond) { 1604; CHECK-LABEL: @lshr_select_xor_false( 1605; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 1 1606; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 3 1607; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]] 1608; CHECK-NEXT: ret i32 [[TMP3]] 1609; 1610 %1 = xor i32 %x, 7 1611 %2 = select i1 %cond, i32 %x, i32 %1 1612 %3 = lshr i32 %2, 1 1613 ret i32 %3 1614} 1615 1616define i32 @ashr_select_xor_true(i32 %x, i1 %cond) { 1617; CHECK-LABEL: @ashr_select_xor_true( 1618; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 1 1619; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 3 1620; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP2]], i32 [[TMP1]] 1621; CHECK-NEXT: ret i32 [[TMP3]] 1622; 1623 %1 = xor i32 %x, 7 1624 %2 = select i1 %cond, i32 %1, i32 %x 1625 %3 = ashr i32 %2, 1 1626 ret i32 %3 1627} 1628 1629define i32 @ashr_select_xor_false(i32 %x, i1 %cond) { 1630; CHECK-LABEL: @ashr_select_xor_false( 1631; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 1 1632; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 3 1633; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[TMP1]], i32 [[TMP2]] 1634; CHECK-NEXT: ret i32 [[TMP3]] 1635; 1636 %1 = xor i32 %x, 7 1637 %2 = select i1 %cond, i32 %x, i32 %1 1638 %3 = ashr i32 %2, 1 1639 ret i32 %3 1640} 1641 1642; OSS Fuzz #4871 1643; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=4871 1644define i177 @lshr_out_of_range(i177 %Y, i177** %A2, i177*** %ptr) { 1645; CHECK-LABEL: @lshr_out_of_range( 1646; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i177 [[Y:%.*]], -1 1647; CHECK-NEXT: [[B4:%.*]] = sext i1 [[TMP1]] to i177 1648; CHECK-NEXT: [[C8:%.*]] = icmp ult i177 [[B4]], [[Y]] 1649; CHECK-NEXT: [[TMP2:%.*]] = sext i1 [[C8]] to i64 1650; CHECK-NEXT: [[G18:%.*]] = getelementptr i177*, i177** [[A2:%.*]], i64 [[TMP2]] 1651; CHECK-NEXT: store i177** [[G18]], i177*** [[PTR:%.*]], align 8 1652; CHECK-NEXT: ret i177 0 1653; 1654 %B5 = udiv i177 %Y, -1 1655 %B4 = add i177 %B5, -1 1656 %B2 = add i177 %B4, -1 1657 %B6 = mul i177 %B5, %B2 1658 %B3 = add i177 %B2, %B2 1659 %B10 = sub i177 %B5, %B3 1660 %B12 = lshr i177 %Y, %B6 1661 %C8 = icmp ugt i177 %B12, %B4 1662 %G18 = getelementptr i177*, i177** %A2, i1 %C8 1663 store i177** %G18, i177*** %ptr 1664 %B1 = udiv i177 %B10, %B6 1665 ret i177 %B1 1666} 1667 1668; OSS Fuzz #26716 1669; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=26716 1670define i177 @lshr_out_of_range2(i177 %Y, i177** %A2, i177*** %ptr) { 1671; CHECK-LABEL: @lshr_out_of_range2( 1672; CHECK-NEXT: ret i177 0 1673; 1674 %B5 = udiv i177 %Y, -1 1675 %B = sdiv i177 %B5, -1 1676 %B4 = add i177 %B5, %B 1677 %B2 = add i177 %B4, -1 1678 %B6 = mul i177 %B5, %B2 1679 %B12 = lshr i177 %Y, %B6 1680 %C8 = icmp ugt i177 %B12, %B4 1681 %G18 = getelementptr i177*, i177** %A2, i1 %C8 1682 store i177** %G18, i177*** %ptr, align 8 1683 %B1 = udiv i177 %B5, %B6 1684 ret i177 %B1 1685} 1686 1687; OSS Fuzz #5032 1688; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=5032 1689define void @ashr_out_of_range(i177* %A) { 1690; CHECK-LABEL: @ashr_out_of_range( 1691; CHECK-NEXT: [[L:%.*]] = load i177, i177* [[A:%.*]], align 4 1692; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i177 [[L]], -1 1693; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i64 -1, i64 -2 1694; CHECK-NEXT: [[G11:%.*]] = getelementptr i177, i177* [[A]], i64 [[TMP2]] 1695; CHECK-NEXT: [[L7:%.*]] = load i177, i177* [[G11]], align 4 1696; CHECK-NEXT: [[C171:%.*]] = icmp slt i177 [[L7]], 0 1697; CHECK-NEXT: [[C17:%.*]] = select i1 [[TMP1]], i1 [[C171]], i1 false 1698; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[C17]] to i64 1699; CHECK-NEXT: [[G62:%.*]] = getelementptr i177, i177* [[G11]], i64 [[TMP3]] 1700; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i177 [[L7]], -1 1701; CHECK-NEXT: [[B28:%.*]] = select i1 [[TMP4]], i177 0, i177 [[L7]] 1702; CHECK-NEXT: store i177 [[B28]], i177* [[G62]], align 4 1703; CHECK-NEXT: ret void 1704; 1705 %L = load i177, i177* %A 1706 %B5 = udiv i177 %L, -1 1707 %B4 = add i177 %B5, -1 1708 %B2 = add i177 %B4, -1 1709 %G11 = getelementptr i177, i177* %A, i177 %B2 1710 %L7 = load i177, i177* %G11 1711 %B6 = mul i177 %B5, %B2 1712 %B24 = ashr i177 %L7, %B6 1713 %B36 = and i177 %L7, %B4 1714 %C17 = icmp sgt i177 %B36, %B24 1715 %G62 = getelementptr i177, i177* %G11, i1 %C17 1716 %B28 = urem i177 %B24, %B6 1717 store i177 %B28, i177* %G62 1718 ret void 1719} 1720 1721; OSS Fuzz #26135 1722; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=26135 1723define void @ashr_out_of_range_1(i177* %A) { 1724; CHECK-LABEL: @ashr_out_of_range_1( 1725; CHECK-NEXT: [[L:%.*]] = load i177, i177* [[A:%.*]], align 4 1726; CHECK-NEXT: [[G11:%.*]] = getelementptr i177, i177* [[A]], i64 -1 1727; CHECK-NEXT: [[B24_LOBIT:%.*]] = ashr i177 [[L]], 175 1728; CHECK-NEXT: [[TMP1:%.*]] = trunc i177 [[B24_LOBIT]] to i64 1729; CHECK-NEXT: [[G62:%.*]] = getelementptr i177, i177* [[G11]], i64 [[TMP1]] 1730; CHECK-NEXT: store i177 0, i177* [[G62]], align 4 1731; CHECK-NEXT: ret void 1732; 1733 %L = load i177, i177* %A, align 4 1734 %B5 = udiv i177 %L, -1 1735 %B4 = add i177 %B5, -1 1736 %B = and i177 %B4, %L 1737 %B2 = add i177 %B, -1 1738 %G11 = getelementptr i177, i177* %A, i177 %B2 1739 %B6 = mul i177 %B5, %B2 1740 %B24 = ashr i177 %L, %B6 1741 %C17 = icmp sgt i177 %B, %B24 1742 %G62 = getelementptr i177, i177* %G11, i1 %C17 1743 %B28 = urem i177 %B24, %B6 1744 store i177 %B28, i177* %G62, align 4 1745 ret void 1746} 1747 1748; OSS Fuzz #38078 1749; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=38078 1750define void @ossfuzz_38078(i32 %arg, i32 %arg1, i32* %ptr, i1* %ptr2, i32* %ptr3, i1* %ptr4, i32* %ptr5, i32* %ptr6, i1* %ptr7) { 1751; CHECK-LABEL: @ossfuzz_38078( 1752; CHECK-NEXT: bb: 1753; CHECK-NEXT: [[G1:%.*]] = getelementptr i32, i32* [[PTR:%.*]], i64 -1 1754; CHECK-NEXT: [[I2:%.*]] = sub i32 0, [[ARG1:%.*]] 1755; CHECK-NEXT: [[I5:%.*]] = icmp eq i32 [[I2]], [[ARG:%.*]] 1756; CHECK-NEXT: call void @llvm.assume(i1 [[I5]]) 1757; CHECK-NEXT: store volatile i32 2147483647, i32* [[G1]], align 4 1758; CHECK-NEXT: br label [[BB:%.*]] 1759; CHECK: BB: 1760; CHECK-NEXT: unreachable 1761; 1762bb: 1763 %i = or i32 0, -1 1764 %B24 = urem i32 %i, -2147483648 1765 %B21 = or i32 %i, %i 1766 %i2 = add nsw i32 %arg, %arg1 1767 %B7 = or i32 %i, %i2 1768 %B8 = and i32 %i, %i2 1769 %B12 = sdiv i32 %i2, %B7 1770 %B3 = add i32 %i2, %B24 1771 %B5 = and i32 %i, %B3 1772 %B18 = and i32 %i, %B8 1773 %i3 = xor i32 %i2, %B3 1774 %C1 = icmp ne i32 %B8, %B5 1775 %i4 = lshr i32 %B5, %i3 1776 %B29 = shl nuw i32 %B8, %i3 1777 %B2 = lshr i32 %B12, %i2 1778 %B16 = add i32 %B2, %i3 1779 %B = sdiv i32 %B29, %B5 1780 %B15 = sub i32 %i2, %B5 1781 %B22 = or i32 %B21, %B29 1782 %B23 = mul i32 %B15, %B 1783 %C2 = icmp sge i1 %C1, false 1784 %C7 = icmp sle i32 %i3, %B16 1785 %B20 = xor i32 %B21, %B22 1786 %G1 = getelementptr i32, i32* %ptr, i32 %B22 1787 %B1 = sub i32 %B, 0 1788 %B26 = ashr i32 %B29, 0 1789 %B4 = add i32 0, %B5 1790 %B27 = srem i32 %B12, %B21 1791 %i5 = icmp eq i32 %B20, %B18 1792 %C11 = icmp ugt i32 %i4, %B4 1793 call void @llvm.assume(i1 %i5) 1794 store volatile i32 %B4, i32* %G1, align 4 1795 %B11 = or i32 0, %B23 1796 br label %BB 1797 1798BB: 1799 store i1 %C7, i1* %ptr2, align 1 1800 store i32 %B11, i32* %ptr3, align 4 1801 store i1 %C11, i1* %ptr4, align 1 1802 store i32 %B1, i32* %ptr5, align 4 1803 store i32 %B27, i32* %ptr6, align 4 1804 %C = icmp ne i32 %B26, 0 1805 %B17 = or i1 %C, %C2 1806 store i1 %B17, i1* %ptr7, align 1 1807 unreachable 1808} 1809declare void @llvm.assume(i1 noundef) 1810 1811define i8 @lshr_mask_demand(i8 %x) { 1812; CHECK-LABEL: @lshr_mask_demand( 1813; CHECK-NEXT: [[S:%.*]] = lshr i8 63, [[X:%.*]] 1814; CHECK-NEXT: [[R:%.*]] = and i8 [[S]], 32 1815; CHECK-NEXT: ret i8 [[R]] 1816; 1817 %s = lshr i8 63, %x ; 0b00111111 1818 %r = and i8 %s, 224 ; 0b11100000 1819 ret i8 %r 1820} 1821 1822define i8 @shl_mask_demand(i8 %x) { 1823; CHECK-LABEL: @shl_mask_demand( 1824; CHECK-NEXT: [[S:%.*]] = shl i8 12, [[X:%.*]] 1825; CHECK-NEXT: [[R:%.*]] = and i8 [[S]], 4 1826; CHECK-NEXT: ret i8 [[R]] 1827; 1828 %s = shl i8 12, %x ; 0b00001100 1829 %r = and i8 %s, 7 ; 0b00000111 1830 ret i8 %r 1831} 1832 1833define i64 @lshr_mul_negpow2(i64 %x) { 1834; CHECK-LABEL: @lshr_mul_negpow2( 1835; CHECK-NEXT: [[TMP1:%.*]] = sub i64 0, [[X:%.*]] 1836; CHECK-NEXT: [[A:%.*]] = and i64 [[TMP1]], 4294967295 1837; CHECK-NEXT: ret i64 [[A]] 1838; 1839 %a = mul i64 %x, -4294967296 1840 %b = lshr i64 %a, 32 1841 ret i64 %b 1842} 1843 1844define i64 @lshr_mul_negpow2_2(i64 %x) { 1845; CHECK-LABEL: @lshr_mul_negpow2_2( 1846; CHECK-NEXT: [[TMP1:%.*]] = sub i64 0, [[X:%.*]] 1847; CHECK-NEXT: [[A:%.*]] = and i64 [[TMP1]], 281474976710655 1848; CHECK-NEXT: ret i64 [[A]] 1849; 1850 %a = mul i64 %x, -65536 1851 %b = lshr i64 %a, 16 1852 ret i64 %b 1853} 1854 1855define <2 x i32> @lshr_mul_negpow2_3(<2 x i32> %x) { 1856; CHECK-LABEL: @lshr_mul_negpow2_3( 1857; CHECK-NEXT: [[TMP1:%.*]] = sub <2 x i32> zeroinitializer, [[X:%.*]] 1858; CHECK-NEXT: [[A:%.*]] = and <2 x i32> [[TMP1]], <i32 255, i32 255> 1859; CHECK-NEXT: ret <2 x i32> [[A]] 1860; 1861 %a = mul <2 x i32> %x, <i32 -16777216, i32 -16777216> 1862 %b = lshr <2 x i32> %a, <i32 24, i32 24> 1863 ret <2 x i32> %b 1864} 1865 1866define i32 @lshr_mul_negpow2_4(i32 %x) { 1867; CHECK-LABEL: @lshr_mul_negpow2_4( 1868; CHECK-NEXT: [[TMP1:%.*]] = sub i32 0, [[X:%.*]] 1869; CHECK-NEXT: [[A:%.*]] = and i32 [[TMP1]], 65535 1870; CHECK-NEXT: [[B:%.*]] = xor i32 [[A]], 1 1871; CHECK-NEXT: ret i32 [[B]] 1872; 1873 %a = mul i32 %x, -65536 1874 %b = xor i32 %a, 65536 1875 %c = lshr i32 %b, 16 1876 ret i32 %c 1877} 1878 1879define <2 x i32> @lshr_mul_negpow2_5(<2 x i32> %x) { 1880; CHECK-LABEL: @lshr_mul_negpow2_5( 1881; CHECK-NEXT: [[TMP1:%.*]] = sub <2 x i32> zeroinitializer, [[X:%.*]] 1882; CHECK-NEXT: [[A:%.*]] = and <2 x i32> [[TMP1]], <i32 65527, i32 65527> 1883; CHECK-NEXT: [[B:%.*]] = or <2 x i32> [[A]], <i32 8, i32 8> 1884; CHECK-NEXT: ret <2 x i32> [[B]] 1885; 1886 %a = mul <2 x i32> %x, <i32 -65536, i32 -65536> 1887 %b = or <2 x i32> %a, <i32 524288, i32 524288> 1888 %c = lshr <2 x i32> %b, <i32 16, i32 16> 1889 ret <2 x i32> %c 1890} 1891 1892define i64 @lshr_mul_negpow2_extra_use(i64 %x) { 1893; CHECK-LABEL: @lshr_mul_negpow2_extra_use( 1894; CHECK-NEXT: [[A:%.*]] = mul i64 [[X:%.*]], -4294967296 1895; CHECK-NEXT: [[B:%.*]] = lshr exact i64 [[A]], 32 1896; CHECK-NEXT: call void @use(i64 [[A]]) 1897; CHECK-NEXT: ret i64 [[B]] 1898; 1899 %a = mul i64 %x, -4294967296 1900 %b = lshr i64 %a, 32 1901 call void @use(i64 %a) 1902 ret i64 %b 1903} 1904