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Searched refs:setReg (Results 1 – 25 of 161) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMachineLoopUtils.cpp55 MO.setReg(R); in PeelSingleBlockLoop()
71 Use->setReg(R); in PeelSingleBlockLoop()
80 MO.setReg(Remaps[MO.getReg()]); in PeelSingleBlockLoop()
95 OrigPhi.getOperand(InitRegIdx).setReg(R); in PeelSingleBlockLoop()
102 MI.getOperand(LoopRegIdx).setReg(LoopReg); in PeelSingleBlockLoop()
H A DTailDuplicator.cpp233 UseMO->setReg( in tailDuplicateAndUpdate()
403 MO.setReg(NewReg); in duplicateInstruction()
434 MO.setReg(VI->second.Reg); in duplicateInstruction()
452 MO.setReg(NewReg); in duplicateInstruction()
523 MI.getOperand(Idx).setReg(SrcReg); in updateSuccessorsPHIs()
534 MI.getOperand(Idx).setReg(Reg); in updateSuccessorsPHIs()
H A DBreakFalseDeps.cpp147 MO.setReg(CurrMO.getReg()); in pickBestRegisterForUndef()
169 MO.setReg(MaxClearanceReg); in pickBestRegisterForUndef()
H A DModuloSchedule.cpp338 O.setReg(ToReg); in replaceRegUsesAfterLoop()
1020 MO.setReg(NewReg); in updateInstruction()
1169 UseOp.setReg(ReplaceReg); in rewriteScheduledInstr()
1175 UseOp.setReg(SplitReg); in rewriteScheduledInstr()
1318 MO.setReg(Reg); in rewrite()
1662 MI.getOperand(0).setReg(PhiReg); in moveStageBetweenBlocks()
1676 NewMI->getOperand(0).setReg(R); in moveStageBetweenBlocks()
1677 NewMI->getOperand(1).setReg(OrigR); in moveStageBetweenBlocks()
1690 MO.setReg(Remaps[MO.getReg()]); in moveStageBetweenBlocks()
1697 MO.setReg(R); in moveStageBetweenBlocks()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCVSXFMAMutate.cpp246 MI.getOperand(0).setReg(KilledProdReg); in processBlock()
247 MI.getOperand(1).setReg(KilledProdReg); in processBlock()
248 MI.getOperand(3).setReg(AddendSrcReg); in processBlock()
265 MI.getOperand(2).setReg(AddendSrcReg); in processBlock()
270 MI.getOperand(2).setReg(OtherProdReg); in processBlock()
H A DPPCVSXCopy.cpp114 SrcMO.setReg(NewVReg); in processBlock()
133 SrcMO.setReg(NewVReg); in processBlock()
H A DPPCMIPeephole.cpp602 MI.getOperand(1).setReg(DefReg1); in simplifyCode()
603 MI.getOperand(2).setReg(DefReg2); in simplifyCode()
636 DefMI->getOperand(0).setReg(MI.getOperand(0).getReg()); in simplifyCode()
703 MI.getOperand(1).setReg(ShiftOp1); in simplifyCode()
747 Use.getOperand(i).setReg(ConvReg1); in simplifyCode()
1537 CMPI2->getOperand(1).setReg(Op2); in eliminateRedundantCompare()
1538 CMPI2->getOperand(2).setReg(Op1); in eliminateRedundantCompare()
1552 CMPI2->getOperand(I).setReg(SrcReg); in eliminateRedundantCompare()
1564 BI2->getOperand(1).setReg(NewVReg); in eliminateRedundantCompare()
1568 BI2->getOperand(1).setReg(BI1->getOperand(1).getReg()); in eliminateRedundantCompare()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyDebugValueManager.cpp48 MO.setReg(Reg); in updateReg()
59 MO.setReg(NewReg); in clone()
H A DWebAssemblyFixBrTableDefaults.cpp66 MI.getOperand(0).setReg(ExtMI->getOperand(1).getReg()); in fixBrTableIndex()
78 MI.getOperand(0).setReg(Reg32); in fixBrTableIndex()
H A DWebAssemblyPeephole.cpp68 MO.setReg(NewReg); in maybeRewriteToDrop()
103 MO.setReg(NewReg); in maybeRewriteToFallthrough()
H A DWebAssemblyExplicitLocals.cpp283 MI.getOperand(2).setReg(NewReg); in runOnMachineFunction()
332 Def.setReg(NewReg); in runOnMachineFunction()
390 MO.setReg(NewReg); in runOnMachineFunction()
H A DWebAssemblyReplacePhysRegs.cpp100 MO.setReg(VReg); in runOnMachineFunction()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DAntiDepBreaker.h64 MI.getDebugOperand(0).setReg(NewReg); in UpdateDbgValue()
68 MI.getOperand(0).setReg(NewReg); in UpdateDbgValue()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZCopyPhysRegs.cpp87 MI->getOperand(1).setReg(Tmp); in visitMBB()
93 MI->getOperand(0).setReg(Tmp); in visitMBB()
H A DSystemZPostRewrite.cpp118 MBBI->getOperand(1).setReg(DestReg); in selectSELRMux()
125 MBBI->getOperand(2).setReg(DestReg); in selectSELRMux()
223 SrcMO.setReg(DstReg); in selectMI()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DMVETPAndVPTOptimisationsPass.cpp400 LoopPhi->getOperand(3).setReg(StartReg); in MergeLoopEnd()
401 LoopPhi->getOperand(1).setReg(DecReg); in MergeLoopEnd()
403 LoopPhi->getOperand(1).setReg(StartReg); in MergeLoopEnd()
404 LoopPhi->getOperand(3).setReg(DecReg); in MergeLoopEnd()
539 MI->getOperand(Idx + 2).setReg(LR); in ConvertTailPredLoop()
641 User.setReg(NewResult); in ReplaceRegisterUseWithVPNOT()
807 MO->setReg(LastVPNOTResult); in ReduceOldVCCRValueUses()
961 Instr.getOperand(PIdx + 1).setReg(LastVPTReg); in ReplaceConstByVPNOTs()
978 Instr.getOperand(PIdx + 1).setReg(NewVPR); in ReplaceConstByVPNOTs()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonAsmPrinter.cpp383 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
394 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
406 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
418 Rs.setReg(getHexagonRegisterPair(Rs.getReg(), RI)); in HexagonProcessInstruction()
544 MO.setReg(High); in HexagonProcessInstruction()
556 MO.setReg(High); in HexagonProcessInstruction()
570 MO.setReg(High); in HexagonProcessInstruction()
603 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DDelaySlotFiller.cpp399 AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreADD()
438 OrMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreOR()
472 RestoreMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreSETHIi()
473 RestoreMI->getOperand(1).setReg(SP::G0); in combineRestoreSETHIi()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp1401 MO.setReg(RegPair.first); in processInstruction()
1411 MO.setReg(RegPair.first); in processInstruction()
1422 MO.setReg(RegPair.first); in processInstruction()
1434 MO.setReg(RegPair.first); in processInstruction()
1748 Rss.setReg(matchRegister(Reg1)); in processInstruction()
1774 Rs.setReg(matchRegister(RegPair)); in processInstruction()
1779 Rs.setReg(matchRegister(RegPair)); in processInstruction()
1791 Rs.setReg(matchRegister(RegPair)); in processInstruction()
1796 Rs.setReg(matchRegister(RegPair)); in processInstruction()
1808 Rt.setReg(matchRegister(RegPair)); in processInstruction()
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DLocalizer.cpp135 LocalizedMI->getOperand(0).setReg(NewReg); in localizeInterBlock()
143 MOUse.setReg(NewVRegIt->second); in localizeInterBlock()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrBuilder.h137 MI->getOperand(Operand + 2).setReg(0); in setDirectAddressInInstr()
139 MI->getOperand(Operand + 4).setReg(0); in setDirectAddressInInstr()
H A DX86FastPreTileConfig.cpp251 MO.setReg(StrideReg); in reload()
262 MO.setReg(TileReg); in reload()
419 MO.setReg(StrideReg); in convertPHI()
482 InMO->setReg(DefTileReg); in canonicalizePHIs()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsOptimizePICCall.cpp158 I->getOperand(0).setReg(DstReg); in setCallTargetReg()
248 getCallTargetRegOpnd(*I)->setReg(getReg(Entry)); in visitNode()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64PreLegalizerCombiner.cpp106 MI.getOperand(2).setReg(WideReg); in applyICmpRedundantTrunc()
107 MI.getOperand(3).setReg(WideZero.getReg(0)); in applyICmpRedundantTrunc()
217 MI.getOperand(0).setReg(NewGVDst); in applyFoldGlobalOffset()
/llvm-project-15.0.7/llvm/lib/Target/SPIRV/
H A DSPIRVPreLegalizer.cpp215 Def->getOperand(0).setReg(NewReg); in insertAssignInstr()
332 AssignTypeInst.getOperand(1).setReg(NewReg); in processInstr()
333 MI.getOperand(0).setReg(NewReg); in processInstr()
342 Op.setReg(IdOpInfo.first); in processInstr()

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