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Searched refs:setOpcode (Results 1 – 25 of 86) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp729 Result.setOpcode(Hexagon::SA1_addi); in deriveSubInst()
735 Result.setOpcode(Hexagon::SA1_addrx); in deriveSubInst()
746 Result.setOpcode(Hexagon::SA1_zxtb); in deriveSubInst()
751 Result.setOpcode(Hexagon::SA1_and1); in deriveSubInst()
950 Result.setOpcode(Hexagon::SA1_sxtb); in deriveSubInst()
955 Result.setOpcode(Hexagon::SA1_sxth); in deriveSubInst()
960 Result.setOpcode(Hexagon::SA1_tfr); in deriveSubInst()
975 Result.setOpcode(Hexagon::SA1_clrf); in deriveSubInst()
980 Result.setOpcode(Hexagon::SA1_clrt); in deriveSubInst()
998 Result.setOpcode(Hexagon::SA1_zxtb); in deriveSubInst()
[all …]
H A DHexagonMCCompound.cpp214 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
227 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
241 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
254 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
267 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
285 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
303 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
314 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
325 CompoundInsn->setOpcode(compoundOpcode); in getCompoundInsn()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonAsmPrinter.cpp249 T.setOpcode(Inst.getOpcode()); in ScaleVectorOffset()
278 Inst.setOpcode(Hexagon::A2_addi); in HexagonProcessInstruction()
292 Inst.setOpcode(Hexagon::A2_paddif); in HexagonProcessInstruction()
299 Inst.setOpcode(Hexagon::A2_paddit); in HexagonProcessInstruction()
320 Inst.setOpcode(Hexagon::A2_andir); in HexagonProcessInstruction()
367 MappedInst.setOpcode(Hexagon::C2_or); in HexagonProcessInstruction()
423 Inst.setOpcode(Hexagon::J2_call); in HexagonProcessInstruction()
498 TmpInst.setOpcode(Hexagon::A2_tfr); in HexagonProcessInstruction()
612 TmpInst.setOpcode(Hexagon::V6_vxor); in HexagonProcessInstruction()
750 MCB.setOpcode(Hexagon::BUNDLE); in emitInstruction()
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/llvm-project-15.0.7/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp262 Inst.setOpcode(XCore::ADD_3r); in Decode2OpInstructionFail()
265 Inst.setOpcode(XCore::SUB_3r); in Decode2OpInstructionFail()
268 Inst.setOpcode(XCore::SHL_3r); in Decode2OpInstructionFail()
271 Inst.setOpcode(XCore::SHR_3r); in Decode2OpInstructionFail()
274 Inst.setOpcode(XCore::EQ_3r); in Decode2OpInstructionFail()
277 Inst.setOpcode(XCore::AND_3r); in Decode2OpInstructionFail()
280 Inst.setOpcode(XCore::OR_3r); in Decode2OpInstructionFail()
283 Inst.setOpcode(XCore::LDW_3r); in Decode2OpInstructionFail()
289 Inst.setOpcode(XCore::LD8U_3r); in Decode2OpInstructionFail()
310 Inst.setOpcode(XCore::LSS_3r); in Decode2OpInstructionFail()
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/llvm-project-15.0.7/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp159 MCB.setOpcode(Hexagon::BUNDLE); in HexagonAsmParser()
528 NewInst.setOpcode(MCI.getOpcode()); in canonicalizeImmediates()
1227 TmpInst.setOpcode(opCode); in makeCombineInst()
1334 Inst.setOpcode(Hexagon::A2_addi); in processInstruction()
1368 Inst.setOpcode(Hexagon::C2_cmpgti); in processInstruction()
1403 Inst.setOpcode(Hexagon::A2_combinew); in processInstruction()
1436 Inst.setOpcode(Hexagon::V6_vcombine); in processInstruction()
1678 Inst.setOpcode(Hexagon::M2_mpyi); in processInstruction()
1714 TmpInst.setOpcode(Hexagon::A2_tfr); in processInstruction()
1788 Inst.setOpcode(Hexagon::A2_addsph); in processInstruction()
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/llvm-project-15.0.7/llvm/lib/Target/SPIRV/
H A DSPIRVAsmPrinter.cpp125 FunctionEndInst.setOpcode(SPIRV::OpFunctionEnd); in outputOpFunctionEnd()
139 LabelInst.setOpcode(SPIRV::OpLabel); in emitOpLabel()
251 Inst.setOpcode(SPIRV::OpSourceExtension); in outputDebugSourceAndStrings()
257 Inst.setOpcode(SPIRV::OpSource); in outputDebugSourceAndStrings()
269 Inst.setOpcode(SPIRV::OpExtInstImport); in outputOpExtInstImports()
279 Inst.setOpcode(SPIRV::OpMemoryModel); in outputOpMemoryModel()
381 Inst.setOpcode(SPIRV::OpExecutionMode); in outputExecutionModeFromMDNode()
393 Inst.setOpcode(SPIRV::OpExecutionMode); in outputExecutionMode()
415 Inst.setOpcode(SPIRV::OpExecutionMode); in outputExecutionMode()
451 Inst.setOpcode(SPIRV::OpDecorate); in outputAnnotations()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYAsmBackend.cpp301 Res.setOpcode(CSKY::LRW32); in relaxInstruction()
306 Res.setOpcode(CSKY::BR32); in relaxInstruction()
310 Res.setOpcode(CSKY::JSRI32); in relaxInstruction()
314 Res.setOpcode(CSKY::JMPI32); in relaxInstruction()
319 Res.setOpcode(Inst.getOpcode() == CSKY::JBT32 ? CSKY::JBT_E : CSKY::JBF_E); in relaxInstruction()
325 Res.setOpcode(CSKY::JBR32); in relaxInstruction()
338 Res.setOpcode(opcode); in relaxInstruction()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/AsmParser/
H A DPPCAsmParser.cpp754 TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ? in ProcessInstruction()
766 TmpInst.setOpcode(PPC::DCBT); in ProcessInstruction()
776 TmpInst.setOpcode(PPC::DCBTST); in ProcessInstruction()
799 TmpInst.setOpcode(PPC::DCBF); in ProcessInstruction()
808 TmpInst.setOpcode(PPC::LA); in ProcessInstruction()
817 TmpInst.setOpcode(PPC::ADDI); in ProcessInstruction()
826 TmpInst.setOpcode(PPC::ADDIS); in ProcessInstruction()
835 TmpInst.setOpcode(PPC::ADDIC); in ProcessInstruction()
844 TmpInst.setOpcode(PPC::ADDIC_rec); in ProcessInstruction()
1042 TmpInst.setOpcode(PPC::ADDPCIS); in ProcessInstruction()
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/llvm-project-15.0.7/bolt/lib/Target/X86/
H A DX86MCPlusBuilder.cpp1620 Inst.setOpcode(NewOpcode); in replaceMemOperandWithImm()
1657 Inst.setOpcode(NewOpcode); in replaceMemOperandWithReg()
1718 Inst.setOpcode(NewOpcode); in convertJmpToTailCall()
1739 Inst.setOpcode(NewOpcode); in convertTailCallToJmp()
1761 Inst.setOpcode(NewOpcode); in convertTailCallToCall()
1773 Inst.setOpcode(NewOpcode); in convertCallToIndirectCall()
1865 Inst.setOpcode(NewOpcode); in shortenInstruction()
1924 Inst.setOpcode(NewOpcode); in convertMoveToConditionalMove()
2426 Inst.setOpcode(NewOpcode); in createSaveToStack()
3142 Inst.setOpcode(Opcode); in createAddRegImm()
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/llvm-project-15.0.7/llvm/lib/Target/AVR/Disassembler/
H A DAVRDisassembler.cpp279 Inst.setOpcode(AVR::LDDRdPtrQ); in decodeLoadStore()
284 Inst.setOpcode(AVR::STDPtrQRr); in decodeLoadStore()
332 Inst.setOpcode(AVR::STPtrRr); in decodeLoadStore()
337 Inst.setOpcode(AVR::STPtrPiRr); in decodeLoadStore()
340 Inst.setOpcode(AVR::STPtrPdRr); in decodeLoadStore()
343 Inst.setOpcode(AVR::LDRdPtr); in decodeLoadStore()
348 Inst.setOpcode(AVR::LDRdPtrPi); in decodeLoadStore()
351 Inst.setOpcode(AVR::LDRdPtrPd); in decodeLoadStore()
/llvm-project-15.0.7/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp619 MI.setOpcode(Mips::BOVC); in DecodeAddiGroupBranch()
622 MI.setOpcode(Mips::BEQC); in DecodeAddiGroupBranch()
692 MI.setOpcode(Mips::BNVC); in DecodeDaddiGroupBranch()
695 MI.setOpcode(Mips::BNEC); in DecodeDaddiGroupBranch()
846 MI.setOpcode(Mips::BLEZC); in DecodeBlezlGroupBranch()
848 MI.setOpcode(Mips::BGEZC); in DecodeBlezlGroupBranch()
851 MI.setOpcode(Mips::BGEC); in DecodeBlezlGroupBranch()
894 MI.setOpcode(Mips::BLTC); in DecodeBgtzlGroupBranch()
932 MI.setOpcode(Mips::BGTZ); in DecodeBgtzGroupBranch()
1028 MI.setOpcode(Mips::DEXT); in DecodeDEXT()
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/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEAsmPrinter.cpp86 SICInst.setOpcode(VE::SIC); in emitSIC()
94 BSICInst.setOpcode(VE::BSICrii); in emitBSIC()
106 LEAInst.setOpcode(VE::LEAzii); in emitLEAzzi()
118 LEASLInst.setOpcode(VE::LEASLzii); in emitLEASLzzi()
130 LEAInst.setOpcode(VE::LEAzii); in emitLEAzii()
143 LEASLInst.setOpcode(VE::LEASLrri); in emitLEASLrri()
155 Inst.setOpcode(Opcode); in emitBinary()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64AsmPrinter.cpp1113 MI.setOpcode(Opcode); in LowerFAULTING_OP()
1143 MOVI.setOpcode(AArch64::MOVID); in emitFMov0()
1308 TmpInst.setOpcode(AArch64::BR); in emitInstruction()
1317 TmpInst.setOpcode(AArch64::B); in emitInstruction()
1337 TmpInstSB.setOpcode(AArch64::SB); in emitInstruction()
1359 Adrp.setOpcode(AArch64::ADRP); in emitInstruction()
1366 Ldr.setOpcode(AArch64::LDRWui); in emitInstruction()
1369 Ldr.setOpcode(AArch64::LDRXui); in emitInstruction()
1379 Add.setOpcode(AArch64::ADDWri); in emitInstruction()
1383 Add.setOpcode(AArch64::ADDXri); in emitInstruction()
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H A DAArch64MCInstLower.cpp303 OutMI.setOpcode(MI->getOpcode()); in Lower()
314 OutMI.setOpcode(AArch64::RET); in Lower()
319 OutMI.setOpcode(AArch64::RET); in Lower()
/llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp2590 Inst.setOpcode(ARM::CPS3p); in DecodeCPSInstruction()
2595 Inst.setOpcode(ARM::CPS2p); in DecodeCPSInstruction()
2600 Inst.setOpcode(ARM::CPS1p); in DecodeCPSInstruction()
2605 Inst.setOpcode(ARM::CPS1p); in DecodeCPSInstruction()
2631 Inst.setOpcode(ARM::t2CPS3p); in DecodeT2CPSInstruction()
2636 Inst.setOpcode(ARM::t2CPS2p); in DecodeT2CPSInstruction()
2641 Inst.setOpcode(ARM::t2CPS1p); in DecodeT2CPSInstruction()
2649 Inst.setOpcode(ARM::t2HINT); in DecodeT2CPSInstruction()
2673 Inst.setOpcode(Opcode); in DecodeT2HintSpaceInstruction()
2808 Inst.setOpcode(ARM::SETPAN); in DecodeSETPANInstruction()
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/llvm-project-15.0.7/bolt/lib/Target/AArch64/
H A DAArch64MCPlusBuilder.cpp847 Inst.setOpcode(AArch64::B); in createTailCall()
862 Inst.setOpcode(AArch64::BRK); in createTrap()
893 Inst.setOpcode(AArch64::HINT); in createNoop()
963 Inst.setOpcode(AArch64::MOVZXi); in createLongJmp()
972 Inst.setOpcode(AArch64::MOVKXi); in createLongJmp()
982 Inst.setOpcode(AArch64::MOVKXi); in createLongJmp()
992 Inst.setOpcode(AArch64::MOVKXi); in createLongJmp()
1002 Inst.setOpcode(AArch64::BR); in createLongJmp()
1022 Inst.setOpcode(AArch64::BR); in createShortJmp()
1094 Inst.setOpcode(AArch64::B); in createUncondBranch()
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/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVMCInstLower.cpp139 OutMI.setOpcode(RVV->BaseInstr); in lowerRISCVVMachineInstrToMCInst()
218 OutMI.setOpcode(MI->getOpcode()); in lowerRISCVMachineInstrToMCInst()
241 OutMI.setOpcode(RISCV::CSRRS); in lowerRISCVMachineInstrToMCInst()
247 OutMI.setOpcode(RISCV::CSRRS); in lowerRISCVMachineInstrToMCInst()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp182 MI.setOpcode(Hexagon::BUNDLE); in getInstruction()
214 MI.setOpcode(Hexagon::S6_allocframe_to_raw); in remapInstruction()
222 MI.setOpcode(L6_deallocframe_map_to_raw); in remapInstruction()
230 MI.setOpcode(L6_return_map_to_raw); in remapInstruction()
238 MI.setOpcode(L4_return_map_to_raw_t); in remapInstruction()
246 MI.setOpcode(L4_return_map_to_raw_f); in remapInstruction()
254 MI.setOpcode(L4_return_map_to_raw_tnew_pt); in remapInstruction()
262 MI.setOpcode(L4_return_map_to_raw_fnew_pt); in remapInstruction()
270 MI.setOpcode(L4_return_map_to_raw_tnew_pnt); in remapInstruction()
278 MI.setOpcode(L4_return_map_to_raw_fnew_pnt); in remapInstruction()
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/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsAsmPrinter.cpp119 TmpInst0.setOpcode(Mips::JALR64); in emitPseudoIndirectBranch()
124 TmpInst0.setOpcode(Mips::JRC16_MMR6); in emitPseudoIndirectBranch()
126 TmpInst0.setOpcode(Mips::JALR); in emitPseudoIndirectBranch()
131 TmpInst0.setOpcode(Mips::JR_MM); in emitPseudoIndirectBranch()
134 TmpInst0.setOpcode(Mips::JR); in emitPseudoIndirectBranch()
859 I.setOpcode(Mips::JAL); in EmitJal()
868 I.setOpcode(Opcode); in EmitInstrReg()
887 I.setOpcode(Opcode); in EmitInstrRegReg()
897 I.setOpcode(Opcode); in EmitInstrRegRegReg()
H A DMipsMCInstLower.cpp216 OutMI.setOpcode(Mips::LUi); in lowerLongBranchLUi()
254 OutMI.setOpcode(Opcode); in lowerLongBranchADDiu()
319 OutMI.setOpcode(MI->getOpcode()); in Lower()
/llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp300 ITInst.setOpcode(ARM::t2IT); in flushPendingInstructions()
8717 TmpInst.setOpcode(Opcode); in processInstruction()
8755 TmpInst.setOpcode(Opcode); in processInstruction()
8773 TmpInst.setOpcode(ARM::ADR); in processInstruction()
10022 TmpInst.setOpcode(NewOpc); in processInstruction()
10057 TmpInst.setOpcode(newOpc); in processInstruction()
10110 TmpInst.setOpcode(newOpc); in processInstruction()
10172 TmpInst.setOpcode(Opc); in processInstruction()
10407 Inst.setOpcode(ARM::t2B); in processInstruction()
10414 Inst.setOpcode(ARM::tB); in processInstruction()
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/llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp178 TmpInst.setOpcode(Opcode); in emitR()
187 TmpInst.setOpcode(Opcode); in emitRX()
207 TmpInst.setOpcode(Opcode); in emitII()
218 TmpInst.setOpcode(Opcode); in emitRRX()
236 TmpInst.setOpcode(Opcode); in emitRRRX()
256 TmpInst.setOpcode(Opcode); in emitRRIII()
1178 TmpInst.setOpcode(Mips::LUi); in emitDirectiveCpLoad()
1190 TmpInst.setOpcode(Mips::ADDiu); in emitDirectiveCpLoad()
1203 TmpInst.setOpcode(Mips::ADDu); in emitDirectiveCpLoad()
1306 Inst.setOpcode(Mips::OR); in emitDirectiveCpreturn()
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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86MCInstLower.cpp343 Inst.setOpcode(Opcode); in SimplifyShortImmForm()
371 Inst.setOpcode(NewOpcode); in SimplifyMOVSX()
422 Inst.setOpcode(Opcode); in SimplifyShortMoveForm()
532 OutMI.setOpcode(NewOpc); in Lower()
573 OutMI.setOpcode(NewOpc); in Lower()
587 OutMI.setOpcode(NewOpc); in Lower()
689 OutMI.setOpcode(NewOpc); in Lower()
1311 MI.setOpcode(Opcode); in LowerFAULTING_OP()
1382 MCI.setOpcode(Opcode); in LowerPATCHABLE_OP()
1758 Ret.setOpcode(OpCode); in LowerPATCHABLE_RET()
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/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrInfo.cpp37 NopInst.setOpcode(ARM::HINT); in getNop()
42 NopInst.setOpcode(ARM::MOVr); in getNop()
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kMCInstLower.cpp147 OutMI.setOpcode(Opcode); in Lower()
168 OutMI.setOpcode(Opcode); in Lower()

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