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/llvm-project-15.0.7/llvm/test/CodeGen/MIR/AMDGPU/
H A Dtarget-index-operands.mir39 …gpr2 = S_ADD_U32 $sgpr2, target-index(amdgpu-constdata-start), implicit-def $scc, implicit-def $scc
40 …gpr2 = S_ADD_U32 $sgpr2, target-index(amdgpu-constdata-start), implicit-def $scc, implicit-def $scc
41 … $sgpr3 = S_ADDC_U32 $sgpr3, 0, implicit-def $scc, implicit $scc, implicit-def $scc, implicit $scc
47 $sgpr3 = S_ADDC_U32 $sgpr4, 0, implicit-def dead $scc, implicit $scc
48 $sgpr4 = S_ADD_U32 $sgpr2, $sgpr6, implicit-def $scc
49 $sgpr5 = S_ADDC_U32 $sgpr3, $sgpr7, implicit-def dead $scc, implicit $scc
69 … = S_ADD_U32 $sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def $scc, implicit-def $scc
70 … = S_ADD_U32 $sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def $scc, implicit-def $scc
71 … $sgpr3 = S_ADDC_U32 $sgpr3, 0, implicit-def $scc, implicit $scc, implicit-def $scc, implicit $scc
77 $sgpr3 = S_ADDC_U32 $sgpr4, 0, implicit-def dead $scc, implicit $scc
[all …]
H A Dexpected-target-index-name.mir32 $sgpr2 = S_ADD_U32 $sgpr2, target-index(0), implicit-def $scc, implicit-def $scc
33 … $sgpr3 = S_ADDC_U32 $sgpr3, 0, implicit-def $scc, implicit $scc, implicit-def $scc, implicit $scc
34 $sgpr4_sgpr5 = S_LSHR_B64 $sgpr2_sgpr3, 32, implicit-def dead $scc
36 $sgpr7 = S_ASHR_I32 $sgpr6, 31, implicit-def dead $scc
37 $sgpr6_sgpr7 = S_LSHL_B64 $sgpr6_sgpr7, 2, implicit-def dead $scc
38 $sgpr2 = S_ADD_U32 $sgpr2, @float_gv, implicit-def $scc
39 $sgpr3 = S_ADDC_U32 $sgpr4, 0, implicit-def dead $scc, implicit $scc
40 $sgpr4 = S_ADD_U32 $sgpr2, $sgpr6, implicit-def $scc
41 $sgpr5 = S_ADDC_U32 $sgpr3, $sgpr7, implicit-def dead $scc, implicit $scc
H A Dinvalid-target-index-operand.mir32 $sgpr2 = S_ADD_U32 $sgpr2, target-index(constdata-start), implicit-def $scc, implicit-def $scc
33 … $sgpr3 = S_ADDC_U32 $sgpr3, 0, implicit-def $scc, implicit $scc, implicit-def $scc, implicit $scc
34 $sgpr4_sgpr5 = S_LSHR_B64 $sgpr2_sgpr3, 32, implicit-def dead $scc
36 $sgpr7 = S_ASHR_I32 $sgpr6, 31, implicit-def dead $scc
37 $sgpr6_sgpr7 = S_LSHL_B64 $sgpr6_sgpr7, 2, implicit-def dead $scc
38 $sgpr2 = S_ADD_U32 $sgpr2, @float_gv, implicit-def $scc
39 $sgpr3 = S_ADDC_U32 $sgpr4, 0, implicit-def dead $scc, implicit $scc
40 $sgpr4 = S_ADD_U32 $sgpr2, $sgpr6, implicit-def $scc
41 $sgpr5 = S_ADDC_U32 $sgpr3, $sgpr7, implicit-def dead $scc, implicit $scc
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Doptimize-compare.mir30 S_CBRANCH_SCC0 %bb.2, implicit $scc
69 S_CBRANCH_SCC0 %bb.2, implicit $scc
106 S_CBRANCH_SCC0 %bb.2, implicit $scc
144 S_CBRANCH_SCC0 %bb.2, implicit $scc
190 S_CBRANCH_SCC0 %bb.2, implicit $scc
228 S_CBRANCH_SCC0 %bb.2, implicit $scc
265 S_CBRANCH_SCC0 %bb.2, implicit $scc
301 S_CBRANCH_SCC0 %bb.2, implicit $scc
341 S_CBRANCH_SCC0 %bb.2, implicit $scc
419 S_NOP 0, implicit killed $scc
[all …]
H A Doptimize-exec-mask-pre-ra-alloc-failure.mir29 S_BITCMP1_B32 %5, 0, implicit-def $scc
33 S_CBRANCH_SCC1 %bb.2, implicit undef $scc
42 S_BITCMP1_B32 %11, 0, implicit-def $scc
44 S_BITCMP1_B32 %13, 0, implicit-def $scc
46 S_BITCMP1_B32 %13, 8, implicit-def $scc
50 S_BITCMP1_B32 %17, 0, implicit-def $scc
52 S_BITCMP1_B32 %17, 8, implicit-def $scc
57 S_BITCMP1_B32 %22, 0, implicit-def $scc
127 S_CBRANCH_SCC1 %bb.18, implicit undef $scc
132 S_BITCMP1_B32 %70, 0, implicit-def $scc
[all …]
H A Dspill-before-exec.mir51 $exec = S_XOR_B64_term $exec, %0, implicit-def $scc
59 $exec = S_XOR_B64_term $exec, %0, implicit-def $scc
67 $exec = S_XOR_B64_term $exec, %0, implicit-def $scc
71 S_CMP_EQ_U64 %1.sub0_sub1, %2.sub2_sub3, implicit-def $scc
72 S_CMP_EQ_U64 %3.sub0_sub1, %4.sub2_sub3, implicit-def $scc
73 S_CMP_EQ_U64 %5.sub0_sub1, %6.sub2_sub3, implicit-def $scc
74 S_CMP_EQ_U64 %7.sub0_sub1, %8.sub2_sub3, implicit-def $scc
75 S_CMP_EQ_U64 %9.sub0_sub1, %10.sub2_sub3, implicit-def $scc
76 S_CMP_EQ_U64 %11.sub0_sub1, %12.sub2_sub3, implicit-def $scc
77 S_CMP_EQ_U64 %13.sub0_sub1, %14.sub2_sub3, implicit-def $scc
[all …]
H A Dcollapse-endcf.mir33 ; GCN-NEXT: $exec = S_OR_B64 $exec, [[COPY]], implicit-def $scc
92 ; GCN-NEXT: $exec = S_OR_B64 $exec, [[COPY]], implicit-def $scc
149 ; GCN-NEXT: $exec = S_OR_B64 $exec, [[COPY]], implicit-def $scc
211 ; GCN-NEXT: $exec = S_OR_B64 $exec, [[COPY]], implicit-def $scc
276 ; GCN-NEXT: $exec = S_OR_B64 $exec, [[COPY]], implicit-def $scc
334 ; GCN-NEXT: $exec = S_OR_B64 $exec, [[COPY1]], implicit-def $scc
338 ; GCN-NEXT: $exec = S_OR_B64 $exec, [[COPY]], implicit-def $scc
398 ; GCN-NEXT: $exec = S_OR_B64 $exec, [[COPY]], implicit-def $scc
456 ; GCN-NEXT: $exec = S_OR_B64 $exec, [[COPY]], implicit-def $scc
632 ; GCN-NEXT: $exec = S_OR_B64 $exec, [[COPY]], implicit-def $scc
[all …]
H A Dendpgm-dce.mir19 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
22 %4 = S_ADD_U32 %3, 1, implicit-def $scc
43 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
46 %4 = S_ADD_U32 %3, 1, implicit-def $scc
67 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
70 %4 = S_ADD_U32 %3, 1, implicit-def $scc
88 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
102 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
117 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
177 %3 = S_ADD_U32 %2, 1, implicit-def $scc
[all …]
H A Dcall-waw-waitcnt.mir31 ; GCN-NEXT: $flat_scr_lo = S_ADD_U32 killed $sgpr4, $sgpr33, implicit-def $scc
32 ; GCN-NEXT: $flat_scr_hi = S_ADDC_U32 killed $sgpr5, 0, implicit-def $scc, implicit killed $scc
33 …XT: BUNDLE implicit-def $sgpr4_sgpr5, implicit-def $sgpr4, implicit-def $sgpr5, implicit-def $scc {
35 …T: $sgpr4 = S_ADD_U32 internal $sgpr4, target-flags(amdgpu-rel32-lo) @func + 4, implicit-def $scc
36 …internal $sgpr5, target-flags(amdgpu-rel32-hi) @func + 4, implicit-def $scc, implicit internal $scc
44 $flat_scr_lo = S_ADD_U32 killed $sgpr4, $sgpr33, implicit-def $scc
45 $flat_scr_hi = S_ADDC_U32 killed $sgpr5, 0, implicit-def $scc, implicit killed $scc
46 BUNDLE implicit-def $sgpr4_sgpr5, implicit-def $sgpr4, implicit-def $sgpr5, implicit-def $scc {
48 $sgpr4 = S_ADD_U32 internal $sgpr4, target-flags(amdgpu-rel32-lo) @func + 4, implicit-def $scc
49 …internal $sgpr5, target-flags(amdgpu-rel32-hi) @func + 4, implicit-def $scc, implicit internal $scc
H A Doptimize-if-exec-masking.mir159 $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
196 $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
233 $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
274 $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
312 $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
354 $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
395 $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
434 $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
471 $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
508 $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
[all …]
H A Dinsert-skip-from-vcc.mir37 $vcc = S_AND_B64 $exec, -1, implicit-def dead $scc
54 $vcc = S_AND_B64 $exec, -1, implicit-def dead $scc
60 # GCN: $vcc = S_AND_B64 $exec, -1, implicit-def $scc
71 $vcc = S_AND_B64 $exec, -1, implicit-def $scc
78 # GCN: $vcc = S_AND_B64 $exec, -1, implicit-def $scc
133 # GCN: $vcc = S_AND_B64 $exec, -1, implicit-def $scc
182 $vcc = S_AND_B64 $exec, $exec, implicit-def dead $scc
200 $vcc = S_AND_B64 $exec, $exec, implicit-def dead $scc
309 # GCN-NEXT: S_ENDPGM 0, implicit $scc
319 $vcc = S_AND_B64 $exec, -1, implicit-def $scc
[all …]
H A Doptimize-negated-cond-exec-masking.mir5 # GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def dead $scc
14 $vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
27 # GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0, implicit-def dead $scc
36 $vcc = S_AND_B64 killed %2, $exec, implicit-def dead $scc
52 # GCN-NEXT: $vcc = S_AND_B64 $exec, $vcc, implicit-def dead $scc
62 $vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
104 # GCN-NEXT: $vcc = S_AND_B64 %2, $exec, implicit-def dead $scc
114 $vcc = S_AND_B64 killed %2, $exec, implicit-def dead $scc
154 $vcc = S_AND_B64 killed %2, $exec, implicit-def dead $scc
202 $vcc = S_AND_B64 killed %2, $exec, implicit-def dead $scc
[all …]
H A Dregcoal-subrange-join-seg.mir7 # GCN: S_CBRANCH_SCC1 %bb.6, implicit undef $scc
84 S_CBRANCH_SCC1 %bb.6, implicit undef $scc
88 S_CBRANCH_SCC1 %bb.4, implicit undef $scc
92 S_CBRANCH_SCC1 %bb.4, implicit undef $scc
100 S_CBRANCH_SCC1 %bb.6, implicit undef $scc
106 S_CBRANCH_SCC1 %bb.14, implicit undef $scc
110 S_CBRANCH_SCC1 %bb.9, implicit undef $scc
118 S_CBRANCH_SCC1 %bb.13, implicit undef $scc
122 S_CBRANCH_SCC1 %bb.12, implicit undef $scc
132 S_CBRANCH_SCC1 %bb.26, implicit undef $scc
[all …]
H A Dsink-after-control-flow.mir39 ; GFX10-NEXT: $exec_lo = S_OR_B32 $exec_lo, [[S_XOR_B32_1]], implicit-def $scc
66 ; GFX10-NEXT: $exec_lo = S_OR_B32 $exec_lo, [[DEF2]], implicit-def $scc
79 %21:sreg_32 = S_XOR_B32 %20, -1, implicit-def $scc
80 %22:sreg_32 = S_AND_B32 %21, $exec_lo, implicit-def $scc
81 %23:sreg_32 = S_XOR_B32 $exec_lo, %22, implicit-def $scc
94 $exec_lo = S_OR_B32 $exec_lo, %23, implicit-def $scc
97 %26:sreg_32 = S_XOR_B32 %25, -1, implicit-def $scc
98 %27:sreg_32 = S_AND_B32 %26, $exec_lo, implicit-def $scc
99 %28:sreg_32 = S_XOR_B32 $exec_lo, %27, implicit-def $scc
112 $exec_lo = S_OR_B32 $exec_lo, %28, implicit-def $scc
[all …]
H A Dskip-branch-taildup-ret.mir34 ; CHECK-NEXT: $exec = S_XOR_B64 $exec, renamable $sgpr2_sgpr3, implicit-def $scc
53 ; CHECK-NEXT: $exec = S_XOR_B64 $exec, renamable $sgpr2_sgpr3, implicit-def $scc
90 $exec = S_XOR_B64 $exec, renamable $sgpr2_sgpr3, implicit-def $scc
97 $exec = S_OR_B64 $exec, killed renamable $sgpr2_sgpr3, implicit-def $scc
109 $exec = S_XOR_B64 $exec, renamable $sgpr2_sgpr3, implicit-def $scc
119 $exec = S_OR_B64 $exec, killed renamable $sgpr2_sgpr3, implicit-def $scc
145 ; CHECK-NEXT: $exec = S_XOR_B64 $exec, renamable $sgpr6_sgpr7, implicit-def $scc
189 $exec = S_XOR_B64 $exec, renamable $sgpr6_sgpr7, implicit-def $scc
196 $exec = S_OR_B64 $exec, killed renamable $sgpr6_sgpr7, implicit-def $scc
206 $exec = S_XOR_B64 $exec, renamable $sgpr6_sgpr7, implicit-def $scc
[all …]
H A Dregcoalescing-remove-partial-redundancy-assert.mir20 S_CMP_EQ_U32 killed %28, 0, implicit-def $scc
21 S_CBRANCH_SCC0 %bb.2, implicit killed $scc
30 S_CBRANCH_SCC0 %bb.4, implicit undef $scc
46 S_CBRANCH_SCC1 %bb.8, implicit undef $scc
91 S_CBRANCH_SCC1 %bb.18, implicit undef $scc
95 S_CBRANCH_SCC1 %bb.12, implicit undef $scc
103 S_CBRANCH_SCC1 %bb.18, implicit undef $scc
109 S_CBRANCH_SCC1 %bb.17, implicit undef $scc
113 S_CBRANCH_SCC1 %bb.16, implicit undef $scc
123 S_CBRANCH_SCC1 %bb.26, implicit undef $scc
[all …]
H A Dchange-scc-to-vcc.mir4 # Test that the Fix SGPR Copy pass changes scc definitions to vcc if the
5 # instruction that uses the scc is changed to use vcc.
35 %8:sreg_32 = S_ADD_U32 killed %1, killed %2, implicit-def $scc
36 %9:sreg_32 = S_ADDC_U32 killed %3, killed %4, implicit-def $scc, implicit $scc
38 %11:sreg_32 = S_ADDC_U32 killed %10, %6, implicit-def dead $scc, implicit $scc
42 # This case successfully converted scc definitions to vcc because the input
45 name: test-working-scc-def
48 ; GCN-LABEL: name: test-working-scc-def
69 %7:sreg_32 = S_ADD_U32 killed %6, killed %2, implicit-def $scc
70 %8:sreg_32 = S_ADDC_U32 killed %3, killed %4, implicit-def $scc, implicit $scc
[all …]
H A Doptimize-exec-masking-pre-ra.mir37 ; GCN-NEXT: $exec = S_AND_B64 $exec, [[COPY]], implicit-def dead $scc
60 ; GCN-NEXT: $exec = S_OR_B64 $exec, [[COPY2]], implicit-def $scc
72 %4:sreg_64 = S_AND_B64 %3, %2, implicit-def dead $scc
73 %5:sreg_64 = S_XOR_B64 %4, %3, implicit-def dead $scc
84 $exec = S_AND_B64 $exec, %0, implicit-def dead $scc
85 %7:sreg_64 = S_AND_B64 $exec, %6, implicit-def $scc
86 $exec = S_XOR_B64_term $exec, %7, implicit-def $scc
95 %10:sreg_64 = S_AND_B64 %9, %8, implicit-def dead $scc
103 $exec = S_OR_B64 $exec, %9, implicit-def $scc
106 $exec = S_OR_B64 $exec, %7, implicit-def $scc
[all …]
H A Dpei-scavenge-vgpr-spill.mir30 ; GFX8-NEXT: $sgpr6 = S_ADD_I32 $sgpr32, 1048832, implicit-def dead $scc
34 ; GFX8-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc
36 ; GFX8-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 2097152, implicit-def dead $scc
48 ; GFX8-NEXT: $sgpr6 = S_ADD_I32 $sgpr32, 1048832, implicit-def dead $scc
57 ; GFX9-NEXT: $sgpr6 = S_ADD_I32 $sgpr32, 1048832, implicit-def dead $scc
61 ; GFX9-NEXT: $sgpr33 = frame-setup S_ADD_I32 $sgpr32, 524224, implicit-def $scc
73 ; GFX9-NEXT: $sgpr6 = S_ADD_I32 $sgpr32, 1048832, implicit-def dead $scc
82 ; GFX9-FLATSCR-NEXT: $sgpr6 = S_ADD_I32 $sgpr32, 16388, implicit-def dead $scc
89 ; GFX9-FLATSCR-NEXT: $vcc_hi = S_ADD_I32 $sgpr33, 8192, implicit-def $scc
91 ; GFX9-FLATSCR-NEXT: $vcc_hi = S_ADD_I32 $sgpr33, 16384, implicit-def $scc
[all …]
H A Doptimize-negated-cond-exec-masking-wave32.mir6 # GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def dead $scc
15 $vcc_lo = S_AND_B32 $exec_lo, killed $vcc_lo, implicit-def dead $scc
28 # GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def dead $scc
37 $vcc_lo = S_AND_B32 killed %2, $exec_lo, implicit-def dead $scc
79 # GCN-NEXT: $vcc_lo = S_AND_B32 %2, $exec_lo, implicit-def dead $scc
89 $vcc_lo = S_AND_B32 killed %2, $exec_lo, implicit-def dead $scc
129 $vcc_lo = S_AND_B32 killed %2, $exec_lo, implicit-def dead $scc
167 # GCN-NEXT: $vcc_lo = S_AND_B32 %2, $exec_lo, implicit-def dead $scc
177 $vcc_lo = S_AND_B32 killed %2, $exec_lo, implicit-def dead $scc
253 $vcc_lo = S_AND_B32 killed %2, $exec_lo, implicit-def dead $scc
[all …]
H A Dearly-term.mir51 ; GCN: S_CBRANCH_SCC0 %bb.2, implicit $scc
68 SI_EARLY_TERMINATE_SCC0 implicit $scc, implicit $exec
89 ; GCN: S_CBRANCH_SCC0 %bb.3, implicit $scc
110 SI_EARLY_TERMINATE_SCC0 implicit $scc, implicit $exec
137 ; GCN: S_CBRANCH_SCC0 %bb.2, implicit $scc
140 ; GCN: liveins: $vgpr0, $scc
159 SI_EARLY_TERMINATE_SCC0 implicit $scc, implicit $exec
194 SI_EARLY_TERMINATE_SCC0 implicit $scc, implicit $exec
214 ; GCN: S_CBRANCH_SCC0 %bb.2, implicit $scc
247 ; GCN: S_CBRANCH_SCC0 %bb.2, implicit $scc
[all …]
H A Dsplitkit-getsubrangeformask.ll42 …ub1:sreg_64 = S_ADDC_U32 undef %54:sreg_32, [[S_ASHR_I32_2]], implicit-def dead $scc, implicit $scc
59 …DDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 undef %54:sreg_32, 0, implicit-def dead $scc, implicit $scc
61 …9.sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_]], [[S_ASHR_I32_]], implicit-def dead $scc, implicit $scc
64 ….sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_]], [[S_ASHR_I32_1]], implicit-def dead $scc, implicit $scc
66 ….sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_]], [[S_ASHR_I32_2]], implicit-def dead $scc, implicit $scc
69 ….sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_]], [[S_ASHR_I32_3]], implicit-def dead $scc, implicit $scc
71 …sub1:sreg_64 = S_ADDC_U32 undef %51:sreg_32, [[S_ASHR_I32_]], implicit-def dead $scc, implicit $scc
79 ….sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_1]], [[S_ASHR_I32_]], implicit-def dead $scc, implicit $scc
81 …sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_1]], [[S_ASHR_I32_1]], implicit-def dead $scc, implicit $scc
83 …sub1:sreg_64 = S_ADDC_U32 [[S_ADDC_U32_1]], [[S_ASHR_I32_2]], implicit-def dead $scc, implicit $scc
[all …]
H A Dfold-restore-undef-use.mir29 ; CHECK-NEXT: $exec = S_XOR_B64_term $exec, killed renamable $sgpr4_sgpr5, implicit-def $scc
35 …; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32
50 …; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32
53 …; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32
67 $exec = S_XOR_B64_term $exec, %1, implicit-def $scc
71 ADJCALLSTACKUP 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32
75 ADJCALLSTACKDOWN 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32
81 ADJCALLSTACKUP 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32
83 ADJCALLSTACKDOWN 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32
84 ADJCALLSTACKUP 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32
[all …]
H A Dlower-term-opcodes.mir43 ; CHECK-NEXT: $sgpr0 = S_XOR_B32 $sgpr1, $sgpr2, implicit-def $scc
48 ; CHECK-NEXT: $sgpr0_sgpr1 = S_XOR_B64 $sgpr2_sgpr3, $sgpr2_sgpr3, implicit-def $scc
53 ; CHECK-NEXT: $sgpr0 = S_OR_B32 $sgpr1, $sgpr2, implicit-def $scc
58 ; CHECK-NEXT: $sgpr0_sgpr1 = S_OR_B64 $sgpr2_sgpr3, $sgpr2_sgpr3, implicit-def $scc
63 ; CHECK-NEXT: $sgpr0 = S_ANDN2_B32 $sgpr1, $sgpr2, implicit-def $scc
86 $sgpr0 = S_XOR_B32_term $sgpr1, $sgpr2, implicit-def $scc
89 $sgpr0_sgpr1 = S_XOR_B64_term $sgpr2_sgpr3, $sgpr2_sgpr3, implicit-def $scc
92 $sgpr0 = S_OR_B32_term $sgpr1, $sgpr2, implicit-def $scc
95 $sgpr0_sgpr1 = S_OR_B64_term $sgpr2_sgpr3, $sgpr2_sgpr3, implicit-def $scc
98 $sgpr0 = S_ANDN2_B32_term $sgpr1, $sgpr2, implicit-def $scc
[all …]
/llvm-project-15.0.7/llvm/test/MC/AMDGPU/
H A Dgfx90a_err.s201 global_atomic_add_f32 v0, v[0:1], v2, off glc scc
204 global_atomic_add_f32 v[0:1], v2, off scc
207 global_atomic_add_f32 v0, v2, s[0:1] scc
210 global_atomic_add_f32 v1, v0, v2, s[0:1] glc scc
219 flat_atomic_add_f64 v[0:1], v[2:3] scc
222 flat_atomic_min_f64 v[0:1], v[2:3] scc
225 flat_atomic_max_f64 v[0:1], v[2:3] scc
228 global_atomic_add_f64 v[0:1], v[2:3], off scc
231 global_atomic_min_f64 v[0:1], v[2:3], off scc
234 global_atomic_max_f64 v[0:1], v[2:3], off scc
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