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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dmul.ll986 ; GFX7-NEXT: s_mul_i32 s35, s1, s12
988 ; GFX7-NEXT: s_add_u32 s24, s35, s24
991 ; GFX7-NEXT: s_cselect_b32 s35, 1, 0
1044 ; GFX7-NEXT: s_cmp_lg_u32 s35, 0
1207 ; GFX8-NEXT: s_mul_i32 s35, s1, s12
1209 ; GFX8-NEXT: s_add_u32 s24, s35, s24
1212 ; GFX8-NEXT: s_cselect_b32 s35, 1, 0
1265 ; GFX8-NEXT: s_cmp_lg_u32 s35, 0
1386 ; GFX9-NEXT: s_mul_i32 s35, s1, s12
1389 ; GFX9-NEXT: s_add_u32 s24, s35, s24
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dgfx-callable-argument-types.ll111 ; GFX9-NEXT: s_addc_u32 s35, s35, external_void_func_i1@rel32@hi+12
138 ; GFX10-NEXT: s_addc_u32 s35, s35, external_void_func_i1@rel32@hi+12
487 ; GFX9-NEXT: s_addc_u32 s35, s35, external_void_func_i8@rel32@hi+12
513 ; GFX10-NEXT: s_addc_u32 s35, s35, external_void_func_i8@rel32@hi+12
845 ; GFX9-NEXT: s_addc_u32 s35, s35, external_void_func_i16@rel32@hi+12
871 ; GFX10-NEXT: s_addc_u32 s35, s35, external_void_func_i16@rel32@hi+12
1203 ; GFX9-NEXT: s_addc_u32 s35, s35, external_void_func_i32@rel32@hi+12
1229 ; GFX10-NEXT: s_addc_u32 s35, s35, external_void_func_i32@rel32@hi+12
1320 ; GFX9-NEXT: s_addc_u32 s35, s35, external_void_func_i64@rel32@hi+12
1961 ; GFX9-NEXT: s_addc_u32 s35, s35, external_void_func_f16@rel32@hi+12
[all …]
H A Dgfx-callable-preserved-registers.ll229 ; GFX9-NEXT: s_addc_u32 s35, s35, external_void_func_void@rel32@hi+12
259 ; GFX10-NEXT: s_addc_u32 s35, s35, external_void_func_void@rel32@hi+12
344 ; GFX9-NEXT: s_addc_u32 s35, s35, external_void_func_void@rel32@hi+12
380 ; GFX10-NEXT: s_addc_u32 s35, s35, external_void_func_void@rel32@hi+12
460 ; GFX9-NEXT: s_addc_u32 s35, s35, external_void_func_void@rel32@hi+12
490 ; GFX10-NEXT: s_addc_u32 s35, s35, external_void_func_void@rel32@hi+12
576 ; GFX9-NEXT: s_addc_u32 s35, s35, external_void_func_void@rel32@hi+12
691 ; GFX9-NEXT: s_addc_u32 s35, s35, external_void_func_void@rel32@hi+12
725 ; GFX10-NEXT: s_addc_u32 s35, s35, external_void_func_void@rel32@hi+12
1093 ; GFX9-NEXT: s_addc_u32 s35, s35, external_void_func_void@rel32@hi+12
[all …]
H A Dspill_more_than_wavesize_csr_sgprs.ll12 "~{s35},~{s36},~{s37},~{s38},~{s39},~{s40},~{s41},~{s42}
34 "~{s35},~{s36},~{s37},~{s38},~{s39},~{s40},~{s41},~{s42}
H A Dtail-call-amdgpu-gfx.ll33 ; GCN-NEXT: s_addc_u32 s35, s35, callee@rel32@hi+12
H A Dindirect-call.ll405 ; GCN-NEXT: v_writelane_b32 v40, s35, 3
463 ; GCN-NEXT: v_readlane_b32 s35, v40, 3
573 ; GCN-NEXT: v_writelane_b32 v40, s35, 3
634 ; GCN-NEXT: v_readlane_b32 s35, v40, 3
745 ; GCN-NEXT: v_writelane_b32 v40, s35, 3
805 ; GCN-NEXT: v_readlane_b32 s35, v40, 3
987 ; GCN-NEXT: v_readlane_b32 s35, v40, 3
1185 ; GCN-NEXT: v_readlane_b32 s35, v40, 3
1380 ; GCN-NEXT: v_readlane_b32 s35, v40, 3
1583 ; GCN-NEXT: v_readlane_b32 s35, v40, 3
[all …]
H A Dgfx-call-non-gfx-func.ll41 ; SDAG-NEXT: s_addc_u32 s35, s35, extern_c_func@gotpcrel32@hi+12
121 ; GISEL-NEXT: s_addc_u32 s35, s35, extern_c_func@gotpcrel32@hi+12
H A Dwwm-reserved-spill.ll49 ; GFX9-O0-NEXT: s_mov_b32 s35, 1
51 ; GFX9-O0-NEXT: s_mov_b32 s35, 2
52 ; GFX9-O0-NEXT: v_and_b32_e64 v3, v3, s35
461 ; GFX9-O0-NEXT: v_mov_b32_e32 v2, s35
467 ; GFX9-O0-NEXT: s_mov_b32 s35, 0
545 ; GFX9-O0-NEXT: s_mov_b32 s35, s9
549 ; GFX9-O0-NEXT: v_mov_b32_e32 v9, s35
563 ; GFX9-O0-NEXT: s_addc_u32 s35, s35, strict_wwm_called_i64@gotpcrel32@hi+12
720 ; GFX9-O0-NEXT: s_mov_b32 s41, s35
786 ; GFX9-O3-NEXT: s_brev_b32 s35, -2
[all …]
H A Dcall-preserved-registers.ll11 ; GCN-NEXT: s_addc_u32 s35, s35,
31 ; GCN: v_writelane_b32 v40, s35, 3
37 ; GCN: v_readlane_b32 s35, v40, 3
H A Dpromote-constOffset-to-imm.ll35 ; GFX8-NEXT: v_mov_b32_e32 v4, s35
117 ; GFX900-NEXT: v_mov_b32_e32 v4, s35
261 ; GFX90A-NEXT: v_mov_b32_e32 v1, s35
444 ; GFX8-NEXT: v_mov_b32_e32 v5, s35
571 ; GFX900-NEXT: v_mov_b32_e32 v5, s35
803 ; GFX90A-NEXT: v_mov_b32_e32 v5, s35
1140 ; GFX8-NEXT: v_mov_b32_e32 v4, s35
1518 ; GFX8-NEXT: v_mov_b32_e32 v4, s35
1799 ; GFX8-NEXT: v_mov_b32_e32 v4, s35
2334 ; GFX8-NEXT: v_mov_b32_e32 v4, s35
[all …]
H A Ddwarf-multi-register-use-crash.ll26 ; CHECK-NEXT: v_writelane_b32 v40, s35, 3
89 ; CHECK-NEXT: v_readlane_b32 s35, v40, 3
H A Dgfx-callable-return-types.ll35 ; GFX9-NEXT: s_addc_u32 s35, s35, return_i1@gotpcrel32@hi+12
64 ; GFX10-NEXT: s_addc_u32 s35, s35, return_i1@gotpcrel32@hi+12
143 ; GFX9-NEXT: s_addc_u32 s35, s35, return_i16@gotpcrel32@hi+12
172 ; GFX10-NEXT: s_addc_u32 s35, s35, return_i16@gotpcrel32@hi+12
251 ; GFX9-NEXT: s_addc_u32 s35, s35, return_2xi16@gotpcrel32@hi+12
280 ; GFX10-NEXT: s_addc_u32 s35, s35, return_2xi16@gotpcrel32@hi+12
368 ; GFX9-NEXT: s_addc_u32 s35, s35, return_3xi16@gotpcrel32@hi+12
397 ; GFX10-NEXT: s_addc_u32 s35, s35, return_3xi16@gotpcrel32@hi+12
1650 ; GFX9-NEXT: s_addc_u32 s35, s35, return_512xi32@gotpcrel32@hi+12
1681 ; GFX10-NEXT: s_addc_u32 s35, s35, return_512xi32@gotpcrel32@hi+12
H A Dbranch-relax-spill.ll120 ; CHECK-NEXT: s_mov_b32 s35, 0
461 ; CHECK-NEXT: ; reg use s35
704 %sgpr35 = tail call i32 asm sideeffect "s_mov_b32 s35, 0", "={s35}"() #0
825 tail call void asm sideeffect "; reg use $0", "{s35}"(i32 %sgpr35) #0
910 ; CHECK-NEXT: v_writelane_b32 v0, s35, 4
1086 ; CHECK-NEXT: s_mov_b32 s35, 0
1427 ; CHECK-NEXT: ; reg use s35
1699 ; CHECK-NEXT: v_readlane_b32 s35, v0, 4
1747 %sgpr35 = tail call i32 asm sideeffect "s_mov_b32 s35, 0", "={s35}"() #0
1868 tail call void asm sideeffect "; reg use $0", "{s35}"(i32 %sgpr35) #0
H A Dsgpr-spills-split-regalloc.ll196 ; GCN: v_writelane_b32 [[B:v[0-9]+]], s35, 0
208 ; GCN: v_readlane_b32 s35, [[G]], 0
243 "~{s34},~{s35},~{s36},~{s37}" () #0
H A Dinsert_vector_dynelt.ll1071 ; GCN-NEXT: s_lshr_b32 s35, s7, 24
1134 ; GCN-NEXT: v_lshrrev_b16_e64 v17, 7, s35
1137 ; GCN-NEXT: v_lshrrev_b16_e64 v18, 6, s35
1145 ; GCN-NEXT: v_lshrrev_b16_e64 v18, 5, s35
1148 ; GCN-NEXT: v_lshrrev_b16_e64 v19, 4, s35
1159 ; GCN-NEXT: v_lshrrev_b16_e64 v18, 3, s35
1162 ; GCN-NEXT: v_lshrrev_b16_e64 v19, 2, s35
1167 ; GCN-NEXT: v_mov_b32_e32 v14, s35
1173 ; GCN-NEXT: v_lshrrev_b16_e64 v19, 1, s35
H A Dload-constant-i16.ll2186 ; GCN-HSA-NEXT: s_lshr_b32 s35, s19, 16
2216 ; GCN-HSA-NEXT: v_mov_b32_e32 v3, s35
2572 ; GCN-HSA-NEXT: s_ashr_i32 s35, s19, 16
2590 ; GCN-HSA-NEXT: v_mov_b32_e32 v3, s35
3045 ; GCN-HSA-NEXT: s_lshr_b32 s35, s15, 16
3177 ; GCN-HSA-NEXT: v_mov_b32_e32 v11, s35
3789 ; GCN-HSA-NEXT: s_ashr_i32 s35, s31, 16
3910 ; GCN-HSA-NEXT: v_mov_b32_e32 v11, s35
5846 ; GCN-HSA-NEXT: v_mov_b32_e32 v1, s35
6305 ; GCN-HSA-NEXT: v_mov_b32_e32 v0, s35
[all …]
/llvm-project-15.0.7/clang/test/CodeGen/
H A Darm-arguments.c191 struct s35 struct
195 typedef struct s35 s35_with_align; argument
H A Darm64-arguments.c236 struct s35 struct
240 typedef struct s35 s35_with_align; argument
/llvm-project-15.0.7/llvm/test/MC/Hexagon/
H A Dsysregs.s42 r1:0=s35:34
43 # CHECK: r1:0 = s35:34
H A Dsysregs2.s101 r10=s35
102 # CHECK: { r10 = s35 }
/llvm-project-15.0.7/llvm/test/CodeGen/VE/Scalar/
H A Dva_caller.ll31 ; CHECK-NEXT: ld %s35, (, %s1)
47 ; CHECK-NEXT: st %s35, 272(, %s11)
/llvm-project-15.0.7/clang/test/CodeGen/X86/
H A Dx86_32-arguments-darwin.c145 struct s35 { struct { int : 0; } a; char b; char c; } f35(void) { while (1) {} } in f35() argument
/llvm-project-15.0.7/clang/test/Sema/
H A Dtest-wunaligned-access.c497 struct U35 s35; variable
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dlegalize-extracts.mir299 %val:_(s35) = G_IMPLICIT_DEF
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td324 def S35 : Rs<35, "s35">, DwarfRegNum<[179]>;
391 def S35_34 : Rss<34, "s35:34", [ISDBCFG1, S35]>, DwarfRegNum<[178]>;

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