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/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DExecutionDomainFix.cpp76 if (LiveRegs[rx]) in setLiveReg()
84 if (!LiveRegs[rx]) in kill()
122 for (unsigned rx = 0; rx != NumRegs; ++rx) in collapse() local
144 for (unsigned rx = 0; rx != NumRegs; ++rx) { in merge() local
178 for (unsigned rx = 0; rx != NumRegs; ++rx) { in enterBasicBlock() local
252 kill(rx); in processDefs()
276 kill(rx); in visitHardInstr()
315 kill(rx); in visitSoftInstr()
335 kill(rx); in visitSoftInstr()
387 if (!LiveRegs[rx] || (mo.isDef() && LiveRegs[rx] != dv)) { in visitSoftInstr()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYInstrFormats16Instr.td31 bits<3> rx;
44 bits<4> rx;
57 bits<4> rx;
70 bits<4> rx;
83 bits<4> rx;
95 bits<4> rx;
108 bits<4> rx;
119 bits<4> rx;
151 bits<3> rx;
175 bits<3> rx;
[all …]
H A DCSKYInstrFormats.td84 bits<5> rx;
134 bits<5> rx;
147 bits<5> rx;
174 bits<5> rx;
186 bits<5> rx;
202 bits<5> rx;
214 bits<5> rx;
227 bits<5> rx;
270 bits<5> rx;
288 bits<5> rx;
[all …]
H A DCSKYInstrFormatsF1.td42 bits<5> rx;
45 let Inst{20 - 16} = {rx};
56 : F_XZ_FG<3, sop, (outs regtype1:$vrz), (ins regtype2:$rx), !strconcat(op, "\t$vrz, $rx"),
144 bits<5> rx;
149 let Inst{20 - 16} = rx; //rx
159 bits<5> rx;
163 let Inst{20 - 16} = rx; //rx
176 let Inst{20 - 16} = 0; //rx
185 bits<5> rx;
191 let Inst{20 - 16} = rx; // rx;
[all …]
H A DCSKYInstrInfo.td516 def NEG32 : CSKYPseudo<(outs GPR:$rd), (ins GPR:$rx), "neg32 $rd, $rx", []>;
780 bits<5> rx;
783 let Inst{20 - 16} = rx;
898 (outs GPR:$rx), (ins), "mfcr\t$rx, fcr", []> {
899 bits<5> rx;
905 let Inst{4 - 0} = rx;
911 (outs), (ins GPR:$rx), "mtcr\t$rx, fcr", []> {
912 bits<5> rx;
1289 def : Pat<(bitreverse GPR:$rx), (BREV32 GPR:$rx)>;
1290 def : Pat<(bswap GPR:$rx), (REVB32 GPR:$rx)>;
[all …]
H A DCSKYInstrInfoF2.td379 (f2FSEL_S (f2FCMPHSZ_S FPR32Op:$rs1), FPR32Op:$rx, FPR32Op:$false)>;
385 (f2FSEL_S (f2FCMPLTZ_S FPR32Op:$rs1), FPR32Op:$rx, FPR32Op:$false)>;
391 (f2FSEL_S (f2FCMPLSZ_S FPR32Op:$rs1), FPR32Op:$rx, FPR32Op:$false)>;
397 (f2FSEL_S (f2FCMPHZ_S FPR32Op:$rs1), FPR32Op:$rx, FPR32Op:$false)>;
403 (f2FSEL_S (f2FCMPNEZ_S FPR32Op:$rs1), FPR32Op:$rx, FPR32Op:$false)>;
409 (f2FSEL_S (f2FCMPUOZ_S FPR32Op:$rs1), FPR32Op:$rx, FPR32Op:$false)>;
433 (f2FSEL_S (f2FCMPHZ_S FPR32Op:$rs1), FPR32Op:$rx, FPR32Op:$false)>;
458 def : Pat<(select CARRY:$ca, FPR32Op:$rx, FPR32Op:$false),
459 (f2FSEL_S CARRY:$ca, FPR32Op:$rx, FPR32Op:$false)>;
461 def : Pat<(select CARRY:$ca, FPR64Op:$rx, FPR64Op:$false),
[all …]
H A DCSKYInstrInfo16Instr.td119 def NEG16 : CSKYPseudo<(outs mGPR:$rd), (ins mGPR:$rx), "neg16 $rd, $rx", []>;
123 (ins mGPR:$rx, uimm8:$imm8), "rsubi16 $rd, $rx, $imm8", []>;
178 bits<4> rx;
182 let Inst{5 - 2} = rx;
233 (ins mGPR:$rx, uimm2_jmpix:$indeximm2), "jmpix16\t$rx, $indeximm2", []> {
234 bits<3> rx;
323 bits<4> rx;
327 let Inst{5 - 2} = rx;
334 bits<4> rx;
338 let Inst{5 - 2} = rx;
[all …]
H A DCSKYInstrFormatsF2.td119 !strconcat(op, "\t$vrz, ($rx, ${imm8})"), []> {
121 bits<5> rx;
126 let Inst{20-16} = rx;
141 !strconcat(op, "\t$regs, (${rx})"), []> {
143 bits<5> rx;
146 let Inst{20-16} = rx;
162 op#"\t$rz, ($rx, $ry << ${imm})", []> {
163 bits<5> rx;
169 let Inst{20-16} = rx;
197 bits<5> rx;
H A DCSKYInstrInfoF1.td148 def FMTVRL : F_XZ_FG<3, 0b011011, (outs sFPR32Op:$vrz), (ins GPR:$rx),
149 "fmtvrl\t$vrz, $rx", [(set sFPR32Op:$vrz, (bitconvert GPR:$rx))]>;
158 def FMTVRL_D : F_XZ_FG<3, 0b011011, (outs sFPR64Op:$vrz), (ins GPR:$rx),
159 "fmtvrl\t$vrz, $rx", []>;
161 def FMTVRH_D : F_XZ_FG<3, 0b011010, (outs sFPR64Op:$vrz), (ins sFPR64Op:$vrZ, GPR:$rx),
162 "fmtvrh\t$vrz, $rx", []>;
259 (outs), (ins GPR:$rx, regseq_d1:$regs, variable_ops), "fldmm\t$regs, (${rx})", []>;
275 (outs), (ins GPR:$rx, regseq_d1:$regs, variable_ops), "fstmm\t$regs, (${rx})", []>;
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMips16InstrInfo.td368 let rx=0 in
578 // Format: AND rx, ry MIPS16e
690 // Format: CMP rx, ry MIPS16e
718 // Format: DIV rx, ry MIPS16e
874 // Format: MFHI rx MIPS16e
885 // Format: MFLO rx MIPS16e
933 // Format: NEG rx, ry MIPS16e
940 // Format: NOT rx, ry MIPS16e
947 // Format: OR rx, ry MIPS16e
1010 // Format: SEB rx MIPS16e
[all …]
H A DMips16InstrFormats.td121 bits<3> rx;
138 bits<3> rx;
171 bits<3> rx;
209 bits<3> rx;
235 bits<3> rx;
255 bits<3> rx;
277 bits<3> rx;
488 bits<3> rx;
512 bits<3> rx;
536 bits<3> rx;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCMacroFusion.def76 // sldi rx, ra, {3, 6} - {add, subf}
77 // sldi rx, ra n is alias of rldicr rx, ra, n, 63-n
81 // rldicl rx, ra, 1, 0 - xor
86 // rldicr rx, ra, 1, 63 - xor
94 // { lbz,lbzx,lhz,lhzx,lwz,lwzx } - cmpi 0,1,rx,{ 0,1,-1 }
95 // { lbz,lbzx,lhz,lhzx,lwz,lwzx } - cmpli 0,L,rx,{ 0,1 }
103 // { ld,ldx } - cmpi 0,1,rx,{ 0,1,-1 }
104 // { ld,ldx } - cmpli 0,1,rx,{ 0,1 }
109 // { lha,lhax,lwa,lwax } - cmpi 0,L,rx,{ 0,1,-1 }
135 // addis rx,ra,si - addi rt,rx,SI, SI >= 0
[all …]
/llvm-project-15.0.7/flang/test/Semantics/
H A Dstructconst02.f9015 real(kind=rk) :: rx = real(0.,kind=rk) component
33 call scalararg(scalar(4)(ix=1,rx=2.,zx=(3.,4.),cx='a',lx=.true.))
37 call scalararg(scalar(4)(ix=5.,rx=6,zx=(7._8,8._2),cx=4_'b',lx=.true.))
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DExecutionDomainFix.h180 void setLiveReg(int rx, DomainValue *DV);
183 void kill(int rx);
186 void force(int rx, unsigned domain);
/llvm-project-15.0.7/flang/lib/Evaluate/
H A Dtools.cpp128 [&](Expr<SomeReal> &&rx, in ConvertRealOperands()
131 std::move(rx), ConvertTo(rx, std::move(iy)))}; in ConvertRealOperands()
133 [&](Expr<SomeReal> &&rx, in ConvertRealOperands() argument
136 std::move(rx), std::move(ry))}; in ConvertRealOperands()
154 [&](Expr<SomeReal> &&rx, in ConvertRealOperands() argument
157 std::move(rx), ConvertTo(rx, std::move(by)))}; in ConvertRealOperands()
192 Expr<SomeReal> &&rx, Expr<SomeInteger> &&iy) { in MixedRealLeft() argument
205 std::move(rx.u))); in MixedRealLeft()
377 [](Expr<SomeReal> &&rx, Expr<SomeReal> &&ry) { in NumericOperation() argument
379 std::move(rx), std::move(ry))); in NumericOperation()
[all …]
/llvm-project-15.0.7/llvm/test/TableGen/
H A DLetInsideMultiClasses.td22 def rx : Instruction<opc, "rx">;
/llvm-project-15.0.7/clang/test/CodeGen/
H A Dbuiltins-hexagon-v66.c6 int test1(int rx, int rs, int rt) { in test1() argument
7 return __builtin_HEXAGON_M2_mnaci(rx, rs, rt); in test1()
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dintrinsics-v66.ll5 define i32 @test1(i32 %rx, i32 %rs, i32 %rt) local_unnamed_addr #0 {
7 %v0 = tail call i32 @llvm.hexagon.M2.mnaci(i32 %rx, i32 %rs, i32 %rt)
/llvm-project-15.0.7/lld/test/ELF/linkerscript/
H A Dmemory-at.test13 FLASH (rx) : ORIGIN = 0x1000, LENGTH = 0x100
H A Dlma-align2.test23 CODE (rx) : ORIGIN = 0x08000000, LENGTH = 100K
/llvm-project-15.0.7/lldb/test/Shell/SymbolFile/NativePDB/Inputs/
H A Dfunction-types-builtins.lldbinit54 dv rx
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/autohvx/
H A Dwiden-trunc.ll3 ; If the "rx = #N, vsetq(rx)" get reordered with the rest, update the test.
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dstack-no-redzone.ll12 ; stwux r1, rx, r1
18 ; mr r1, rx
/llvm-project-15.0.7/lldb/test/Shell/SymbolFile/NativePDB/
H A Dfunction-types-builtins.cpp171 auto rx = &unaryret<volatile int*, 22>; variable
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A DPBQP-chain.ll23 define void @fir(double* nocapture %rx, double* nocapture %ry, double* nocapture %c, double* nocapt…
100 store double %add.7, double* %rx, align 8

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