Lines Matching refs:rx
81 (outs GPR:$rz), (ins GPR:$rx,ImmType:$imm16),
82 !strconcat(op, "\t$rz, $rx, $imm16"), pattern> {
84 bits<5> rx;
87 let Inst{20 - 16} = rx;
132 : CSKY32Inst<AddrModeNone, 0x3a, (outs), (ins GPR:$rx),
133 !strconcat(op, "\t$rx"), pattern> {
134 bits<5> rx;
137 let Inst{20 - 16} = rx;
145 (ins GPR:$rx, operand:$imm2),
146 !strconcat(op, "\t$rx, $imm2"), pattern> {
147 bits<5> rx;
150 let Inst{20 - 16} = rx;
172 (ins GPR:$rx, operand:$imm16), !strconcat(op, "\t$rx, $imm16"), []> {
174 bits<5> rx;
176 let Inst{20 - 16} = rx;
184 : CSKY32Inst<AddrModeNone, 0x3a, (outs), (ins GPR:$rx, operand:$imm16),
185 !strconcat(op, "\t$rx, $imm16"), []> {
186 bits<5> rx;
189 let Inst{20 - 16} = rx;
199 (ins GPR:$rx, ImmType:$imm12), !strconcat(op, "\t$rz, $rx, $imm12"),
200 [(set GPR:$rz, (node GPR:$rx, ImmType:$imm12))]> {
202 bits<5> rx;
205 let Inst{20 - 16} = rx;
212 : CSKY32Inst<am, opcode, outs, ins, !strconcat(op, "\t$rz, ($rx, ${imm12})"),
214 bits<5> rx;
218 let Inst{20 - 16} = rx;
225 : CSKY32Inst<am, opcode, outs, ins, !strconcat(op, "\t($rx, ${imm12})"),
227 bits<5> rx;
230 let Inst{20 - 16} = rx;
240 (outs GPR:$rz), (ins GPR:$rx, operand:$imm12), op, []>;
246 (ins GPR:$rz, GPR:$rx, operand:$imm12), op, []>;
267 (ins CARRY:$cond, GPR:$false, GPR:$rx, ImmType:$imm5),
268 !strconcat(op, "\t$rz, $rx, $imm5"), pattern> {
270 bits<5> rx;
273 let Inst{20 - 16} = rx;
286 !strconcat(op, "\t$rz, $rx, $imm5"), pattern> {
288 bits<5> rx;
291 let Inst{20 - 16} = rx;
302 bits<5> rx;
305 let Inst{20 - 16} = rx;
376 : CSKY32Inst<AddrModeNone, 0x30, (outs), (ins GPR:$rx), opStr #"\t$rx", []> {
377 bits<5> rx;
380 let Inst{20 - 16} = rx;
391 bits<5> rx;
394 let Inst{20 - 16} = rx;
403 : CSKY32Inst<AddrModeNone, 0x31, outs, ins, op #"\t$rz, $rx, $msb, $lsb",
405 bits<5> rx;
410 let Inst{20 - 16} = rx;
417 : CSKY32Inst<AddrModeNone, 0x31, outs, ins, op #"\t$rz, $rx, $msb, $lsb",
419 bits<5> rx;
424 let Inst{20 - 16} = rx;
434 : CSKY32Inst<AddrModeNone, 0x31, outs, ins, !strconcat(op, "\t$rz, $rx"), pattern> {
435 bits<5> rx;
438 let Inst{20 - 16} = rx;
451 bits<5> rx;
453 let Inst{20 - 16} = rx;
462 : I_5_XZ_U2<sop, lsb, msb, (outs GPR:$rz), (ins GPR:$rx), op,
463 [(set GPR:$rz, (opnode GPR:$rx, type))]>;
466 : I_5_XZ_U2<sop, lsb, msb, (outs GPR:$rz), (ins GPR:$rx), op,
467 [(set GPR:$rz, (and GPR:$rx, (i32 v)))]>;
474 (outs CARRY:$ca), (ins GPR:$rx, ImmType:$imm5),
475 !strconcat(op, "\t$rx, $imm5"), pattern> {
477 bits<5> rx;
479 let Inst{20 - 16} = rx;
520 !strconcat(op, "\t$rz, $rx, $ry"), pattern> {
522 bits<5> rx;
525 let Inst{20 - 16} = rx;
533 // Input: GPR:rx, GPR:ry
534 // Asm string: op rz, rx, ry
539 (ins GPR:$rx, GPR:$ry), op, [(set GPR:$rz, (opnode GPR:$rx, GPR:$ry))]> {
549 op # "\t$rz, ($rx, $ry << ${imm})", pattern> {
550 bits<5> rx;
555 let Inst{20 - 16} = rx; // rx;
562 (outs GPR:$rz), (ins GPR:$rx, GPR:$ry, uimm_shift:$imm), op, []>;
565 (outs), (ins GPR:$rz, GPR:$rx, GPR:$ry, uimm_shift:$imm), op, []>;
571 : CSKY32Inst<AddrModeNone, 0x31, outs, ins, !strconcat(op, "\t$rz, $rx"),
573 bits<5> rx;
575 let Inst{25 - 21} = rx;
576 let Inst{20 - 16} = rx;
586 (ins GPR:$rx, GPR:$ry),
587 !strconcat(op, "\t$rx, $ry"), []> {
589 bits<5> rx;
591 let Inst{20 - 16} = rx;
603 : CSKY32Inst<AddrModeNone, 0x31, (outs GPR:$rz), (ins GPR:$rx),
604 !strconcat(op, "\t$rz, $rx"), []> {
605 bits<5> rx;
608 let Inst{20 - 16} = rx;
618 (ins CARRY:$ca, GPR:$rx, GPR:$false),
619 !strconcat(op, "\t$rz, $rx"), pattern> {
621 bits<5> rx;
623 let Inst{20 - 16} = rx;
634 : CSKY32Inst<AddrModeNone, 0x31, outs, ins, !strconcat(op, "\t$rx"), pattern> {
635 bits<5> rx;
637 let Inst{20 - 16} = rx;