Lines Matching refs:rx
82 FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm),
87 FRI16_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
91 FRI16<_op, (outs CPU16Regs:$rx), (ins pcrel16:$imm, i32imm:$size),
92 !strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin>;
96 FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm),
101 FRI16R_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
105 FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
106 !strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin> {
107 let Constraints = "$rx_ = $rx";
112 FRI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
113 !strconcat(asmstr, "\t$rx, $imm # 16 bit inst"), [], itin>;
121 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm),
122 !strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), []> {
181 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry),
182 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), []> {
193 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm),
198 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
202 FEXT_RI16<_op, (outs ), (ins CPU16Regs:$rx, simm16:$imm),
207 FEXT_RI16R_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
210 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>;
214 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
215 !strconcat(asmstr, "\t$rx, $imm"), [], itin>;
219 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins pcrel16:$imm, i32imm:$size),
220 !strconcat(asmstr, "\t$rx, $imm"), [], itin>;
224 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
225 !strconcat(asmstr, "\t$rx, $imm"), [], itin> {
226 let Constraints = "$rx_ = $rx";
257 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, uimm5:$sa),
258 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>;
265 (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm),
266 !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t",
277 (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ),
278 !strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t",
308 MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
309 !strconcat(asmstr, "\t$rx, $ry"), []>;
315 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
316 !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> {
325 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
326 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
335 FRR16<f, (outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
336 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
340 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
341 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), []> ;
347 FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry),
348 !strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ;
351 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
352 !strconcat(asmstr, "\t$rx, $ry"), [], itin> ;
357 FRR16<f, (outs CPU16Regs:$rx), (ins),
358 !strconcat(asmstr, "\t$rx"), [], itin>;
362 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
365 let Constraints = "$rx = $rz";
368 let rx=0 in
377 FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx),
378 !strconcat(asmstr, "\t$rx"), [], itin> ;
383 FRR_SF16<_funct, _subfunc, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_),
384 !strconcat(asmstr, "\t $rx"),
386 let Constraints = "$rx_ = $rx";
393 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
394 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
489 MipsPseudo16<(outs CPU16Regs:$rx), (ins simm32:$imm, simm32:$constid),
490 "lw\t$rx, 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t$imm\n2:", []>;
525 // Format: ADDIU rx, immediate MIPS16e
545 // Format: ADDIU rx, pc, immediate MIPS16e
570 // Format: ADDU rz, rx, ry MIPS16e
578 // Format: AND rx, ry MIPS16e
586 // Format: BEQZ rx, offset MIPS16e
594 // Format: BEQZ rx, offset MIPS16e
615 // Format: BNEZ rx, offset MIPS16e
622 // Format: BNEZ rx, offset MIPS16e
690 // Format: CMP rx, ry MIPS16e
699 // Format: CMPI rx, immediate MIPS16e
708 // Format: CMPI rx, immediate MIPS16e
718 // Format: DIV rx, ry MIPS16e
727 // Format: DIVU rx, ry MIPS16e
784 // Format: LB ry, offset(rx) MIPS16e
793 // Format: LBU ry, offset(rx) MIPS16e
803 // Format: LH ry, offset(rx) MIPS16e
812 // Format: LHU ry, offset(rx) MIPS16e
822 // Format: LI rx, immediate MIPS16e
829 // Format: LI rx, immediate MIPS16e
840 // Format: LW ry, offset(rx) MIPS16e
848 // Format: LW rx, offset(sp) MIPS16e
874 // Format: MFHI rx MIPS16e
885 // Format: MFLO rx MIPS16e
911 // Format: MULT rx, ry MIPS16e
922 // Format: MULTU rx, ry MIPS16e
933 // Format: NEG rx, ry MIPS16e
940 // Format: NOT rx, ry MIPS16e
947 // Format: OR rx, ry MIPS16e
1002 // Format: SB ry, offset(rx) MIPS16e
1010 // Format: SEB rx MIPS16e
1012 // Sign-extend least significant byte in register rx.
1018 // Format: SEH rx MIPS16e
1020 // Sign-extend least significant word in register rx.
1140 // Format: SH ry, offset(rx) MIPS16e
1148 // Format: SLL rx, ry, sa MIPS16e
1155 // Format: SLLV ry, rx MIPS16e
1161 // Format: SLTI rx, immediate MIPS16e
1171 // Format: SLTI rx, immediate MIPS16e
1182 // Format: SLTIU rx, immediate MIPS16e
1192 // Format: SLTI rx, immediate MIPS16e
1201 // Format: SLTIU rx, immediate MIPS16e
1208 // Format: SLT rx, ry MIPS16e
1218 // Format: SLTU rx, ry MIPS16e
1234 // Format: SRAV ry, rx MIPS16e
1243 // Format: SRA rx, ry, sa MIPS16e
1252 // Format: SRLV ry, rx MIPS16e
1261 // Format: SRL rx, ry, sa MIPS16e
1269 // Format: SUBU rz, rx, ry MIPS16e
1276 // Format: SW ry, offset(rx) MIPS16e
1283 // Format: SW rx, offset(sp) MIPS16e
1284 // Purpose: Store Word rx (SP-Relative)
1291 // Format: XOR rx, ry MIPS16e
1393 Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry),
1394 (I CPU16Regs:$rx, CPU16Regs:$ry)>;
1397 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16),
1398 (I CPU16Regs:$rx, imm_type:$imm16)>;
1426 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1427 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1432 <(brcond (i32 (seteq CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1433 (BteqzT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1437 <(brcond (i32 (seteq CPU16Regs:$rx, 0)), bb:$targ16),
1438 (BeqzRxImm16 CPU16Regs:$rx, bb:$targ16)
1445 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1446 (BtnezT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1453 <(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1454 (BteqzT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1460 <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1461 (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1468 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1469 (BtnezT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1473 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1474 (BtnezT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1481 <(brcond (i32 (setle CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1482 (BteqzT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1489 <(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1490 (BtnezT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1494 <(brcond (i32 (setne CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1495 (BtnezT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1499 <(brcond (i32 (setne CPU16Regs:$rx, 0)), bb:$targ16),
1500 (BnezRxImm16 CPU16Regs:$rx, bb:$targ16)
1507 <(brcond CPU16Regs:$rx, bb:$targ16),
1508 (BnezRxImm16 CPU16Regs:$rx, bb:$targ16)
1517 // <(brcond (i32 (setugt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1518 // (BtnezT8SltuX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1525 // <(brcond (i32 (setuge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1526 // (BteqzT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1534 // <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1535 // (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1550 <(MipsDivRem16 CPU16Regs:$rx, CPU16Regs:$ry),
1551 (DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1557 <(MipsDivRemU16 CPU16Regs:$rx, CPU16Regs:$ry),
1558 (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;