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/llvm-project-15.0.7/libcxx/test/std/numerics/bit/bitops.rot/
H A Drotr.pass.cpp31 ASSERT_NOEXCEPT(std::rotr(T(), 0)); in test()
33 T highbit = std::rotr(T(1), 1); in test()
44 assert(std::rotr(T(128), 0) == T(128)); in test()
45 assert(std::rotr(T(128), 1) == T(64)); in test()
46 assert(std::rotr(T(128), 2) == T(32)); in test()
47 assert(std::rotr(T(128), 3) == T(16)); in test()
48 assert(std::rotr(T(128), 4) == T(8)); in test()
49 assert(std::rotr(T(128), 5) == T(4)); in test()
50 assert(std::rotr(T(128), 6) == T(2)); in test()
51 assert(std::rotr(T(128), 7) == T(1)); in test()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dbswap.ll14 ; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
18 ; MM: rotr ${{[0-9]+}}, $[[R0]], 16
22 ; MIPS64: rotr ${{[0-9]+}}, $[[R0]], 16
45 ; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
47 ; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
51 ; MM: rotr ${{[0-9]+}}, $[[R0]], 16
53 ; MM: rotr ${{[0-9]+}}, $[[R0]], 16
99 ; MM-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
101 ; MM-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
103 ; MM-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
[all …]
H A Drotate.ll22 ; CHECK: rotr $2, $4, 22
24 ; MM32: rotr $2, $4, 22
45 ; CHECK: rotr $2, $4, 10
47 ; MM32: rotr $2, $4, 10
/llvm-project-15.0.7/llvm/test/MC/Mips/
H A Drotations32.s25 # CHECK-32R: rotr $4, $4, 0 # encoding: [0x00,0x24,0x20,0x02]
28 # CHECK-32R: rotr $4, $5, 0 # encoding: [0x00,0x25,0x20,0x02]
33 # CHECK-32R: rotr $4, $4, 31 # encoding: [0x00,0x24,0x27,0xc2]
38 # CHECK-32R: rotr $4, $5, 31 # encoding: [0x00,0x25,0x27,0xc2]
43 # CHECK-32R: rotr $4, $4, 30 # encoding: [0x00,0x24,0x27,0x82]
48 # CHECK-32R: rotr $4, $5, 30 # encoding: [0x00,0x25,0x27,0x82]
64 # CHECK-32R: rotr $4, $4, 0 # encoding: [0x00,0x24,0x20,0x02]
67 # CHECK-32R: rotr $4, $5, 0 # encoding: [0x00,0x25,0x20,0x02]
72 # CHECK-32R: rotr $4, $4, 1 # encoding: [0x00,0x24,0x20,0x42]
77 # CHECK-32R: rotr $4, $5, 1 # encoding: [0x00,0x25,0x20,0x42]
[all …]
H A Dset-mips0-directive.s5 rotr $7, $7, 22
10 rotr $2, $2, 15
15 rotr $3, $3, 19
17 # CHECK: rotr $7, $7, 22
22 # CHECK: rotr $2, $2, 15
27 # CHECK: rotr $3, $3, 19
H A Dset-mips-directives.s19 rotr $2,15
22 rotr $2,15
25 rotr $2,15
55 # CHECK: rotr $2, $2, 15
58 # CHECK: rotr $2, $2, 15
61 # CHECK: rotr $2, $2, 15
H A Drotations64.s25 # CHECK-64R: rotr $4, $4, 0 # encoding: [0x00,0x24,0x20,0x02]
28 # CHECK-64R: rotr $4, $5, 0 # encoding: [0x00,0x25,0x20,0x02]
33 # CHECK-64R: rotr $4, $4, 31 # encoding: [0x00,0x24,0x27,0xc2]
38 # CHECK-64R: rotr $4, $5, 31 # encoding: [0x00,0x25,0x27,0xc2]
43 # CHECK-64R: rotr $4, $4, 30 # encoding: [0x00,0x24,0x27,0x82]
48 # CHECK-64R: rotr $4, $5, 30 # encoding: [0x00,0x25,0x27,0x82]
64 # CHECK-64R: rotr $4, $4, 0 # encoding: [0x00,0x24,0x20,0x02]
67 # CHECK-64R: rotr $4, $5, 0 # encoding: [0x00,0x25,0x20,0x02]
72 # CHECK-64R: rotr $4, $4, 1 # encoding: [0x00,0x24,0x20,0x42]
77 # CHECK-64R: rotr $4, $5, 1 # encoding: [0x00,0x25,0x20,0x42]
[all …]
H A Dset-arch.s18 rotr $2, $2, 15
21 rotr $2, $2, 15
24 rotr $2, $2, 15
59 # CHECK: rotr $2, $2, 15
H A Dmicromips-shift-instructions.s16 # CHECK-EL: rotr $9, $6, 7 # encoding: [0x26,0x01,0xc0,0x38]
36 # CHECK-EB: rotr $9, $6, 7 # encoding: [0x01,0x26,0x38,0xc0]
53 rotr $9, $6, 7
H A Dmips64-alu-instructions.s17 # CHECK: rotr $9, $6, 7 # encoding: [0xc2,0x49,0x26,0x00]
45 rotr $9, $6, 7
H A Dmips-alu-instructions.s19 # CHECK: rotr $9, $6, 7 # encoding: [0xc2,0x49,0x26,0x00]
50 rotr $9, $6, 7
/llvm-project-15.0.7/llvm/test/TableGen/
H A DSetTheory.td115 // The 'rotr' operator rotates right, but also accepts a negative shift.
116 def rotr;
117 def S7a : Set<(rotr S0f, 0)>;
118 def S7b : Set<(rotr S0f, 1)>;
119 def S7c : Set<(rotr S0f, 3)>;
120 def S7d : Set<(rotr S0f, 4)>;
121 def S7e : Set<(rotr S0f, 5)>;
122 def S7f : Set<(rotr S0f, -1)>;
123 def S7g : Set<(rotr S0f, -4)>;
124 def S7h : Set<(rotr S0f, -5)>;
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dror.ll4 ; rotr (rotr x, 4), 6 -> rotr x, 10 -> ror r0, r0, #10
16 ; rotl (rotr x, 4), 6 -> rotl x, 2 -> ror r0, r0, #30
/llvm-project-15.0.7/llvm/test/MC/LoongArch/Basic/Integer/
H A Dbit-shift.s28 # CHECK-ASM-AND-OBJ: rotr.w $ra, $s3, $t6
30 rotr.w $ra, $s3, $t6
67 # CHECK64-ASM-AND-OBJ: rotr.d $s8, $sp, $ra
69 rotr.d $s8, $sp, $ra
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrShiftRotate.td559 [(set GR8:$dst, (rotr GR8:$src1, CL))]>;
568 [(set GR64:$dst, (rotr GR64:$src1, CL))]>;
816 def : Pat<(rotr GR8:$src1, (i8 7)), (ROL8r1 GR8:$src1)>;
916 def : Pat<(rotr GR32:$src, (i8 imm:$shamt)),
918 def : Pat<(rotr GR64:$src, (i8 imm:$shamt)),
927 def : Pat<(rotr (loadi32 addr:$src), (i8 imm:$shamt)),
929 def : Pat<(rotr (loadi64 addr:$src), (i8 imm:$shamt)),
1026 def : Pat<(rotr GR8:$src1, (i8 relocImm:$src2)),
1028 def : Pat<(rotr GR16:$src1, (i8 relocImm:$src2)),
1030 def : Pat<(rotr GR32:$src1, (i8 relocImm:$src2)),
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/
H A Dbswap.ll24 ; MIPS32R2-NEXT: rotr $2, $1, 16
60 ; MIPS32R2-NEXT: rotr $2, $1, 16
62 ; MIPS32R2-NEXT: rotr $3, $1, 16
H A Dbitreverse.ll45 ; MIPS32R2-NEXT: rotr $2, $1, 16
140 ; MIPS32R2-NEXT: rotr $3, $2, 16
163 ; MIPS32R2-NEXT: rotr $3, $1, 16
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-regress-interphase-shift.ll5 ; unselectable "rotr" node: (i32 (rotr i32, i64)).
/llvm-project-15.0.7/llvm/test/CodeGen/AVR/
H A Drot.ll54 %rotr = or i8 %parta, %partb
56 ret i8 %rotr
/llvm-project-15.0.7/llvm/unittests/ADT/
H A DAPIntTest.cpp296 EXPECT_EQ(one, one.rotr(0)); in TEST()
297 EXPECT_EQ(one, one.rotr(1)); in TEST()
1489 EXPECT_EQ(APInt(8, 16), APInt(8, 16).rotr(0)); in TEST()
1490 EXPECT_EQ(APInt(8, 8), APInt(8, 16).rotr(1)); in TEST()
1491 EXPECT_EQ(APInt(8, 4), APInt(8, 16).rotr(2)); in TEST()
1492 EXPECT_EQ(APInt(8, 1), APInt(8, 16).rotr(4)); in TEST()
1493 EXPECT_EQ(APInt(8, 16), APInt(8, 16).rotr(8)); in TEST()
1495 EXPECT_EQ(APInt(8, 1), APInt(8, 1).rotr(0)); in TEST()
1496 EXPECT_EQ(APInt(8, 128), APInt(8, 1).rotr(1)); in TEST()
1527 EXPECT_EQ(Rot, Big.rotr(144)); in TEST()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInteger.td70 defm ROTR : BinaryInt<rotr, "rotr", 0x78, 0x8a>;
106 def : Pat<(rotr I32:$lhs, (and I32:$rhs, 31)), (ROTR_I32 I32:$lhs, I32:$rhs)>;
108 def : Pat<(rotr I64:$lhs, (and I64:$rhs, 63)), (ROTR_I64 I64:$lhs, I64:$rhs)>;
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dpostlegalizercombiner-rotate.mir32 name: rotr
42 ; CHECK-LABEL: name: rotr
/llvm-project-15.0.7/llvm/test/CodeGen/WebAssembly/
H A Di64.ll244 ; CHECK-LABEL: rotr:
245 ; CHECK-NEXT: .functype rotr (i64, i64) -> (i64){{$}}
248 ; CHECK-NEXT: i64.rotr $push0=, $pop[[L0]], $pop[[L1]]
250 define i64 @rotr(i64 %x, i64 %y) {
262 ; CHECK-NEXT: i64.rotr $push0=, $pop[[L0]], $pop[[L1]]
H A Di32.ll244 ; CHECK-LABEL: rotr:
245 ; CHECK-NEXT: .functype rotr (i32, i32) -> (i32){{$}}
248 ; CHECK-NEXT: i32.rotr $push0=, $pop[[L0]], $pop[[L1]]
250 define i32 @rotr(i32 %x, i32 %y) {
262 ; CHECK-NEXT: i32.rotr $push0=, $pop[[L0]], $pop[[L1]]
/llvm-project-15.0.7/llvm/test/MC/Mips/micromips/
H A Dinvalid.s42 rotr $2, -1 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
43 rotr $2, 32 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
44 rotr $2, $3, -1 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
45 rotr $2, $3, 32 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate

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