Searched refs:regclasses (Results 1 – 13 of 13) sorted by relevance
59 for (const TargetRegisterClass *RC : TRI->regclasses()) in ResourcePriorityQueue()359 for (const TargetRegisterClass *RC : TRI->regclasses()) in regPressureDelta()363 for (const TargetRegisterClass *RC : TRI->regclasses()) { in regPressureDelta()
1780 for (const TargetRegisterClass *RC : TRI->regclasses()) in RegReductionPQBase()2089 for (const TargetRegisterClass *RC : TRI->regclasses()) { in dumpRegPressure()
5239 for (const TargetRegisterClass *RC : RI->regclasses()) { in getRegForInlineAsmConstraint()
219 for (const TargetRegisterClass* RC : regclasses()) { in getMinimalPhysRegClass()237 for (const TargetRegisterClass *RC : regclasses()) { in getMinimalPhysRegClassLLT()265 for (const TargetRegisterClass *C : regclasses()) in getAllocatableSet()
186 for (const TargetRegisterClass *C : TRI->regclasses()) { in computePSetLimit()
498 for (const TargetRegisterClass *RC : TRI->regclasses()) { in isForwardableRegClassCopy()514 for (const TargetRegisterClass *RC : TRI->regclasses()) { in isForwardableRegClassCopy()
33 for (const TargetRegisterClass *RC : TRI.regclasses()) { in PhysicalRegisterInfo()
4 # Skip folding a REG_SEQUENCE to its user when the regclasses for the user operands can't be
533 iterator_range<regclass_iterator> regclasses() const { in regclasses() function
740 iterator_range<regclass_iterator> regclasses() const { in regclasses() function
224 for (const TargetRegisterClass *RC : TRI.regclasses()) { in HexagonBlockRanges()
737 for (const TargetRegisterClass *RC : TRI.regclasses()) { in MLocTracker()1227 for (const auto *TRCI : TRI->regclasses()) in transferDebugInstrRef()
581 // FIXME: This could be better modeled by looking at the regclasses of the operands.