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/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dfast-isel-pic.ll22 ; ARMv7: movw [[reg2:r[0-9]+]],
23 ; ARMv7: movt [[reg2]],
24 ; ARMv7: add [[reg2]], pc, [[reg2]]
26 ; ARMv7-ELF: ldr r[[reg2:[0-9]+]],
28 ; ARMv7-ELF-NEXT: ldr r[[reg2]], [pc, r[[reg2]]]
29 ; ARMv7-ELF: ldr r[[reg2]], [r[[reg2]]]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dmax-literals.ll6 …e amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) {
12 %4 = extractelement <4 x float> %reg2, i32 0
35 … amdgpu_vs void @main2(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) {
41 %4 = extractelement <4 x float> %reg2, i32 0
H A Dpv-packing.ll4 …main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg …
28 %3 = extractelement <4 x float> %reg2, i32 0
29 %4 = extractelement <4 x float> %reg2, i32 1
30 %5 = extractelement <4 x float> %reg2, i32 2
H A Dload-input-fold.ll3 …main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg …
9 %4 = extractelement <4 x float> %reg2, i32 0
10 %5 = extractelement <4 x float> %reg2, i32 1
11 %6 = extractelement <4 x float> %reg2, i32 2
12 %7 = extractelement <4 x float> %reg2, i32 3
H A Dshared-op-cycle.ll4 …e amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) {
22 %w2 = extractelement <4 x float> %reg2, i32 3
H A Dpv.ll5 …main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg …
11 %tmp16 = extractelement <4 x float> %reg2, i32 0
12 %tmp17 = extractelement <4 x float> %reg2, i32 1
13 %tmp18 = extractelement <4 x float> %reg2, i32 2
14 %tmp19 = extractelement <4 x float> %reg2, i32 3
H A Dbig_alu.ll5 …main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg …
29 %tmp22 = extractelement <4 x float> %reg2, i32 0
30 %tmp23 = extractelement <4 x float> %reg2, i32 1
31 %tmp24 = extractelement <4 x float> %reg2, i32 2
32 %tmp25 = extractelement <4 x float> %reg2, i32 3
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/micromips-sizereduction/
H A Dmicromips-xor16.ll9 %reg2 = xor i32 %reg1, -1
12 %bool2 = icmp eq i32 %bool1.ext, %reg2
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Davoid_complex_am.ll4 ; On X86, reg1 + 1*reg2 has the same cost as reg1 + 8*reg2.
H A Dfma-do-not-commute.ll2 ; Check that the 2nd and 3rd arguments of fmaXXX231 reg1, reg2, mem3 are not commuted.
/llvm-project-15.0.7/llvm/test/MC/MachO/
H A Dbad-macro.s5 .macro test_macro reg1, reg2 argument
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64PBQPRegAlloc.cpp149 bool haveSameParity(unsigned reg1, unsigned reg2) { in haveSameParity() argument
151 assert(isFPReg(reg2) && "Expecting an FP register for reg2"); in haveSameParity()
153 return isOdd(reg1) == isOdd(reg2); in haveSameParity()
/llvm-project-15.0.7/libunwind/src/
H A DDwarfParser.hpp451 uint64_t reg2; in parseFDEInstructions() local
536 reg2 = addressSpace.getULEB128(p, instructionsEnd); in parseFDEInstructions()
542 if (reg2 > kMaxRegisterNumber) { in parseFDEInstructions()
547 results->setRegister(reg, kRegisterInRegister, (int64_t)reg2, in parseFDEInstructions()
550 "DW_CFA_register(reg=%" PRIu64 ", reg2=%" PRIu64 ")\n", reg, reg2); in parseFDEInstructions()
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dselect-select.mir452 ; CHECK-NEXT: %reg2:gpr32 = COPY $w2
454 ; CHECK-NEXT: %select:gpr32 = CSNEGWr %t, %reg2, 1, implicit $nzcv
461 %reg2:gpr(s32) = COPY $w2
462 %sub:gpr(s32) = G_SUB %zero(s32), %reg2
698 ; CHECK-NEXT: %reg2:gpr32 = COPY $w2
701 ; CHECK-NEXT: %select:gpr32 = CSNEGWr %xor, %reg2, 1, implicit $nzcv
706 %reg2:gpr(s32) = COPY $w2
711 %sub:gpr(s32) = G_SUB %zero(s32), %reg2
/llvm-project-15.0.7/llvm/test/CodeGen/VE/Scalar/
H A Dloadrri.ll8 ;;; 1. LD1BSXrri with %reg1 + %reg2
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrFMA.td172 // FMA*132* reg1, reg2, reg3; // reg1 * reg3 + reg2;
174 // FMA*231* reg2, reg1, reg3; // reg1 * reg3 + reg2;
/llvm-project-15.0.7/llvm/include/llvm/BinaryFormat/
H A DDwarf.def754 HANDLE_DW_OP(0x52, reg2, 2, DWARF)
/llvm-project-15.0.7/llvm/docs/
H A DLangRef.rst5795 DW_OP_stack_value)`` used with the list ``(%reg1, %reg2)`` would evaluate to
5796 ``%reg1 - reg2``. This list of values should be provided by the containing