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/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dselect-select.mir81 %reg0:gpr(s32) = COPY $w0
109 %reg0:gpr(s32) = COPY $w0
137 %reg0:gpr(s32) = COPY $w0
166 %reg0:gpr(s32) = COPY $w0
195 %reg0:gpr(s32) = COPY $w0
224 %reg0:gpr(s32) = COPY $w0
253 %reg0:gpr(s32) = COPY $w0
281 %reg0:gpr(s32) = COPY $w0
308 %reg0:gpr(s32) = COPY $w0
336 %reg0:gpr(s64) = COPY $x0
[all …]
H A Dselect-cmp.mir141 %reg0:gpr(s32) = COPY $w0
164 %reg0:gpr(s64) = COPY $x0
182 ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
188 %reg0:gpr(s32) = COPY $w0
206 ; CHECK-NEXT: %reg0:gpr32 = COPY $w0
212 %reg0:gpr(s32) = COPY $w0
214 %ext:gpr(s64) = G_ZEXT %reg0(s32)
242 %reg0:gpr(s16) = COPY $h0
244 %ext:gpr(s32) = G_ZEXT %reg0(s16)
274 %reg0:gpr(s32) = COPY $w0
[all …]
H A Dpostlegalizercombiner-mulpow2.mir17 ; CHECK: %reg0:_(s64) = COPY $x0
20 ; CHECK: %mul:_(s64) = nsw G_MUL %reg0, %cst
24 %reg0:_(s64) = COPY $x0
28 %mul:_(s64) = nsw G_MUL %reg0, %cst
H A Dpostlegalizer-lowering-swap-compare-operands.mir61 ; LOWER: %reg0:_(s64) = COPY $x0
69 ; SELECT: %reg0:gpr64 = COPY $x0
76 %reg0:_(s64) = COPY $x0
600 ; LOWER: %reg0:_(s64) = COPY $x0
614 ; SELECT: %reg0:gpr64 = COPY $x0
626 %reg0:_(s64) = COPY $x0
653 ; LOWER: %reg0:_(s64) = COPY $x0
666 ; SELECT: %reg0:gpr64 = COPY $x0
674 %reg0:_(s64) = COPY $x0
704 ; LOWER: %reg0:_(s64) = COPY $x0
[all …]
H A Dspeculative-hardening-brcond.mir70 ; CHECK: %reg0:fpr32 = COPY $s0
72 ; CHECK: FCMPSrr %reg0, %reg1, implicit-def $nzcv
80 %reg0:fpr(s32) = COPY $s0
82 %cmp:gpr(s32) = G_FCMP floatpred(oeq), %reg0, %reg1
H A Dselect-ptr-add.mir100 ; CHECK: %reg0:gpr32 = COPY $w0
103 ; CHECK: %ptr_add:gpr64sp = ADDXrx [[COPY]], %reg0, 18
105 %reg0:gpr(s32) = COPY $w0
107 %ext:gpr(s64) = G_ZEXT %reg0(s32)
H A Dpostlegalizer-lowering-adjust-icmp-imm.mir656 ; LOWER-NEXT: %reg0:_(s32) = COPY $w0
660 ; LOWER-NEXT: %select:_(s32) = G_SELECT %cmp(s32), %reg0, %reg1
666 ; SELECT-NEXT: %reg0:gpr32common = COPY $w0
672 %reg0:_(s32) = COPY $w0
675 %cmp:_(s32) = G_ICMP intpred(sle), %reg0(s32), %cst
676 %select:_(s32) = G_SELECT %cmp, %reg0, %reg1
694 ; LOWER-NEXT: %reg0:gpr(s64) = COPY $x0
696 ; LOWER-NEXT: %and:gpr(s64) = G_AND %reg0, %bit
704 ; SELECT-NEXT: %reg0:gpr64 = COPY $x0
709 %reg0:gpr(s64) = COPY $x0
[all …]
H A Dselect-uaddo.mir155 ; CHECK-NEXT: %reg0:gpr64sp = COPY $x0
157 ; CHECK-NEXT: %add:gpr64 = ADDSXrx %reg0, %reg1, 18, implicit-def $nzcv
161 %reg0:gpr(s64) = COPY $x0
166 %add:gpr(s64), %flags:gpr(s32) = G_UADDO %reg0, %shift
H A Dselect-saddo.mir155 ; CHECK-NEXT: %reg0:gpr64sp = COPY $x0
157 ; CHECK-NEXT: %add:gpr64 = ADDSXrx %reg0, %reg1, 18, implicit-def $nzcv
161 %reg0:gpr(s64) = COPY $x0
166 %add:gpr(s64), %flags:gpr(s32) = G_SADDO %reg0, %shift
H A Dselect-ssubo.mir155 ; CHECK-NEXT: %reg0:gpr64sp = COPY $x0
157 ; CHECK-NEXT: %add:gpr64 = SUBSXrx %reg0, %reg1, 18, implicit-def $nzcv
161 %reg0:gpr(s64) = COPY $x0
166 %add:gpr(s64), %flags:gpr(s32) = G_SSUBO %reg0, %shift
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A D2010-05-12-FastAllocKills.ll10 ; %reg1025 = MUL_Fp80m32 %reg1024, %rip, 1, %reg0, %const.0, %reg0; mem:LD4[ConstantPool]
19 ; %fp0 = LD_Fp80m %stack.3, 1, %reg0, 0, %reg0; mem:LD10[FixedStack3](align=4)
21 ; %fp2 = MUL_Fp80m32 %fp1, %rip, 1, %reg0, %const.0, %reg0; mem:LD4[ConstantPool]
23 ; ST_FpP80m %stack.3, 1, %reg0, 0, %reg0, killed %fp0; mem:ST10[FixedStack3](align=4)
24 ; ST_FpP80m %stack.4, 1, %reg0, 0, %reg0, killed %fp1; mem:ST10[FixedStack4](align=4)
25 ; ST_FpP80m %stack.5, 1, %reg0, 0, %reg0, killed %fp2; mem:ST10[FixedStack5](align=4)
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A D2011-11-29-128bitArithmetics.ll32 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
33 ; CHECK: movt [[reg0]], :upper16:{{.*}}
64 ; CHECK: movt [[reg0]], :upper16:{{.*}}
95 ; CHECK: movt [[reg0]], :upper16:{{.*}}
126 ; CHECK: movt [[reg0]], :upper16:{{.*}}
157 ; CHECK: movt [[reg0]], :upper16:{{.*}}
188 ; CHECK: movt [[reg0]], :upper16:{{.*}}
220 ; CHECK: movt [[reg0]], :upper16:{{.*}}
254 ; CHECK: movt [[reg0]], :upper16:{{.*}}
277 ; CHECK: movt [[reg0]], :upper16:{{.*}}
[all …]
H A Dfast-isel-pic.ll11 ; THUMB: movw [[reg0:r[0-9]+]],
12 ; THUMB: movt [[reg0]],
13 ; THUMB: add [[reg0]], pc
15 ; THUMB-ELF: ldr r[[reg0:[0-9]+]],
16 ; THUMB-ELF: add r[[reg0]], pc
17 ; THUMB-ELF: ldr r[[reg0]], [r[[reg0]]]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dtex-clause-antidep.ll6 define amdgpu_vs void @test(<4 x float> inreg %reg0) {
7 %1 = extractelement <4 x float> %reg0, i32 0
8 %2 = extractelement <4 x float> %reg0, i32 1
9 %3 = extractelement <4 x float> %reg0, i32 2
10 %4 = extractelement <4 x float> %reg0, i32 3
H A Dtexture-input-merge.ll5 define amdgpu_vs void @test(<4 x float> inreg %reg0) {
6 %1 = extractelement <4 x float> %reg0, i32 0
7 %2 = extractelement <4 x float> %reg0, i32 1
8 %3 = extractelement <4 x float> %reg0, i32 2
9 %4 = extractelement <4 x float> %reg0, i32 3
H A Dfmad.ll5 define amdgpu_ps void @test(<4 x float> inreg %reg0) {
6 %r0 = extractelement <4 x float> %reg0, i32 0
7 %r1 = extractelement <4 x float> %reg0, i32 1
8 %r2 = extractelement <4 x float> %reg0, i32 2
H A Dllvm.pow.ll8 define amdgpu_ps void @test1(<4 x float> inreg %reg0) {
9 %r0 = extractelement <4 x float> %reg0, i32 0
10 %r1 = extractelement <4 x float> %reg0, i32 1
30 define amdgpu_ps void @test2(<4 x float> inreg %reg0, <4 x float> inreg %reg1) {
31 %vec = call <4 x float> @llvm.pow.v4f32( <4 x float> %reg0, <4 x float> %reg1)
H A Dfmin.ll5 define amdgpu_ps void @test(<4 x float> inreg %reg0) {
6 %r0 = extractelement <4 x float> %reg0, i32 0
7 %r1 = extractelement <4 x float> %reg0, i32 1
H A Dfmax.ll5 define amdgpu_ps void @test(<4 x float> inreg %reg0) {
6 %r0 = extractelement <4 x float> %reg0, i32 0
7 %r1 = extractelement <4 x float> %reg0, i32 1
H A Dr600-encoding.ll13 define amdgpu_ps void @test(<4 x float> inreg %reg0) {
15 %r0 = extractelement <4 x float> %reg0, i32 0
16 %r1 = extractelement <4 x float> %reg0, i32 1
H A Dfloor.ll4 define amdgpu_ps void @test(<4 x float> inreg %reg0) {
5 %r0 = extractelement <4 x float> %reg0, i32 0
H A Dcomplex-folding.ll5 define amdgpu_ps void @main(<4 x float> inreg %reg0) {
7 %0 = extractelement <4 x float> %reg0, i32 0
H A Dinput-mods.ll12 define amdgpu_ps void @test(<4 x float> inreg %reg0) {
13 %r0 = extractelement <4 x float> %reg0, i32 0
/llvm-project-15.0.7/clang/test/CodeGen/
H A Daarch64-inline-asm.c59 register unsigned long reg0 asm("r0") = 0; in test_gcc_registers()
67 asm volatile("hvc #0" : : "r" (reg0), "r" (reg1)); in test_gcc_registers()
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dirtranslator-readnone-intrinsic-callsite.ll11 %reg0 = call i32 @llvm.amdgcn.s.getreg(i32 0)
12 store volatile i32 %reg0, i32 addrspace(1)* undef

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