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/llvm-project-15.0.7/llvm/test/CodeGen/MSP430/
H A DBranchSelector.ll5 @reg = common global i16 0, align 2
12 store volatile i16 11, i16* @reg, align 2
13 store volatile i16 13, i16* @reg, align 2
14 store volatile i16 17, i16* @reg, align 2
15 store volatile i16 11, i16* @reg, align 2
16 store volatile i16 13, i16* @reg, align 2
17 store volatile i16 17, i16* @reg, align 2
18 store volatile i16 11, i16* @reg, align 2
19 store volatile i16 13, i16* @reg, align 2
20 store volatile i16 17, i16* @reg, align 2
[all …]
/llvm-project-15.0.7/compiler-rt/lib/asan/
H A Dasan_rtl_x86_64.S9 #define NAME(n, reg, op, s, i) n##_##op##_##i##_##s##_##reg argument
11 #define FNAME(reg, op, s, i) NAME(__asan_check, reg, op, s, i) argument
12 #define RLABEL(reg, op, s, i) NAME(.return, reg, op, s, i) argument
13 #define CLABEL(reg, op, s, i) NAME(.check, reg, op, s, i) argument
14 #define FLABEL(reg, op, s, i) NAME(.fail, reg, op, s, i) argument
22 FNAME(reg, op, s, i): ;\
33 RLABEL(reg, op, s, add): ;\
37 CLABEL(reg, op, 1, i): ;\
48 CLABEL(reg, op, 2, i): ;\
60 CLABEL(reg, op, 4, i): ;\
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dirtranslator-amdgpu_kernel-system-sgprs.ll6 ; HSA-NEXT: - { reg: '$vgpr0', virtual-reg: '%1' }
7 ; HSA-NEXT: - { reg: '$sgpr4', virtual-reg: '%2' }
8 ; HSA-NEXT: - { reg: '$sgpr5', virtual-reg: '%3' }
18 ; HSA-NEXT: - { reg: '$vgpr0', virtual-reg: '%1' }
19 ; HSA-NEXT: - { reg: '$sgpr4', virtual-reg: '%2' }
20 ; HSA-NEXT: - { reg: '$sgpr5', virtual-reg: '%3' }
31 ; HSA-NEXT: - { reg: '$vgpr0', virtual-reg: '%1' }
32 ; HSA-NEXT: - { reg: '$sgpr4', virtual-reg: '%2' }
33 ; HSA-NEXT: - { reg: '$sgpr5', virtual-reg: '%3' }
34 ; HSA-NEXT: - { reg: '$sgpr6', virtual-reg: '%4' }
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/MIR/AMDGPU/
H A Dmachine-function-info-no-ir.mir30 # FULL-NEXT: workGroupIDX: { reg: '$sgpr6' }
31 # FULL-NEXT: workGroupIDY: { reg: '$sgpr13' }
32 # FULL-NEXT: workGroupIDZ: { reg: '$sgpr14' }
33 # FULL-NEXT: LDSKernelId: { reg: '$sgpr15' }
36 # FULL-NEXT: workItemIDX: { reg: '$vgpr0' }
68 # SIMPLE-NEXT: workGroupIDX: { reg: '$sgpr6' }
74 # SIMPLE-NEXT: workItemIDX: { reg: '$vgpr0' }
94 kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }
95 workGroupIDX: { reg: '$sgpr6' }
97 workItemIDX: { reg: '$vgpr0' }
[all …]
/llvm-project-15.0.7/libunwind/src/
H A DDwarfParser.hpp102 initialState.savedRegisters[reg] = savedRegisters[reg]; in checkSaveRegister()
124 savedRegisters[reg] = initialState.savedRegisters[reg]; in restoreRegisterToInitialState()
450 uint64_t reg; in parseFDEInstructions() local
633 reg, results->savedRegisters[reg].value, length); in parseFDEInstructions()
677 reg); in parseFDEInstructions()
759 for (reg = UNW_SPARC_O0; reg <= UNW_SPARC_O7; reg++) { in parseFDEInstructions()
765 for (reg = UNW_SPARC_L0; reg <= UNW_SPARC_I7; reg++) { in parseFDEInstructions()
779 for (reg = UNW_SPARC_L0; reg <= UNW_SPARC_I7; reg++) { in parseFDEInstructions()
805 reg = operand; in parseFDEInstructions()
824 reg = operand; in parseFDEInstructions()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dstore-prepostinc.mir50 - { reg: '$r0', virtual-reg: '' }
51 - { reg: '$r1', virtual-reg: '' }
71 - { reg: '$r0', virtual-reg: '' }
72 - { reg: '$r1', virtual-reg: '' }
93 - { reg: '$r0', virtual-reg: '' }
94 - { reg: '$r1', virtual-reg: '' }
115 - { reg: '$r0', virtual-reg: '' }
116 - { reg: '$r1', virtual-reg: '' }
137 - { reg: '$r0', virtual-reg: '' }
138 - { reg: '$r1', virtual-reg: '' }
[all …]
/llvm-project-15.0.7/lldb/source/Plugins/Process/Utility/
H A DRegisterContextPOSIX_arm64.cpp28 bool RegisterContextPOSIX_arm64::IsGPR(unsigned reg) { in IsGPR() argument
35 bool RegisterContextPOSIX_arm64::IsFPR(unsigned reg) { in IsFPR() argument
42 bool RegisterContextPOSIX_arm64::IsSVE(unsigned reg) const { in IsSVE()
43 return m_register_info_up->IsSVEReg(reg); in IsSVE()
46 bool RegisterContextPOSIX_arm64::IsPAuth(unsigned reg) const { in IsPAuth()
47 return m_register_info_up->IsPAuthReg(reg); in IsPAuth()
67 return m_register_info_up->GetRegisterInfo()[reg].byte_size; in GetRegisterSize()
88 if (reg < GetRegisterCount()) in GetRegisterInfoAtIndex()
89 return &GetRegisterInfo()[reg]; in GetRegisterInfoAtIndex()
104 if (reg < GetRegisterCount()) in GetRegisterName()
[all …]
H A DRegisterContextPOSIX_ppc64le.cpp98 bool RegisterContextPOSIX_ppc64le::IsGPR(unsigned reg) { in IsGPR() argument
102 bool RegisterContextPOSIX_ppc64le::IsFPR(unsigned reg) { in IsFPR() argument
103 return (reg >= k_first_fpr_ppc64le) && (reg <= k_last_fpr_ppc64le); in IsFPR()
106 bool RegisterContextPOSIX_ppc64le::IsVMX(unsigned reg) { in IsVMX() argument
107 return (reg >= k_first_vmx_ppc64le) && (reg <= k_last_vmx_ppc64le); in IsVMX()
111 return (reg >= k_first_vsx_ppc64le) && (reg <= k_last_vsx_ppc64le); in IsVSX()
125 return GetRegisterInfo()[reg].byte_offset; in GetRegisterOffset()
130 return GetRegisterInfo()[reg].byte_size; in GetRegisterSize()
151 if (reg < k_num_registers_ppc64le) in GetRegisterInfoAtIndex()
152 return &GetRegisterInfo()[reg]; in GetRegisterInfoAtIndex()
[all …]
H A DRegisterContextPOSIX_powerpc.cpp79 bool RegisterContextPOSIX_powerpc::IsGPR(unsigned reg) { in IsGPR() argument
80 return (reg <= k_last_gpr_powerpc); // GPR's come first. in IsGPR()
83 bool RegisterContextPOSIX_powerpc::IsFPR(unsigned reg) { in IsFPR() argument
84 return (reg >= k_first_fpr) && (reg <= k_last_fpr); in IsFPR()
87 bool RegisterContextPOSIX_powerpc::IsVMX(unsigned reg) { in IsVMX() argument
88 return (reg >= k_first_vmx) && (reg <= k_last_vmx); in IsVMX()
106 return GetRegisterInfo()[reg].byte_offset; in GetRegisterOffset()
111 return GetRegisterInfo()[reg].byte_size; in GetRegisterSize()
132 if (reg < k_num_registers_powerpc) in GetRegisterInfoAtIndex()
133 return &GetRegisterInfo()[reg]; in GetRegisterInfoAtIndex()
[all …]
H A DRegisterContextPOSIX_arm64.h33 virtual unsigned GetRegisterSize(unsigned reg);
35 virtual unsigned GetRegisterOffset(unsigned reg);
43 const char *GetRegisterName(unsigned reg);
50 bool IsGPR(unsigned reg);
52 bool IsFPR(unsigned reg);
56 bool IsSVE(unsigned reg) const;
57 bool IsPAuth(unsigned reg) const;
59 bool IsSVEZ(unsigned reg) const { return m_register_info_up->IsSVEZReg(reg); } in IsSVEZ() argument
60 bool IsSVEP(unsigned reg) const { return m_register_info_up->IsSVEPReg(reg); } in IsSVEP() argument
61 bool IsSVEVG(unsigned reg) const { in IsSVEVG() argument
[all …]
H A DRegisterContextPOSIX_arm.cpp28 bool RegisterContextPOSIX_arm::IsGPR(unsigned reg) { in IsGPR() argument
29 if (m_register_info_up->GetRegisterSetFromRegisterIndex(reg) == in IsGPR()
35 bool RegisterContextPOSIX_arm::IsFPR(unsigned reg) { in IsFPR() argument
36 if (m_register_info_up->GetRegisterSetFromRegisterIndex(reg) == in IsFPR()
55 return m_register_info_up->GetRegisterInfo()[reg].byte_offset; in GetRegisterOffset()
59 return m_register_info_up->GetRegisterInfo()[reg].byte_size; in GetRegisterSize()
78 RegisterContextPOSIX_arm::GetRegisterInfoAtIndex(size_t reg) { in GetRegisterInfoAtIndex() argument
79 if (reg < GetRegisterCount()) in GetRegisterInfoAtIndex()
80 return &GetRegisterInfo()[reg]; in GetRegisterInfoAtIndex()
95 if (reg < GetRegisterCount()) in GetRegisterName()
[all …]
H A DRegisterContextPOSIX_mips64.cpp29 bool RegisterContextPOSIX_mips64::IsGPR(unsigned reg) { in IsGPR() argument
33 bool RegisterContextPOSIX_mips64::IsFPR(unsigned reg) { in IsFPR() argument
36 return reg < (m_registers_count[fpr_registers_count] in IsFPR()
68 assert(reg < m_num_registers && "Invalid register number."); in GetRegisterOffset()
69 return GetRegisterInfo()[reg].byte_offset; in GetRegisterOffset()
73 assert(reg < m_num_registers && "Invalid register number."); in GetRegisterSize()
74 return GetRegisterInfo()[reg].byte_size; in GetRegisterSize()
94 if (reg < m_num_registers) in GetRegisterInfoAtIndex()
95 return &GetRegisterInfo()[reg]; in GetRegisterInfoAtIndex()
124 assert(reg < m_num_registers && "Invalid register offset."); in GetRegisterName()
[all …]
H A DRegisterContextPOSIX_s390x.cpp72 bool RegisterContextPOSIX_s390x::IsGPR(unsigned reg) { in IsGPR() argument
73 return reg <= m_reg_info.last_gpr; // GPRs come first. in IsGPR()
76 bool RegisterContextPOSIX_s390x::IsFPR(unsigned reg) { in IsFPR() argument
77 return (m_reg_info.first_fpr <= reg && reg <= m_reg_info.last_fpr); in IsFPR()
112 RegisterContextPOSIX_s390x::GetRegisterInfoAtIndex(size_t reg) { in GetRegisterInfoAtIndex() argument
113 if (reg < m_reg_info.num_registers) in GetRegisterInfoAtIndex()
114 return &GetRegisterInfo()[reg]; in GetRegisterInfoAtIndex()
125 return GetRegisterInfo()[reg].byte_offset; in GetRegisterOffset()
128 unsigned RegisterContextPOSIX_s390x::GetRegisterSize(unsigned reg) { in GetRegisterSize() argument
130 return GetRegisterInfo()[reg].byte_size; in GetRegisterSize()
[all …]
/llvm-project-15.0.7/lldb/source/Target/
H A DDynamicRegisterInfo.cpp392 assert(reg.name); in SetRegisterInfo()
393 assert(reg.set_name); in SetRegisterInfo()
405 reg.name.AsCString(), reg.alt_name.AsCString(), reg.byte_size, in SetRegisterInfo()
406 reg.byte_offset, reg.encoding, reg.format, in SetRegisterInfo()
407 {reg.regnum_ehframe, reg.regnum_dwarf, reg.regnum_generic, in SetRegisterInfo()
542 if ((strcmp(reg.name, "pc") == 0) || (strcmp(reg.name, "r15") == 0)) in Finalize()
565 if ((strcmp(reg.name, "eip") == 0) || (strcmp(reg.name, "pc") == 0)) in Finalize()
581 if ((strcmp(reg.name, "rip") == 0) || (strcmp(reg.name, "pc") == 0)) in Finalize()
642 for (auto &reg : m_regs) { in ConfigureOffsets() local
652 reg.byte_offset = in ConfigureOffsets()
[all …]
H A DRegisterContext.cpp69 for (uint32_t reg = start_idx; reg < num_registers; ++reg) { in GetRegisterInfoByName() local
115 bool success = WriteRegisterFromUnsigned(reg, pc); in SetPC()
155 return ReadRegisterAsUnsigned(reg, fail_value); in GetSP()
161 return WriteRegisterFromUnsigned(reg, sp); in SetSP()
167 return ReadRegisterAsUnsigned(reg, fail_value); in GetFP()
173 return WriteRegisterFromUnsigned(reg, fp); in SetFP()
179 return ReadRegisterAsUnsigned(reg, fail_value); in GetReturnAddress()
185 return ReadRegisterAsUnsigned(reg, fail_value); in GetFlags()
190 if (reg != LLDB_INVALID_REGNUM) in ReadRegisterAsUnsigned()
206 if (reg == LLDB_INVALID_REGNUM) in WriteRegisterFromUnsigned()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dselect-with-no-legality-check.mir15 - { reg: '$d0', virtual-reg: '%1' }
41 - { reg: '$d0', virtual-reg: '%0' }
42 - { reg: '$d1', virtual-reg: '%1' }
70 - { reg: '$d0', virtual-reg: '%0' }
71 - { reg: '$d1', virtual-reg: '%1' }
99 - { reg: '$q0', virtual-reg: '%0' }
100 - { reg: '$d0', virtual-reg: '%1' }
128 - { reg: '$q0', virtual-reg: '%0' }
129 - { reg: '$d0', virtual-reg: '%1' }
157 - { reg: '$q0', virtual-reg: '%0' }
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-ptest-removal-cmpeq.mir17 - { reg: '$p0', virtual-reg: '%0' }
18 - { reg: '$z0', virtual-reg: '%1' }
19 - { reg: '$z1', virtual-reg: '%2' }
58 - { reg: '$p0', virtual-reg: '%0' }
59 - { reg: '$z0', virtual-reg: '%1' }
60 - { reg: '$z1', virtual-reg: '%2' }
94 - { reg: '$p0', virtual-reg: '%0' }
95 - { reg: '$z0', virtual-reg: '%1' }
96 - { reg: '$z1', virtual-reg: '%2' }
130 - { reg: '$p0', virtual-reg: '%0' }
[all …]
H A Dmachine-combiner-instr-fmf.mir21 - { reg: '$s0', virtual-reg: '%0' }
22 - { reg: '$s1', virtual-reg: '%1' }
23 - { reg: '$s2', virtual-reg: '%2' }
61 - { reg: '$s0', virtual-reg: '%0' }
62 - { reg: '$s1', virtual-reg: '%1' }
63 - { reg: '$s2', virtual-reg: '%2' }
101 - { reg: '$s0', virtual-reg: '%0' }
102 - { reg: '$s1', virtual-reg: '%1' }
103 - { reg: '$s2', virtual-reg: '%2' }
141 - { reg: '$s0', virtual-reg: '%0' }
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dframe-lowering-entry-all-sgpr-used.mir15 - { reg: '$vgpr0' }
16 - { reg: '$vgpr1' }
17 - { reg: '$vgpr2' }
18 - { reg: '$sgpr4_sgpr5' }
19 - { reg: '$sgpr6_sgpr7' }
20 - { reg: '$sgpr8' }
21 - { reg: '$sgpr9' }
35 workGroupIDX: { reg: '$sgpr8' }
36 workGroupIDY: { reg: '$sgpr9' }
38 workItemIDX: { reg: '$vgpr0' }
[all …]
H A Dbranch-relax-spill.ll356 ; CHECK-NEXT: ; reg use s0
359 ; CHECK-NEXT: ; reg use s1
362 ; CHECK-NEXT: ; reg use s2
365 ; CHECK-NEXT: ; reg use s3
368 ; CHECK-NEXT: ; reg use s4
371 ; CHECK-NEXT: ; reg use s5
374 ; CHECK-NEXT: ; reg use s6
377 ; CHECK-NEXT: ; reg use s7
380 ; CHECK-NEXT: ; reg use s8
383 ; CHECK-NEXT: ; reg use s9
[all …]
H A Dno-remat-indirect-mov.mir11 - { reg: '$vgpr0', virtual-reg: '%0' }
12 - { reg: '$vgpr1', virtual-reg: '%1' }
13 - { reg: '$vgpr2', virtual-reg: '%2' }
14 - { reg: '$vgpr3', virtual-reg: '%3' }
15 - { reg: '$vgpr4', virtual-reg: '%4' }
16 - { reg: '$vgpr5', virtual-reg: '%5' }
17 - { reg: '$vgpr6', virtual-reg: '%6' }
18 - { reg: '$vgpr7', virtual-reg: '%7' }
19 - { reg: '$vgpr8', virtual-reg: '%8' }
20 - { reg: '$vgpr9', virtual-reg: '%9' }
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Daix-cc-byval-split.ll24 ; CHECK32: - { reg: '$r3', virtual-reg: '' }
25 ; CHECK32: - { reg: '$r4', virtual-reg: '' }
26 ; CHECK32: - { reg: '$r5', virtual-reg: '' }
27 ; CHECK32: - { reg: '$r6', virtual-reg: '' }
28 ; CHECK32: - { reg: '$r7', virtual-reg: '' }
29 ; CHECK32: - { reg: '$r8', virtual-reg: '' }
30 ; CHECK32: - { reg: '$r9', virtual-reg: '' }
31 ; CHECK32: - { reg: '$r10', virtual-reg: '' }
56 ; CHECK64: - { reg: '$x3', virtual-reg: '' }
57 ; CHECK64: - { reg: '$x4', virtual-reg: '' }
[all …]
/llvm-project-15.0.7/compiler-rt/lib/sanitizer_common/
H A Dsanitizer_asm.h26 # define CFI_REL_OFFSET(reg, n) .cfi_rel_offset reg, n argument
27 # define CFI_OFFSET(reg, n) .cfi_offset reg, n argument
28 # define CFI_DEF_CFA_REGISTER(reg) .cfi_def_cfa_register reg argument
29 # define CFI_DEF_CFA(reg, n) .cfi_def_cfa reg, n argument
30 # define CFI_RESTORE(reg) .cfi_restore reg argument
38 # define CFI_REL_OFFSET(reg, n) argument
39 # define CFI_OFFSET(reg, n) argument
40 # define CFI_DEF_CFA_REGISTER(reg) argument
41 # define CFI_DEF_CFA(reg, n) argument
42 # define CFI_RESTORE(reg) argument
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dstore-prepostinc.mir36 - { reg: '$r0', virtual-reg: '' }
37 - { reg: '$r1', virtual-reg: '' }
56 - { reg: '$r0', virtual-reg: '' }
57 - { reg: '$r1', virtual-reg: '' }
77 - { reg: '$r0', virtual-reg: '' }
78 - { reg: '$r1', virtual-reg: '' }
98 - { reg: '$r0', virtual-reg: '' }
99 - { reg: '$r1', virtual-reg: '' }
119 - { reg: '$r0', virtual-reg: '' }
120 - { reg: '$r1', virtual-reg: '' }
[all …]
/llvm-project-15.0.7/llvm/test/tools/llvm-reduce/mir/
H A Dpreserve-machine-function-info-amdgpu.mir38 # RESULT-NEXT: workGroupIDX: { reg: '$sgpr20' }
39 # RESULT-NEXT: workGroupIDY: { reg: '$sgpr19' }
40 # RESULT-NEXT: workGroupIDZ: { reg: '$sgpr18' }
41 # RESULT-NEXT: LDSKernelId: { reg: '$sgpr15' }
89 dispatchPtr: { reg: '$sgpr6_sgpr7' }
90 queuePtr: { reg: '$sgpr4_sgpr5' }
91 dispatchID: { reg: '$sgpr12_sgpr13' }
92 workGroupIDX: { reg: '$sgpr20' }
93 workGroupIDY: { reg: '$sgpr19' }
94 workGroupIDZ: { reg: '$sgpr18' }
[all …]

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