180814287SRaphael Isemann //===-- RegisterContextPOSIX_ppc64le.cpp ----------------------------------===//
2fd2c8d65SPavel Labath //
32946cd70SChandler Carruth // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
42946cd70SChandler Carruth // See https://llvm.org/LICENSE.txt for license information.
52946cd70SChandler Carruth // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6fd2c8d65SPavel Labath //
7fd2c8d65SPavel Labath //===----------------------------------------------------------------------===//
8fd2c8d65SPavel Labath
9*76e47d48SRaphael Isemann #include <cerrno>
10*76e47d48SRaphael Isemann #include <cstdint>
11fd2c8d65SPavel Labath #include <cstring>
12fd2c8d65SPavel Labath
131a05affaSJames Y Knight #include "lldb/Target/Process.h"
14fd2c8d65SPavel Labath #include "lldb/Target/Target.h"
15fd2c8d65SPavel Labath #include "lldb/Target/Thread.h"
16fd2c8d65SPavel Labath #include "lldb/Utility/DataBufferHeap.h"
17fd2c8d65SPavel Labath #include "lldb/Utility/DataExtractor.h"
18fd2c8d65SPavel Labath #include "lldb/Utility/Endian.h"
19d821c997SPavel Labath #include "lldb/Utility/RegisterValue.h"
20d821c997SPavel Labath #include "lldb/Utility/Scalar.h"
21fd2c8d65SPavel Labath #include "llvm/Support/Compiler.h"
22fd2c8d65SPavel Labath
23fd2c8d65SPavel Labath #include "RegisterContextPOSIX_ppc64le.h"
24fd2c8d65SPavel Labath
25fd2c8d65SPavel Labath using namespace lldb_private;
26fd2c8d65SPavel Labath using namespace lldb;
27fd2c8d65SPavel Labath
28fd2c8d65SPavel Labath static const uint32_t g_gpr_regnums[] = {
29fd2c8d65SPavel Labath gpr_r0_ppc64le, gpr_r1_ppc64le, gpr_r2_ppc64le, gpr_r3_ppc64le,
30fd2c8d65SPavel Labath gpr_r4_ppc64le, gpr_r5_ppc64le, gpr_r6_ppc64le, gpr_r7_ppc64le,
31fd2c8d65SPavel Labath gpr_r8_ppc64le, gpr_r9_ppc64le, gpr_r10_ppc64le, gpr_r11_ppc64le,
32fd2c8d65SPavel Labath gpr_r12_ppc64le, gpr_r13_ppc64le, gpr_r14_ppc64le, gpr_r15_ppc64le,
33fd2c8d65SPavel Labath gpr_r16_ppc64le, gpr_r17_ppc64le, gpr_r18_ppc64le, gpr_r19_ppc64le,
34fd2c8d65SPavel Labath gpr_r20_ppc64le, gpr_r21_ppc64le, gpr_r22_ppc64le, gpr_r23_ppc64le,
35fd2c8d65SPavel Labath gpr_r24_ppc64le, gpr_r25_ppc64le, gpr_r26_ppc64le, gpr_r27_ppc64le,
36fd2c8d65SPavel Labath gpr_r28_ppc64le, gpr_r29_ppc64le, gpr_r30_ppc64le, gpr_r31_ppc64le,
37fd2c8d65SPavel Labath gpr_pc_ppc64le, gpr_msr_ppc64le, gpr_origr3_ppc64le, gpr_ctr_ppc64le,
38fd2c8d65SPavel Labath gpr_lr_ppc64le, gpr_xer_ppc64le, gpr_cr_ppc64le, gpr_softe_ppc64le,
39fd2c8d65SPavel Labath gpr_trap_ppc64le,
40fd2c8d65SPavel Labath };
41fd2c8d65SPavel Labath
42fd2c8d65SPavel Labath static const uint32_t g_fpr_regnums[] = {
43fd2c8d65SPavel Labath fpr_f0_ppc64le, fpr_f1_ppc64le, fpr_f2_ppc64le, fpr_f3_ppc64le,
44fd2c8d65SPavel Labath fpr_f4_ppc64le, fpr_f5_ppc64le, fpr_f6_ppc64le, fpr_f7_ppc64le,
45fd2c8d65SPavel Labath fpr_f8_ppc64le, fpr_f9_ppc64le, fpr_f10_ppc64le, fpr_f11_ppc64le,
46fd2c8d65SPavel Labath fpr_f12_ppc64le, fpr_f13_ppc64le, fpr_f14_ppc64le, fpr_f15_ppc64le,
47fd2c8d65SPavel Labath fpr_f16_ppc64le, fpr_f17_ppc64le, fpr_f18_ppc64le, fpr_f19_ppc64le,
48fd2c8d65SPavel Labath fpr_f20_ppc64le, fpr_f21_ppc64le, fpr_f22_ppc64le, fpr_f23_ppc64le,
49fd2c8d65SPavel Labath fpr_f24_ppc64le, fpr_f25_ppc64le, fpr_f26_ppc64le, fpr_f27_ppc64le,
50fd2c8d65SPavel Labath fpr_f28_ppc64le, fpr_f29_ppc64le, fpr_f30_ppc64le, fpr_f31_ppc64le,
51fd2c8d65SPavel Labath fpr_fpscr_ppc64le,
52fd2c8d65SPavel Labath };
53fd2c8d65SPavel Labath
54fd2c8d65SPavel Labath static const uint32_t g_vmx_regnums[] = {
55fd2c8d65SPavel Labath vmx_vr0_ppc64le, vmx_vr1_ppc64le, vmx_vr2_ppc64le, vmx_vr3_ppc64le,
56fd2c8d65SPavel Labath vmx_vr4_ppc64le, vmx_vr5_ppc64le, vmx_vr6_ppc64le, vmx_vr7_ppc64le,
57fd2c8d65SPavel Labath vmx_vr8_ppc64le, vmx_vr9_ppc64le, vmx_vr10_ppc64le, vmx_vr11_ppc64le,
58fd2c8d65SPavel Labath vmx_vr12_ppc64le, vmx_vr13_ppc64le, vmx_vr14_ppc64le, vmx_vr15_ppc64le,
59fd2c8d65SPavel Labath vmx_vr16_ppc64le, vmx_vr17_ppc64le, vmx_vr18_ppc64le, vmx_vr19_ppc64le,
60fd2c8d65SPavel Labath vmx_vr20_ppc64le, vmx_vr21_ppc64le, vmx_vr22_ppc64le, vmx_vr23_ppc64le,
61fd2c8d65SPavel Labath vmx_vr24_ppc64le, vmx_vr25_ppc64le, vmx_vr26_ppc64le, vmx_vr27_ppc64le,
62fd2c8d65SPavel Labath vmx_vr28_ppc64le, vmx_vr29_ppc64le, vmx_vr30_ppc64le, vmx_vr31_ppc64le,
63fd2c8d65SPavel Labath vmx_vscr_ppc64le, vmx_vrsave_ppc64le,
64fd2c8d65SPavel Labath };
65fd2c8d65SPavel Labath
66fd2c8d65SPavel Labath static const uint32_t g_vsx_regnums[] = {
67fd2c8d65SPavel Labath vsx_vs0_ppc64le, vsx_vs1_ppc64le, vsx_vs2_ppc64le, vsx_vs3_ppc64le,
68fd2c8d65SPavel Labath vsx_vs4_ppc64le, vsx_vs5_ppc64le, vsx_vs6_ppc64le, vsx_vs7_ppc64le,
69fd2c8d65SPavel Labath vsx_vs8_ppc64le, vsx_vs9_ppc64le, vsx_vs10_ppc64le, vsx_vs11_ppc64le,
70fd2c8d65SPavel Labath vsx_vs12_ppc64le, vsx_vs13_ppc64le, vsx_vs14_ppc64le, vsx_vs15_ppc64le,
71fd2c8d65SPavel Labath vsx_vs16_ppc64le, vsx_vs17_ppc64le, vsx_vs18_ppc64le, vsx_vs19_ppc64le,
72fd2c8d65SPavel Labath vsx_vs20_ppc64le, vsx_vs21_ppc64le, vsx_vs22_ppc64le, vsx_vs23_ppc64le,
73fd2c8d65SPavel Labath vsx_vs24_ppc64le, vsx_vs25_ppc64le, vsx_vs26_ppc64le, vsx_vs27_ppc64le,
74fd2c8d65SPavel Labath vsx_vs28_ppc64le, vsx_vs29_ppc64le, vsx_vs30_ppc64le, vsx_vs31_ppc64le,
75fd2c8d65SPavel Labath vsx_vs32_ppc64le, vsx_vs33_ppc64le, vsx_vs34_ppc64le, vsx_vs35_ppc64le,
76fd2c8d65SPavel Labath vsx_vs36_ppc64le, vsx_vs37_ppc64le, vsx_vs38_ppc64le, vsx_vs39_ppc64le,
77fd2c8d65SPavel Labath vsx_vs40_ppc64le, vsx_vs41_ppc64le, vsx_vs42_ppc64le, vsx_vs43_ppc64le,
78fd2c8d65SPavel Labath vsx_vs44_ppc64le, vsx_vs45_ppc64le, vsx_vs46_ppc64le, vsx_vs47_ppc64le,
79fd2c8d65SPavel Labath vsx_vs48_ppc64le, vsx_vs49_ppc64le, vsx_vs50_ppc64le, vsx_vs51_ppc64le,
80fd2c8d65SPavel Labath vsx_vs52_ppc64le, vsx_vs53_ppc64le, vsx_vs54_ppc64le, vsx_vs55_ppc64le,
81fd2c8d65SPavel Labath vsx_vs56_ppc64le, vsx_vs57_ppc64le, vsx_vs58_ppc64le, vsx_vs59_ppc64le,
82fd2c8d65SPavel Labath vsx_vs60_ppc64le, vsx_vs61_ppc64le, vsx_vs62_ppc64le, vsx_vs63_ppc64le,
83fd2c8d65SPavel Labath };
84fd2c8d65SPavel Labath
85fd2c8d65SPavel Labath // Number of register sets provided by this context.
86fd2c8d65SPavel Labath enum { k_num_register_sets = 4 };
87fd2c8d65SPavel Labath
88fd2c8d65SPavel Labath static const RegisterSet g_reg_sets_ppc64le[k_num_register_sets] = {
89fd2c8d65SPavel Labath {"General Purpose Registers", "gpr", k_num_gpr_registers_ppc64le,
90fd2c8d65SPavel Labath g_gpr_regnums},
91fd2c8d65SPavel Labath {"Floating Point Registers", "fpr", k_num_fpr_registers_ppc64le,
92fd2c8d65SPavel Labath g_fpr_regnums},
93fd2c8d65SPavel Labath {"Altivec/VMX Registers", "vmx", k_num_vmx_registers_ppc64le,
94fd2c8d65SPavel Labath g_vmx_regnums},
95fd2c8d65SPavel Labath {"VSX Registers", "vsx", k_num_vsx_registers_ppc64le, g_vsx_regnums},
96fd2c8d65SPavel Labath };
97fd2c8d65SPavel Labath
IsGPR(unsigned reg)98fd2c8d65SPavel Labath bool RegisterContextPOSIX_ppc64le::IsGPR(unsigned reg) {
99fd2c8d65SPavel Labath return (reg <= k_last_gpr_ppc64le); // GPR's come first.
100fd2c8d65SPavel Labath }
101fd2c8d65SPavel Labath
IsFPR(unsigned reg)102fd2c8d65SPavel Labath bool RegisterContextPOSIX_ppc64le::IsFPR(unsigned reg) {
103fd2c8d65SPavel Labath return (reg >= k_first_fpr_ppc64le) && (reg <= k_last_fpr_ppc64le);
104fd2c8d65SPavel Labath }
105fd2c8d65SPavel Labath
IsVMX(unsigned reg)106fd2c8d65SPavel Labath bool RegisterContextPOSIX_ppc64le::IsVMX(unsigned reg) {
107fd2c8d65SPavel Labath return (reg >= k_first_vmx_ppc64le) && (reg <= k_last_vmx_ppc64le);
108fd2c8d65SPavel Labath }
109fd2c8d65SPavel Labath
IsVSX(unsigned reg)110fd2c8d65SPavel Labath bool RegisterContextPOSIX_ppc64le::IsVSX(unsigned reg) {
111fd2c8d65SPavel Labath return (reg >= k_first_vsx_ppc64le) && (reg <= k_last_vsx_ppc64le);
112fd2c8d65SPavel Labath }
113fd2c8d65SPavel Labath
RegisterContextPOSIX_ppc64le(Thread & thread,uint32_t concrete_frame_idx,RegisterInfoInterface * register_info)114fd2c8d65SPavel Labath RegisterContextPOSIX_ppc64le::RegisterContextPOSIX_ppc64le(
115fd2c8d65SPavel Labath Thread &thread, uint32_t concrete_frame_idx,
116fd2c8d65SPavel Labath RegisterInfoInterface *register_info)
117fd2c8d65SPavel Labath : RegisterContext(thread, concrete_frame_idx) {
118d5b44036SJonas Devlieghere m_register_info_up.reset(register_info);
119fd2c8d65SPavel Labath }
120fd2c8d65SPavel Labath
InvalidateAllRegisters()121fd2c8d65SPavel Labath void RegisterContextPOSIX_ppc64le::InvalidateAllRegisters() {}
122fd2c8d65SPavel Labath
GetRegisterOffset(unsigned reg)123fd2c8d65SPavel Labath unsigned RegisterContextPOSIX_ppc64le::GetRegisterOffset(unsigned reg) {
124fd2c8d65SPavel Labath assert(reg < k_num_registers_ppc64le && "Invalid register number.");
125fd2c8d65SPavel Labath return GetRegisterInfo()[reg].byte_offset;
126fd2c8d65SPavel Labath }
127fd2c8d65SPavel Labath
GetRegisterSize(unsigned reg)128fd2c8d65SPavel Labath unsigned RegisterContextPOSIX_ppc64le::GetRegisterSize(unsigned reg) {
129fd2c8d65SPavel Labath assert(reg < k_num_registers_ppc64le && "Invalid register number.");
130fd2c8d65SPavel Labath return GetRegisterInfo()[reg].byte_size;
131fd2c8d65SPavel Labath }
132fd2c8d65SPavel Labath
GetRegisterCount()133fd2c8d65SPavel Labath size_t RegisterContextPOSIX_ppc64le::GetRegisterCount() {
134fd2c8d65SPavel Labath size_t num_registers = k_num_registers_ppc64le;
135fd2c8d65SPavel Labath return num_registers;
136fd2c8d65SPavel Labath }
137fd2c8d65SPavel Labath
GetGPRSize()138fd2c8d65SPavel Labath size_t RegisterContextPOSIX_ppc64le::GetGPRSize() {
139d5b44036SJonas Devlieghere return m_register_info_up->GetGPRSize();
140fd2c8d65SPavel Labath }
141fd2c8d65SPavel Labath
GetRegisterInfo()142fd2c8d65SPavel Labath const RegisterInfo *RegisterContextPOSIX_ppc64le::GetRegisterInfo() {
143fd2c8d65SPavel Labath // Commonly, this method is overridden and g_register_infos is copied and
14405097246SAdrian Prantl // specialized. So, use GetRegisterInfo() rather than g_register_infos in
14505097246SAdrian Prantl // this scope.
146d5b44036SJonas Devlieghere return m_register_info_up->GetRegisterInfo();
147fd2c8d65SPavel Labath }
148fd2c8d65SPavel Labath
149fd2c8d65SPavel Labath const RegisterInfo *
GetRegisterInfoAtIndex(size_t reg)150fd2c8d65SPavel Labath RegisterContextPOSIX_ppc64le::GetRegisterInfoAtIndex(size_t reg) {
151fd2c8d65SPavel Labath if (reg < k_num_registers_ppc64le)
152fd2c8d65SPavel Labath return &GetRegisterInfo()[reg];
153fd2c8d65SPavel Labath else
154248a1305SKonrad Kleine return nullptr;
155fd2c8d65SPavel Labath }
156fd2c8d65SPavel Labath
GetRegisterSetCount()157fd2c8d65SPavel Labath size_t RegisterContextPOSIX_ppc64le::GetRegisterSetCount() {
158fd2c8d65SPavel Labath size_t sets = 0;
159fd2c8d65SPavel Labath for (size_t set = 0; set < k_num_register_sets; ++set) {
160fd2c8d65SPavel Labath if (IsRegisterSetAvailable(set))
161fd2c8d65SPavel Labath ++sets;
162fd2c8d65SPavel Labath }
163fd2c8d65SPavel Labath
164fd2c8d65SPavel Labath return sets;
165fd2c8d65SPavel Labath }
166fd2c8d65SPavel Labath
GetRegisterSet(size_t set)167fd2c8d65SPavel Labath const RegisterSet *RegisterContextPOSIX_ppc64le::GetRegisterSet(size_t set) {
168fd2c8d65SPavel Labath if (IsRegisterSetAvailable(set))
169fd2c8d65SPavel Labath return &g_reg_sets_ppc64le[set];
170fd2c8d65SPavel Labath else
171248a1305SKonrad Kleine return nullptr;
172fd2c8d65SPavel Labath }
173fd2c8d65SPavel Labath
GetRegisterName(unsigned reg)174fd2c8d65SPavel Labath const char *RegisterContextPOSIX_ppc64le::GetRegisterName(unsigned reg) {
175fd2c8d65SPavel Labath assert(reg < k_num_registers_ppc64le && "Invalid register offset.");
176fd2c8d65SPavel Labath return GetRegisterInfo()[reg].name;
177fd2c8d65SPavel Labath }
178fd2c8d65SPavel Labath
IsRegisterSetAvailable(size_t set_index)179fd2c8d65SPavel Labath bool RegisterContextPOSIX_ppc64le::IsRegisterSetAvailable(size_t set_index) {
180fd2c8d65SPavel Labath size_t num_sets = k_num_register_sets;
181fd2c8d65SPavel Labath
182fd2c8d65SPavel Labath return (set_index < num_sets);
183fd2c8d65SPavel Labath }
184