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/llvm-project-15.0.7/llvm/test/CodeGen/Mips/llvm-ir/
H A Dand.ll36 ; MIPS-NEXT: jr $ra
52 ; MIPS64-NEXT: jr $ra
85 ; MIPS-NEXT: jr $ra
101 ; MIPS64-NEXT: jr $ra
134 ; MIPS-NEXT: jr $ra
183 ; MIPS-NEXT: jr $ra
230 ; MIPS-NEXT: jr $ra
288 ; MIPS-NEXT: jr $ra
363 ; MIPS-NEXT: jr $ra
408 ; MIPS-NEXT: jr $ra
[all …]
H A Dor.ll23 ; GP32-NEXT: jr $ra
29 ; GP64-NEXT: jr $ra
36 ; MM32-NEXT: jrc $ra
50 ; GP32-NEXT: jr $ra
56 ; GP64-NEXT: jr $ra
77 ; GP32-NEXT: jr $ra
83 ; GP64-NEXT: jr $ra
104 ; GP32-NEXT: jr $ra
109 ; GP64-NEXT: jr $ra
131 ; GP32-NEXT: jr $ra
[all …]
H A Dxor.ll34 ; MIPS-NEXT: jr $ra
50 ; MIPS64-NEXT: jr $ra
83 ; MIPS-NEXT: jr $ra
99 ; MIPS64-NEXT: jr $ra
132 ; MIPS-NEXT: jr $ra
181 ; MIPS-NEXT: jr $ra
228 ; MIPS-NEXT: jr $ra
286 ; MIPS-NEXT: jr $ra
361 ; MIPS-NEXT: jr $ra
406 ; MIPS-NEXT: jr $ra
[all …]
H A Dret.ll24 ; turned into jic 0, $ra.
31 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
42 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
52 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
62 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
72 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
82 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
92 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
103 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
118 ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
[all …]
H A Dnan-fp-attr.ll34 ; MIPS32R1-NEXT: jr $ra
39 ; MIPS32R2-NEXT: jr $ra
49 ; MIPS32R6-NEXT: jr $ra
79 ; MM-NEXT: jr $ra
90 ; MMR6-NEXT: jrc $ra
167 ; MM-NEXT: jrc $ra
177 ; MMR6-NEXT: jrc $ra
231 ; MM-NEXT: jr $ra
242 ; MMR6-NEXT: jrc $ra
310 ; MM-NEXT: jr $ra
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/
H A Dmemory-offsets.s9 …lw $31, ($29) # CHECK: lw $ra, 0($sp) # encoding: [0x8f,0xbf,0x00,0x00]
10 …lw $31, 0($29) # CHECK: lw $ra, 0($sp) # encoding: [0x8f,0xbf,0x00,0x00]
11 …lw $31, (8)($29) # CHECK: lw $ra, 8($sp) # encoding: [0x8f,0xbf,0x00,0x08]
12 …lw $31, 3 + (4 * 8)($29) # CHECK: lw $ra, 35($sp) # encoding: [0x8f,0xbf,0x00,0x23]
13 …lw $31, (8 + 8)($29) # CHECK: lw $ra, 16($sp) # encoding: [0x8f,0xbf,0x00,0x10]
14 …lw $31, (8 << 4)($29) # CHECK: lw $ra, 128($sp) # encoding: [0x8f,0xbf,0x00,0x80]
15 …lw $31, (32768 >> 2)($29) # CHECK: lw $ra, 8192($sp) # encoding: [0x8f,0xbf,0x20,0x00]
16 …lw $31, 32768 >> 2($29) # CHECK: lw $ra, 8192($sp) # encoding: [0x8f,0xbf,0x20,0x00]
17 …lw $31, 2 << 3($29) # CHECK: lw $ra, 16($sp) # encoding: [0x8f,0xbf,0x00,0x10]
30 … # CHECK: addu $ra, $ra, $sp # encoding: [0x03,0xfd,0xf8,0x21]
[all …]
H A Dmicromips-loadstore-instructions.s44 # CHECK-EL: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x12,0x45]
46 # CHECK-EL: swm16 $16, $17, $ra, 8($sp) # encoding: [0x52,0x45]
48 # CHECK-EL: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x12,0x45]
150 lwm16 $16, $17, $ra, 8($sp)
151 swm16 $16, $17, $ra, 8($sp)
152 lwm $16, $17, $ra, 8($sp)
153 lwm $16, $17, $ra, 64($sp)
154 lwm $16, $17, $ra, 8($4)
156 swm $16, $17, $ra, 8($sp)
157 swm $16, $17, $ra, 64($sp)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/LoongArch/ir-instruction/
H A Dsext-zext-trunc.ll11 ; LA32-NEXT: jirl $zero, $ra, 0
17 ; LA64-NEXT: jirl $zero, $ra, 0
27 ; LA32-NEXT: jirl $zero, $ra, 0
33 ; LA64-NEXT: jirl $zero, $ra, 0
43 ; LA32-NEXT: jirl $zero, $ra, 0
49 ; LA64-NEXT: jirl $zero, $ra, 0
60 ; LA32-NEXT: jirl $zero, $ra, 0
66 ; LA64-NEXT: jirl $zero, $ra, 0
75 ; LA32-NEXT: jirl $zero, $ra, 0
80 ; LA64-NEXT: jirl $zero, $ra, 0
[all …]
H A Dcall.ll10 ; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
14 ; LA32-NEXT: jirl $zero, $ra, 0
23 ; LA64-NEXT: jirl $zero, $ra, 0
32 ; LA32-NEXT: jirl $zero, $ra, 0
37 ; LA64-NEXT: jirl $zero, $ra, 0
50 ; LA32-NEXT: jirl $zero, $ra, 0
59 ; LA64-NEXT: jirl $zero, $ra, 0
71 ; LA32-NEXT: jirl $ra, $a2, 0
74 ; LA32-NEXT: jirl $zero, $ra, 0
82 ; LA64-NEXT: jirl $ra, $a2, 0
[all …]
H A Dor.ll10 ; LA32-NEXT: jirl $zero, $ra, 0
15 ; LA64-NEXT: jirl $zero, $ra, 0
25 ; LA32-NEXT: jirl $zero, $ra, 0
30 ; LA64-NEXT: jirl $zero, $ra, 0
40 ; LA32-NEXT: jirl $zero, $ra, 0
45 ; LA64-NEXT: jirl $zero, $ra, 0
55 ; LA32-NEXT: jirl $zero, $ra, 0
60 ; LA64-NEXT: jirl $zero, $ra, 0
71 ; LA32-NEXT: jirl $zero, $ra, 0
76 ; LA64-NEXT: jirl $zero, $ra, 0
[all …]
H A Dxor.ll10 ; LA32-NEXT: jirl $zero, $ra, 0
15 ; LA64-NEXT: jirl $zero, $ra, 0
25 ; LA32-NEXT: jirl $zero, $ra, 0
30 ; LA64-NEXT: jirl $zero, $ra, 0
40 ; LA32-NEXT: jirl $zero, $ra, 0
45 ; LA64-NEXT: jirl $zero, $ra, 0
55 ; LA32-NEXT: jirl $zero, $ra, 0
60 ; LA64-NEXT: jirl $zero, $ra, 0
71 ; LA32-NEXT: jirl $zero, $ra, 0
76 ; LA64-NEXT: jirl $zero, $ra, 0
[all …]
H A Dsdiv-udiv-srem-urem.ll14 ; LA32-NEXT: jirl $zero, $ra, 0
18 ; LA64-NEXT: jirl $zero, $ra, 0
38 ; LA32-NEXT: jirl $zero, $ra, 0
45 ; LA64-NEXT: jirl $zero, $ra, 0
75 ; LA32-NEXT: jirl $zero, $ra, 0
82 ; LA64-NEXT: jirl $zero, $ra, 0
110 ; LA32-NEXT: jirl $zero, $ra, 0
117 ; LA64-NEXT: jirl $zero, $ra, 0
149 ; LA32-NEXT: jirl $zero, $ra, 0
154 ; LA64-NEXT: jirl $zero, $ra, 0
[all …]
H A Dfloat-convert.ll12 ; LA32F-NEXT: jirl $zero, $ra, 0
18 ; LA32D-NEXT: jirl $zero, $ra, 0
24 ; LA64F-NEXT: jirl $zero, $ra, 0
30 ; LA64D-NEXT: jirl $zero, $ra, 0
40 ; LA32F-NEXT: jirl $zero, $ra, 0
46 ; LA32D-NEXT: jirl $zero, $ra, 0
52 ; LA64F-NEXT: jirl $zero, $ra, 0
58 ; LA64D-NEXT: jirl $zero, $ra, 0
68 ; LA32F-NEXT: jirl $zero, $ra, 0
74 ; LA32D-NEXT: jirl $zero, $ra, 0
[all …]
H A Dand.ll10 ; LA32-NEXT: jirl $zero, $ra, 0
15 ; LA64-NEXT: jirl $zero, $ra, 0
25 ; LA32-NEXT: jirl $zero, $ra, 0
30 ; LA64-NEXT: jirl $zero, $ra, 0
40 ; LA32-NEXT: jirl $zero, $ra, 0
45 ; LA64-NEXT: jirl $zero, $ra, 0
55 ; LA32-NEXT: jirl $zero, $ra, 0
60 ; LA64-NEXT: jirl $zero, $ra, 0
71 ; LA32-NEXT: jirl $zero, $ra, 0
76 ; LA64-NEXT: jirl $zero, $ra, 0
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dbittest.ll37 ; MIPS-NEXT: jr $ra
57 ; MIPS64-NEXT: jr $ra
77 ; MM32R3-NEXT: jr $ra
95 ; MIPS-NEXT: jr $ra
115 ; MIPS64-NEXT: jr $ra
154 ; MIPS-NEXT: jr $ra
213 ; MIPS-NEXT: jr $ra
272 ; MIPS-NEXT: jr $ra
335 ; MIPS-NEXT: jr $ra
399 ; MIPS-NEXT: jr $ra
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Ddouble-intrinsics.ll24 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
26 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
33 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
35 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
57 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
67 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
69 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
76 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
79 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
119 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
[all …]
H A Dfloat-intrinsics.ll35 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
37 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
44 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
46 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
59 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
68 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
78 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
87 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
90 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
130 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
[all …]
H A Ddouble-intrinsics-strict.ll26 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
28 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
35 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
37 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
59 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
69 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
78 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
81 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
112 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
121 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
[all …]
H A Dfloat-intrinsics-strict.ll26 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
28 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
35 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
37 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
50 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
59 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
69 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
78 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
81 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
121 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
[all …]
H A Dstack-realignment.ll16 ; RV32I-NEXT: .cfi_offset ra, -4
35 ; RV64I-NEXT: .cfi_offset ra, -8
58 ; RV32I-NEXT: .cfi_offset ra, -4
70 ; RV64I-NEXT: .cfi_offset ra, -8
88 ; RV32I-NEXT: .cfi_offset ra, -4
107 ; RV64I-NEXT: .cfi_offset ra, -8
130 ; RV32I-NEXT: .cfi_offset ra, -4
142 ; RV64I-NEXT: .cfi_offset ra, -8
160 ; RV32I-NEXT: .cfi_offset ra, -4
179 ; RV64I-NEXT: .cfi_offset ra, -8
[all …]
H A Datomic-load-store.ll15 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
18 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
30 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
33 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
49 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
52 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
64 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
67 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
83 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
99 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/micromips-sizereduction/
H A Dmicromips-movep.mir23 liveins: $ra
33 ; CHECK: $ra = LWSP_MM $sp, 20 :: (load (s32) from %stack.0)
35 ; CHECK: PseudoReturn undef $ra, implicit $v0, implicit $v1
38 SW killed $ra, $sp, 20 :: (store (s32) into %stack.0)
44 $ra = LW $sp, 20 :: (load (s32) from %stack.0)
46 PseudoReturn undef $ra, implicit $v0, implicit $v1
58 liveins: $ra
70 ; CHECK: PseudoReturn undef $ra, implicit $v0, implicit $v1
73 SW killed $ra, $sp, 20 :: (store (s32) into %stack.0)
79 $ra = LW $sp, 20 :: (load (s32) from %stack.0)
[all …]
/llvm-project-15.0.7/lld/test/ELF/
H A Driscv-relax-call.s47 # NORVC-NEXT: jal ra, 0x10420
61 # NORVC-NEXT: jalr ra, -6(ra)
63 # NORVC-NEXT: jalr ra, -14(ra)
87 # RVC-NEXT: c.jr ra
104 # RVC32-NEXT: jalr ra, -4(ra)
106 # RVC64-NEXT: jalr ra, -4(ra)
108 # RVC64-NEXT: jalr ra, -12(ra)
116 # NORELAX-NEXT: 10010: auipc ra, 0
117 # NORELAX-NEXT: jalr ra, 16(ra)
118 # NORELAX-NEXT: auipc ra, 0
[all …]
/llvm-project-15.0.7/llvm/test/MC/RISCV/
H A Dfunction-call.s12 # INSTR: auipc ra, 0
13 # INSTR: jalr ra
17 # INSTR: auipc ra, 0
18 # INSTR: jalr ra
25 # INSTR: auipc ra, 0
26 # INSTR: jalr ra
32 # INSTR: jalr ra
35 call ra
38 # INSTR: jalr ra
44 # INSTR: jalr ra
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Darm-eabi.ll1 ; RUN: llc < %s -mtriple=arm-none-eabi -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EA…
2 ; RUN: llc < %s -mtriple=arm-none-eabihf -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-…
3 ; RUN: llc < %s -mtriple=arm-none-androideabi -disable-post-ra -o - | FileCheck %s --check-prefix=C…
4 ; RUN: llc < %s -mtriple=arm-none-gnueabi -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK…
5 ; RUN: llc < %s -mtriple=arm-none-gnueabihf -disable-post-ra -o - | FileCheck %s --check-prefix=CHE…
6 ; RUN: llc < %s -mtriple=arm-none-musleabi -disable-post-ra -o - | FileCheck %s --check-prefix=CHEC…
7 ; RUN: llc < %s -mtriple=arm-none-musleabihf -disable-post-ra -o - | FileCheck %s --check-prefix=CH…
8 ; RUN: llc < %s -mtriple=arm-none-eabi -meabi=gnu -disable-post-ra -o - | FileCheck %s --check-pref…
15 ; RUN: llc < %s -mtriple=arm-none-eabi -meabi=4 -disable-post-ra -o - | FileCheck %s --check-prefix…
16 ; RUN: llc < %s -mtriple=arm-none-eabihf -meabi=4 -disable-post-ra -o - | FileCheck %s --check-pref…
[all …]

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