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/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dhtm.ll17 declare i32 @llvm.ppc.tbegin(i32) #1
29 declare i32 @llvm.ppc.tend(i32)
48 declare i32 @llvm.ppc.tabort(i32)
69 declare i32 @llvm.ppc.tendall()
70 declare i32 @llvm.ppc.tresume()
71 declare i32 @llvm.ppc.tsuspend()
72 declare i64 @llvm.ppc.ttest()
127 declare i64 @llvm.ppc.get.tfhar()
144 declare i32 @llvm.ppc.tcheck()
146 declare i32 @llvm.ppc.trechkpt()
[all …]
H A Dppc-passname.ll1 ; Test pass name: ppc-loop-instr-form-prep.
13 ; Test pass name: ppc-toc-reg-deps.
25 ; Test pass name: ppc-vsx-copy.
32 ; STOP-AFTER-VSX-COPY: -ppc-vsx-copy
37 ; Test pass name: ppc-early-ret.
44 ; STOP-AFTER-EARLY-RET: -ppc-early-ret
49 ; Test pass name: ppc-vsx-fma-mutate.
61 ; Test pass name: ppc-vsx-swaps.
68 ; STOP-AFTER-VSX-SWAPS: -ppc-vsx-swaps
73 ; Test pass name: ppc-reduce-cr-ops.
[all …]
H A Dp10-vector-mask-ops.ll3 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
6 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
9 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
15 declare i32 @llvm.ppc.altivec.vextractbm(<16 x i8>)
16 declare i32 @llvm.ppc.altivec.vextracthm(<8 x i16>)
17 declare i32 @llvm.ppc.altivec.vextractwm(<4 x i32>)
18 declare i32 @llvm.ppc.altivec.vextractdm(<2 x i64>)
19 declare i32 @llvm.ppc.altivec.vextractqm(<1 x i128>)
172 declare <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64)
173 declare <8 x i16> @llvm.ppc.altivec.mtvsrhm(i64)
[all …]
H A Dbuiltins-ppc-xlcompat-fnabs.ll3 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr8 < %s | \
6 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
9 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
12 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
15 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mattr=+vsx < %s | \
19 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr6 < %s | \
22 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr6 < %s | \
25 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr8 \
28 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr8 \
31 declare double @llvm.ppc.fnabs(double)
[all …]
H A Dbuiltins-ppc-p10permute.ll2 ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr10 \
5 ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr10 \
17 declare <16 x i8> @llvm.ppc.altivec.vsldbi(<16 x i8>, <16 x i8>, i32 immarg)
94 declare <16 x i8> @llvm.ppc.altivec.vinsblx(<16 x i8>, i32, i32)
105 declare <16 x i8> @llvm.ppc.altivec.vinsbrx(<16 x i8>, i32, i32)
116 declare <8 x i16> @llvm.ppc.altivec.vinshlx(<8 x i16>, i32, i32)
127 declare <8 x i16> @llvm.ppc.altivec.vinshrx(<8 x i16>, i32, i32)
138 declare <4 x i32> @llvm.ppc.altivec.vinswlx(<4 x i32>, i32, i32)
149 declare <4 x i32> @llvm.ppc.altivec.vinswrx(<4 x i32>, i32, i32)
160 declare <2 x i64> @llvm.ppc.altivec.vinsdlx(<2 x i64>, i64, i64)
[all …]
H A Dp10-bit-manip-ops.ll3 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
6 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
13 declare i64 @llvm.ppc.pdepd(i64, i64)
14 declare i64 @llvm.ppc.pextd(i64, i64)
16 declare i64 @llvm.ppc.cfuged(i64, i64)
17 declare i64 @llvm.ppc.altivec.vgnb(<1 x i128>, i32)
21 declare i64 @llvm.ppc.cntlzdm(i64, i64)
22 declare i64 @llvm.ppc.cnttzdm(i64, i64)
50 %tmp = tail call i64 @llvm.ppc.pdepd(i64 %a, i64 %b)
60 %tmp = tail call i64 @llvm.ppc.pextd(i64 %a, i64 %b)
[all …]
H A Dp10-string-ops.ll3 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
6 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
11 declare <16 x i8> @llvm.ppc.altivec.vclrlb(<16 x i8>, i32)
12 declare <16 x i8> @llvm.ppc.altivec.vclrrb(<16 x i8>, i32)
34 declare <16 x i8> @llvm.ppc.altivec.vstribr(<16 x i8>)
35 declare <16 x i8> @llvm.ppc.altivec.vstribl(<16 x i8>)
36 declare <8 x i16> @llvm.ppc.altivec.vstrihr(<8 x i16>)
37 declare <8 x i16> @llvm.ppc.altivec.vstrihl(<8 x i16>)
39 declare i32 @llvm.ppc.altivec.vstribr.p(i32, <16 x i8>)
40 declare i32 @llvm.ppc.altivec.vstribl.p(i32, <16 x i8>)
[all …]
H A Dbuiltins-ppc-xlcompat-trap.ll12 declare void @llvm.ppc.tw(i32 %a, i32 %b, i32 %c)
18 call void @llvm.ppc.tw(i32 %a, i32 %b, i32 1)
27 call void @llvm.ppc.tw(i32 %a, i32 %b, i32 2)
36 call void @llvm.ppc.tw(i32 %a, i32 %b, i32 3)
45 call void @llvm.ppc.tw(i32 %a, i32 %b, i32 4)
54 call void @llvm.ppc.tw(i32 %a, i32 %b, i32 5)
63 call void @llvm.ppc.tw(i32 %a, i32 %b, i32 6)
72 call void @llvm.ppc.tw(i32 %a, i32 %b, i32 8)
81 call void @llvm.ppc.tw(i32 %a, i32 %b, i32 12)
338 declare void @llvm.ppc.trap(i32 %a)
[all …]
H A Dbuiltins-ppc-p9-f128.ll2 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
11 %0 = call fp128 @llvm.ppc.sqrtf128.round.to.odd(fp128 %a)
18 declare fp128 @llvm.ppc.sqrtf128.round.to.odd(fp128)
54 declare fp128 @llvm.ppc.addf128.round.to.odd(fp128, fp128)
66 declare fp128 @llvm.ppc.subf128.round.to.odd(fp128, fp128)
79 declare fp128 @llvm.ppc.mulf128.round.to.odd(fp128, fp128)
90 declare fp128 @llvm.ppc.divf128.round.to.odd(fp128, fp128)
102 declare double @llvm.ppc.truncf128.round.to.odd(fp128)
121 declare fp128 @llvm.ppc.scalar.insert.exp.qp(fp128, i64)
127 %1 = call i64 @llvm.ppc.scalar.extract.expq(fp128 %0)
[all …]
H A Dvsx_builtins.ll4 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
8 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
12 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
16 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
20 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
24 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
28 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
32 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
46 declare <4 x i32> @llvm.ppc.vsx.lxvw4x.be(i8*)
59 declare <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8*)
[all …]
H A Dbuiltins-ppc-xlcompat-conversionfunc.ll11 declare double @llvm.ppc.fcfid(double %a)
17 %1 = call double @llvm.ppc.fcfid(double %a)
21 declare double @llvm.ppc.fcfud(double %a)
27 %1 = call double @llvm.ppc.fcfud(double %a)
31 declare double @llvm.ppc.fctid(double %a)
37 %1 = call double @llvm.ppc.fctid(double %a)
41 declare double @llvm.ppc.fctidz(double %a)
51 declare double @llvm.ppc.fctiw(double %a)
61 declare double @llvm.ppc.fctiwz(double %a)
71 declare double @llvm.ppc.fctudz(double %a)
[all …]
H A Dbuiltins-ppc-xlcompat-trap-64bit-only.ll16 call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 1)
25 call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 2)
34 call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 3)
42 call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 4)
51 call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 5)
60 call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 6)
69 call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 8)
78 call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 12)
213 call void @llvm.ppc.tdw(i64 %a, i64 0, i32 1)
335 declare void @llvm.ppc.trapd(i64 %a)
[all …]
H A Dbuiltins-ppc-xlcompat-sync-64.ll18 declare i64 @llvm.ppc.popcntb.i64.i64(i64)
28 call void @llvm.ppc.eieio()
31 declare void @llvm.ppc.eieio()
41 call void @llvm.ppc.iospace.eieio()
44 declare void @llvm.ppc.iospace.eieio()
52 call void @llvm.ppc.iospace.lwsync()
55 declare void @llvm.ppc.iospace.lwsync()
63 call void @llvm.ppc.iospace.sync()
66 declare void @llvm.ppc.iospace.sync()
77 call void @llvm.ppc.icbt(i8* %0)
[all …]
H A Dbuiltins-ppc-elf2-abi.ll143 %1 = call <4 x float> @llvm.ppc.vsx.xvresp(<4 x float> %0)
250 declare <4 x float> @llvm.ppc.vsx.xvresp(<4 x float>)
253 declare <2 x double> @llvm.ppc.vsx.xvredp(<2 x double>)
284 declare <4 x float> @llvm.ppc.vsx.xvcvdpsp(<2 x double>) #1
285 declare <4 x i32> @llvm.ppc.vsx.xvcvdpsxws(<2 x double>) #1
287 declare <2 x double> @llvm.ppc.vsx.xvcvsxwdp(<4 x i32>) #1
288 declare <2 x double> @llvm.ppc.vsx.xvcvuxwdp(<4 x i32>) #1
290 declare <4 x float> @llvm.ppc.vsx.xvcvsxdsp(<2 x i64>) #1
291 declare <4 x float> @llvm.ppc.vsx.xvcvuxdsp(<2 x i64>) #1
292 declare <2 x i64> @llvm.ppc.vsx.xvcvspsxds(<4 x float>) #1
[all …]
H A Dbuiltins-ppc-xlcompat-sync-32.ll3 ; RUN: --ppc-asm-full-reg-names -mcpu=pwr7 < %s | FileCheck %s
11 %popcntb = tail call i32 @llvm.ppc.popcntb.i32.i32(i32 %a)
14 declare i32 @llvm.ppc.popcntb.i32.i32(i32)
24 call void @llvm.ppc.eieio()
27 declare void @llvm.ppc.eieio()
37 call void @llvm.ppc.iospace.eieio()
40 declare void @llvm.ppc.iospace.eieio()
48 call void @llvm.ppc.iospace.lwsync()
51 declare void @llvm.ppc.iospace.lwsync()
59 call void @llvm.ppc.iospace.sync()
[all …]
H A Dp9-vector-sign-extend.ll3 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
8 declare <4 x i32> @llvm.ppc.altivec.vextsb2w(<16 x i8>) nounwind readnone
9 declare <2 x i64> @llvm.ppc.altivec.vextsb2d(<16 x i8>) nounwind readnone
10 declare <4 x i32> @llvm.ppc.altivec.vextsh2w(<8 x i16>) nounwind readnone
11 declare <2 x i64> @llvm.ppc.altivec.vextsh2d(<8 x i16>) nounwind readnone
12 declare <2 x i64> @llvm.ppc.altivec.vextsw2d(<4 x i32>) nounwind readnone
19 %tmp = tail call <4 x i32> @llvm.ppc.altivec.vextsb2w(<16 x i8> %x)
28 %tmp = tail call <2 x i64> @llvm.ppc.altivec.vextsb2d(<16 x i8> %x)
37 %tmp = tail call <4 x i32> @llvm.ppc.altivec.vextsh2w(<8 x i16> %x)
46 %tmp = tail call <2 x i64> @llvm.ppc.altivec.vextsh2d(<8 x i16> %x)
[all …]
H A Dbuiltins-ppc-p9-darn.ll12 %0 = call i64 @llvm.ppc.darnraw()
22 %0 = call i64 @llvm.ppc.darn()
33 %0 = call i32 @llvm.ppc.darn32()
45 ; OPT: call i64 @llvm.ppc.darnraw()
46 ; OPT-NEXT: call i64 @llvm.ppc.darn()
48 %0 = call i64 @llvm.ppc.darnraw()
49 %1 = call i64 @llvm.ppc.darn()
67 %1 = call i64 @llvm.ppc.darn()
83 declare i64 @llvm.ppc.darn()
84 declare i64 @llvm.ppc.darnraw()
[all …]
H A Dp9-vector-compares-and-counts.ll39 declare <16 x i8> @llvm.ppc.altivec.vcmpneb(<16 x i8>, <16 x i8>)
51 declare <16 x i8> @llvm.ppc.altivec.vcmpnezb(<16 x i8>, <16 x i8>)
63 declare <8 x i16> @llvm.ppc.altivec.vcmpneh(<8 x i16>, <8 x i16>)
87 declare <4 x i32> @llvm.ppc.altivec.vcmpnew(<4 x i32>, <4 x i32>)
152 %0 = tail call i32 @llvm.ppc.altivec.vclzlsbb(<16 x i8> %a)
158 declare i32 @llvm.ppc.altivec.vclzlsbb(<16 x i8>)
163 %0 = tail call i32 @llvm.ppc.altivec.vctzlsbb(<16 x i8> %a)
169 declare i32 @llvm.ppc.altivec.vctzlsbb(<16 x i8>)
180 declare <4 x i32> @llvm.ppc.altivec.vprtybw(<4 x i32>)
191 declare <2 x i64> @llvm.ppc.altivec.vprtybd(<2 x i64>)
[all …]
H A Dp10-vsx-pcv.ll3 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
8 declare <16 x i8> @llvm.ppc.vsx.xxgenpcvbm(<16 x i8>, i32)
9 declare <8 x i16> @llvm.ppc.vsx.xxgenpcvhm(<8 x i16>, i32)
10 declare <4 x i32> @llvm.ppc.vsx.xxgenpcvwm(<4 x i32>, i32)
11 declare <2 x i64> @llvm.ppc.vsx.xxgenpcvdm(<2 x i64>, i32)
19 %gen = tail call <16 x i8> @llvm.ppc.vsx.xxgenpcvbm(<16 x i8> %a, i32 1)
29 %gen = tail call <8 x i16> @llvm.ppc.vsx.xxgenpcvhm(<8 x i16> %a, i32 1)
39 %gen = tail call <4 x i32> @llvm.ppc.vsx.xxgenpcvwm(<4 x i32> %a, i32 1)
49 %gen = tail call <2 x i64> @llvm.ppc.vsx.xxgenpcvdm(<2 x i64> %a, i32 1)
H A Ddcbt.ll3 ; RUN: -verify-machineinstrs -ppc-asm-full-reg-names \
4 ; RUN: -ppc-vsr-nums-as-vr | FileCheck %s
12 tail call void @llvm.ppc.dcbt.with.hint(i8* %a, i32 0)
22 tail call void @llvm.ppc.dcbt.with.hint(i8* %a, i32 8)
32 tail call void @llvm.ppc.dcbt.with.hint(i8* %a, i32 15)
42 tail call void @llvm.ppc.dcbtst.with.hint(i8* %a, i32 0)
52 tail call void @llvm.ppc.dcbtst.with.hint(i8* %a, i32 8)
62 tail call void @llvm.ppc.dcbtst.with.hint(i8* %a, i32 15)
66 declare void @llvm.ppc.dcbt.with.hint(i8*, i32)
67 declare void @llvm.ppc.dcbtst.with.hint(i8*, i32)
H A Ddcbf.ll2 ; RUN: -verify-machineinstrs -ppc-asm-full-reg-names \
3 ; RUN: -ppc-vsr-nums-as-vr | FileCheck %s --check-prefix=CHECK-S
5 ; RUN: -verify-machineinstrs -ppc-asm-full-reg-names \
6 ; RUN: -ppc-vsr-nums-as-vr --filetype=obj | \
12 tail call void @llvm.ppc.dcbf(i8* %a)
22 declare void @llvm.ppc.dcbf(i8*)
27 tail call void @llvm.ppc.dcbfl(i8* %a)
37 declare void @llvm.ppc.dcbfl(i8*)
43 tail call void @llvm.ppc.dcbflp(i8* %add.a)
55 declare void @llvm.ppc.dcbflp(i8*)
H A Dp10-vector-multiply.ll3 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
6 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
9 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
85 declare <4 x i32> @llvm.ppc.altivec.vmulhsw(<4 x i32>, <4 x i32>)
86 declare <4 x i32> @llvm.ppc.altivec.vmulhuw(<4 x i32>, <4 x i32>)
87 declare <2 x i64> @llvm.ppc.altivec.vmulhsd(<2 x i64>, <2 x i64>)
88 declare <2 x i64> @llvm.ppc.altivec.vmulhud(<2 x i64>, <2 x i64>)
96 %mulh = tail call <4 x i32> @llvm.ppc.altivec.vmulhsw(<4 x i32> %a, <4 x i32> %b)
106 %mulh = tail call <4 x i32> @llvm.ppc.altivec.vmulhuw(<4 x i32> %a, <4 x i32> %b)
116 %mulh = tail call <2 x i64> @llvm.ppc.altivec.vmulhsd(<2 x i64> %a, <2 x i64> %b)
[all …]
H A Dbuiltins-ppc-xlcompat-test.ll20 %0 = tail call i32 @llvm.ppc.compare.exp.eq(double %d, double %d)
24 declare i32 @llvm.ppc.compare.exp.eq(double, double)
35 %0 = tail call i32 @llvm.ppc.compare.exp.lt(double %d, double %d)
39 declare i32 @llvm.ppc.compare.exp.lt(double, double)
50 %0 = tail call i32 @llvm.ppc.compare.exp.gt(double %d, double %d)
54 declare i32 @llvm.ppc.compare.exp.gt(double, double)
65 %0 = tail call i32 @llvm.ppc.compare.exp.uo(double %d, double %d)
69 declare i32 @llvm.ppc.compare.exp.uo(double, double)
80 %test_data_class = tail call i32 @llvm.ppc.test.data.class.d(double %d, i32 0)
84 declare i32 @llvm.ppc.test.data.class.d(double, i32 immarg)
[all …]
/llvm-project-15.0.7/clang/lib/Driver/ToolChains/Arch/
H A DPPC.cpp119 ppc::FloatABI FloatABI = ppc::getPPCFloatABI(D, Args); in getPPCTargetFeatures()
120 if (FloatABI == ppc::FloatABI::Soft) in getPPCTargetFeatures()
123 ppc::ReadGOTPtrMode ReadGOT = ppc::getPPCReadGOTPtrMode(D, Triple, Args); in getPPCTargetFeatures()
128 ppc::ReadGOTPtrMode ppc::getPPCReadGOTPtrMode(const Driver &D, const llvm::Triple &Triple, in getPPCReadGOTPtrMode()
136 return ppc::ReadGOTPtrMode::Bss; in getPPCReadGOTPtrMode()
139 ppc::FloatABI ppc::getPPCFloatABI(const Driver &D, const ArgList &Args) { in getPPCFloatABI()
140 ppc::FloatABI ABI = ppc::FloatABI::Invalid; in getPPCFloatABI()
145 ABI = ppc::FloatABI::Soft; in getPPCFloatABI()
147 ABI = ppc::FloatABI::Hard; in getPPCFloatABI()
155 ABI = ppc::FloatABI::Hard; in getPPCFloatABI()
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/PowerPC/
H A Daligned-altivec.ll5 declare <4 x i32> @llvm.ppc.altivec.lvx(i8*) #1
11 %vl = call <4 x i32> @llvm.ppc.altivec.lvx(i8* %hv)
14 ; CHECK: @llvm.ppc.altivec.lvx
29 ; CHECK-NOT: @llvm.ppc.altivec.lvx
49 ; CHECK: @llvm.ppc.altivec.stvx
63 ; CHECK-NOT: @llvm.ppc.altivec.stvx
67 declare <4 x i32> @llvm.ppc.altivec.lvxl(i8*) #1
76 ; CHECK: @llvm.ppc.altivec.lvxl
91 ; CHECK-NOT: @llvm.ppc.altivec.lvxl
111 ; CHECK: @llvm.ppc.altivec.stvxl
[all …]

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