Lines Matching refs:ppc

3 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
6 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
11 declare <2 x i64> @llvm.ppc.altivec.vpdepd(<2 x i64>, <2 x i64>)
12 declare <2 x i64> @llvm.ppc.altivec.vpextd(<2 x i64>, <2 x i64>)
13 declare i64 @llvm.ppc.pdepd(i64, i64)
14 declare i64 @llvm.ppc.pextd(i64, i64)
15 declare <2 x i64> @llvm.ppc.altivec.vcfuged(<2 x i64>, <2 x i64>)
16 declare i64 @llvm.ppc.cfuged(i64, i64)
17 declare i64 @llvm.ppc.altivec.vgnb(<1 x i128>, i32)
18 declare <2 x i64> @llvm.ppc.vsx.xxeval(<2 x i64>, <2 x i64>, <2 x i64>, i32)
19 declare <2 x i64> @llvm.ppc.altivec.vclzdm(<2 x i64>, <2 x i64>)
20 declare <2 x i64> @llvm.ppc.altivec.vctzdm(<2 x i64>, <2 x i64>)
21 declare i64 @llvm.ppc.cntlzdm(i64, i64)
22 declare i64 @llvm.ppc.cnttzdm(i64, i64)
30   %tmp = tail call <2 x i64> @llvm.ppc.altivec.vpdepd(<2 x i64> %a, <2 x i64> %b)
40   %tmp = tail call <2 x i64> @llvm.ppc.altivec.vpextd(<2 x i64> %a, <2 x i64> %b)
50   %tmp = tail call i64 @llvm.ppc.pdepd(i64 %a, i64 %b)
60   %tmp = tail call i64 @llvm.ppc.pextd(i64 %a, i64 %b)
70   %tmp = tail call <2 x i64> @llvm.ppc.altivec.vcfuged(<2 x i64> %a, <2 x i64> %b)
80   %tmp = tail call i64 @llvm.ppc.cfuged(i64 %a, i64 %b)
90   %tmp = tail call i64 @llvm.ppc.altivec.vgnb(<1 x i128> %a, i32 2)
100   %tmp = tail call i64 @llvm.ppc.altivec.vgnb(<1 x i128> %a, i32 7)
110   %tmp = tail call i64 @llvm.ppc.altivec.vgnb(<1 x i128> %a, i32 5)
120   %tmp = tail call <2 x i64> @llvm.ppc.vsx.xxeval(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, i32 255)
130   %tmp = tail call <2 x i64> @llvm.ppc.altivec.vclzdm(<2 x i64> %a, <2 x i64> %b)
140   %tmp = tail call <2 x i64> @llvm.ppc.altivec.vctzdm(<2 x i64> %a, <2 x i64> %b)
150   %tmp = tail call i64 @llvm.ppc.cntlzdm(i64 %a, i64 %b)
160   %tmp = tail call i64 @llvm.ppc.cnttzdm(i64 %a, i64 %b)