Lines Matching refs:ppc
3 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
6 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
9 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
15 declare i32 @llvm.ppc.altivec.vextractbm(<16 x i8>)
16 declare i32 @llvm.ppc.altivec.vextracthm(<8 x i16>)
17 declare i32 @llvm.ppc.altivec.vextractwm(<4 x i32>)
18 declare i32 @llvm.ppc.altivec.vextractdm(<2 x i64>)
19 declare i32 @llvm.ppc.altivec.vextractqm(<1 x i128>)
27 %ext = tail call i32 @llvm.ppc.altivec.vextractbm(<16 x i8> %a)
37 %ext = tail call i32 @llvm.ppc.altivec.vextracthm(<8 x i16> %a)
47 %ext = tail call i32 @llvm.ppc.altivec.vextractwm(<4 x i32> %a)
57 %ext = tail call i32 @llvm.ppc.altivec.vextractdm(<2 x i64> %a)
67 %ext = tail call i32 @llvm.ppc.altivec.vextractqm(<1 x i128> %a)
71 declare <16 x i8> @llvm.ppc.altivec.vexpandbm(<16 x i8>)
72 declare <8 x i16> @llvm.ppc.altivec.vexpandhm(<8 x i16>)
73 declare <4 x i32> @llvm.ppc.altivec.vexpandwm(<4 x i32>)
74 declare <2 x i64> @llvm.ppc.altivec.vexpanddm(<2 x i64>)
75 declare <1 x i128> @llvm.ppc.altivec.vexpandqm(<1 x i128>)
83 %exp = tail call <16 x i8> @llvm.ppc.altivec.vexpandbm(<16 x i8> %a)
93 %exp = tail call <8 x i16> @llvm.ppc.altivec.vexpandhm(<8 x i16> %a)
103 %exp = tail call <4 x i32> @llvm.ppc.altivec.vexpandwm(<4 x i32> %a)
113 %exp = tail call <2 x i64> @llvm.ppc.altivec.vexpanddm(<2 x i64> %a)
123 %exp = tail call <1 x i128> @llvm.ppc.altivec.vexpandqm(<1 x i128> %a)
127 declare i64 @llvm.ppc.altivec.vcntmbb(<16 x i8>, i32)
128 declare i64 @llvm.ppc.altivec.vcntmbh(<8 x i16>, i32)
129 declare i64 @llvm.ppc.altivec.vcntmbw(<4 x i32>, i32)
130 declare i64 @llvm.ppc.altivec.vcntmbd(<2 x i64>, i32)
138 %cnt = tail call i64 @llvm.ppc.altivec.vcntmbb(<16 x i8> %a, i32 1)
148 %cnt = tail call i64 @llvm.ppc.altivec.vcntmbh(<8 x i16> %a, i32 0)
158 %cnt = tail call i64 @llvm.ppc.altivec.vcntmbw(<4 x i32> %a, i32 1)
168 %cnt = tail call i64 @llvm.ppc.altivec.vcntmbd(<2 x i64> %a, i32 0)
172 declare <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64)
173 declare <8 x i16> @llvm.ppc.altivec.mtvsrhm(i64)
174 declare <4 x i32> @llvm.ppc.altivec.mtvsrwm(i64)
175 declare <2 x i64> @llvm.ppc.altivec.mtvsrdm(i64)
176 declare <1 x i128> @llvm.ppc.altivec.mtvsrqm(i64)
184 %mv = tail call <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64 %a)
194 %mv = tail call <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64 1)
204 %mv = tail call <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64 255)
214 %mv = tail call <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64 65535)
224 %mv = tail call <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64 65536)
234 %mv = tail call <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64 65546)
244 %mv = tail call <8 x i16> @llvm.ppc.altivec.mtvsrhm(i64 %a)
254 %mv = tail call <4 x i32> @llvm.ppc.altivec.mtvsrwm(i64 %a)
264 %mv = tail call <2 x i64> @llvm.ppc.altivec.mtvsrdm(i64 %a)
274 %mv = tail call <1 x i128> @llvm.ppc.altivec.mtvsrqm(i64 %a)