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Searched refs:permute (Results 1 – 25 of 31) sorted by relevance

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/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dvec-perm-08.ll5 ; Test a high1/low2 permute for v16i8.
18 ; Test a low2/high1 permute for v16i8.
31 ; Test a low1/high2 permute for v16i8.
44 ; Test a high2/low1 permute for v16i8.
70 ; Test a high1/low2 permute for v8i16.
81 ; Test a low2/high1 permute for v8i16.
92 ; Test a high1/low2 permute for v4i32.
102 ; Test a low2/high1 permute for v4i32.
112 ; Test a high1/low2 permute for v2i64.
122 ; Test low2/high1 permute for v2i64.
[all …]
H A Dvec-perm-10.ll1 ; Test general vector permute of a v8i16.
H A Dvec-perm-11.ll1 ; Test general vector permute of a v4i32.
H A Dvec-perm-09.ll1 ; Test general vector permute of a v16i8.
H A Dvec-perm-14.ll29 ; Test that a zero index in the permute vector is used instead of VGBM, with
/llvm-project-15.0.7/mlir/lib/Dialect/X86Vector/Transforms/
H A DAVXTranspose.cpp132 vs[0] = mm256Permute2f128Ps(ib, s0, s1, MaskHelper::permute<2, 0>()); in transpose4x8xf32()
133 vs[1] = mm256Permute2f128Ps(ib, s2, s3, MaskHelper::permute<2, 0>()); in transpose4x8xf32()
134 vs[2] = mm256Permute2f128Ps(ib, s0, s1, MaskHelper::permute<3, 1>()); in transpose4x8xf32()
135 vs[3] = mm256Permute2f128Ps(ib, s2, s3, MaskHelper::permute<3, 1>()); in transpose4x8xf32()
180 vs[0] = mm256Permute2f128Ps(ib, s0, s4, MaskHelper::permute<2, 0>()); in transpose8x8xf32()
181 vs[1] = mm256Permute2f128Ps(ib, s1, s5, MaskHelper::permute<2, 0>()); in transpose8x8xf32()
182 vs[2] = mm256Permute2f128Ps(ib, s2, s6, MaskHelper::permute<2, 0>()); in transpose8x8xf32()
183 vs[3] = mm256Permute2f128Ps(ib, s3, s7, MaskHelper::permute<2, 0>()); in transpose8x8xf32()
184 vs[4] = mm256Permute2f128Ps(ib, s0, s4, MaskHelper::permute<3, 1>()); in transpose8x8xf32()
185 vs[5] = mm256Permute2f128Ps(ib, s1, s5, MaskHelper::permute<3, 1>()); in transpose8x8xf32()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dllvm.amdgcn.ds.permute.ll3 declare i32 @llvm.amdgcn.ds.permute(i32, i32) #0
8 %bpermute = call i32 @llvm.amdgcn.ds.permute(i32 %index, i32 %src) #0
17 %bpermute = call i32 @llvm.amdgcn.ds.permute(i32 %index, i32 %src) #0
H A Dwaitcnt-permute.mir4 # CHECK-LABEL: name: waitcnt-permute{{$}}
8 name: waitcnt-permute
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dregbankselect-amdgcn.ds.permute.mir20 …; CHECK-NEXT: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ds.permute), [[COPY2]…
23 %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ds.permute), %0, %1
/llvm-project-15.0.7/mlir/test/Dialect/Affine/
H A Dloop-permute.mlir8 // CHECK-120-LABEL: func @permute
9 func.func @permute(%U0 : index, %U1 : index, %U2 : index) {
/llvm-project-15.0.7/mlir/include/mlir/Dialect/X86Vector/
H A DTransforms.h70 static uint8_t permute() { in permute() function
/llvm-project-15.0.7/mlir/unittests/Analysis/Presburger/
H A DIntegerPolyhedronTest.cpp111 auto permute = [&perm](ArrayRef<int64_t> coeffs) { in checkPermutationsSample() local
121 permutedIneqs.push_back(permute(ineq)); in checkPermutationsSample()
123 permutedEqs.push_back(permute(eq)); in checkPermutationsSample()
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dswizzle-avx2.ll12 ; Check that we produce a single vector permute / shuffle in all cases.
H A Dxop-mask-comments.ll54 ; we can't decode vpperm's other permute ops
/llvm-project-15.0.7/mlir/test/Transforms/
H A Dnormalize-memrefs.mlir6 // CHECK-LABEL: func @permute()
7 func.func @permute() {
/llvm-project-15.0.7/llvm/docs/
H A DAMDGPUModifierSyntax.rst117 offset:swizzle(QUAD_PERM,{0..3},{0..3},{0..3},{0..3}) Specifies a quad permute mode pattern
120 … offset:swizzle(BITMASK_PERM, "<mask>") Specifies a bitmask permute mode pattern.
1183 quad_perm:[{0..3},{0..3},{0..3},{0..3}] Full permute of 4 threads.
1224 quad_perm:[{0..3},{0..3},{0..3},{0..3}] Full permute of 4 threads.
1261 quad_perm:[{0..3},{0..3},{0..3},{0..3}] Full permute of 4 threads.
/llvm-project-15.0.7/openmp/docs/design/
H A DRuntimes.rst295 **Syntax:** ``KMP_AFFINITY=[<modifier>,...]<type>[,<permute>][,<offset>]``
351 For both ``compact`` and ``scatter``, ``permute`` and ``offset`` are allowed;
353 a permute specifier. **Both permute and offset default to 0.**
355 The ``permute`` specifier controls which levels are most significant when sorting
356 the machine topology map. A value for ``permute`` forces the mappings to make the
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCScheduleP9.td323 // Three cycle permute operations.
H A DPPCScheduleP10.td57 def P10_PM : ProcResource<4>; // Four 128-bit permute (PM) pipelines.
/llvm-project-15.0.7/mlir/lib/Dialect/SparseTensor/Transforms/
H A DSparsification.cpp116 static AffineMap permute(MLIRContext *context, AffineMap m, in permute() function
1786 permute(getContext(), op.getTiedIndexingMap(t), topSort), // new order in resolveCycle()
/llvm-project-15.0.7/mlir/include/mlir/Dialect/Affine/IR/
H A DAffineOps.td969 * Consider adding a permutation map to permute the slice that is read from memory
1036 * Consider adding a permutation map to permute the slice that is written to memory
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DIntrinsicsPowerPC.td75 // Bit permute doubleword
1416 // P10 VSX Vector permute extended.
/llvm-project-15.0.7/llvm/test/MC/PowerPC/
H A Dppc64-encoding-vmx.s46 # Vector permute and formatting instructions
/llvm-project-15.0.7/clang/test/CodeGenOpenCL/
H A Dbuiltins-amdgcn.cl281 // CHECK: call i32 @llvm.amdgcn.ds.permute(i32 %a, i32 %b)
/llvm-project-15.0.7/mlir/include/mlir/Dialect/Vector/IR/
H A DVectorOps.td1192 (i.e. if it does not permute or broadcast any dimension).
1400 (i.e. if it does not permute any dimension). In contrast to `transfer_read`,

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