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/llvm-project-15.0.7/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.h145 bool ConditionPassed(const uint32_t opcode);
147 uint32_t CurrentCond(const uint32_t opcode);
301 const uint32_t opcode,
332 bool EmulateLDRRtPCRelative(const uint32_t opcode,
378 bool EmulateIT(const uint32_t opcode, const ARMEncoding encoding);
384 bool EmulateB(const uint32_t opcode, const ARMEncoding encoding);
387 bool EmulateCB(const uint32_t opcode, const ARMEncoding encoding);
390 bool EmulateTB(const uint32_t opcode, const ARMEncoding encoding);
469 bool EmulateLDRImmediateARM(const uint32_t opcode,
482 bool EmulateLDRBImmediateARM(const uint32_t opcode,
[all …]
H A DEmulateInstructionARM.cpp1290 Rd = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0); in EmulateMOVRdRm()
2585 d = Bit32(opcode, 22) << 4 | Bits32(opcode, 15, 12); in EmulateVPUSH()
2596 d = Bits32(opcode, 15, 12) << 1 | Bit32(opcode, 22); in EmulateVPUSH()
2677 d = Bit32(opcode, 22) << 4 | Bits32(opcode, 15, 12); in EmulateVPOP()
3478 Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0); in EmulateCMPReg()
3954 (BitIsSet(opcode, 14) && BitIsSet(opcode, 15))) in EmulateLDM()
4202 (BitIsSet(opcode, 14) && BitIsSet(opcode, 15))) in EmulateLDMDB()
11252 if ((Bit32(opcode, 24) == Bit32(opcode, 23)) && BitIsSet(opcode, 21)) in EmulateVLDM()
11287 if ((Bit32(opcode, 24) == Bit32(opcode, 23)) && BitIsSet(opcode, 21)) in EmulateVLDM()
11446 if ((Bit32(opcode, 24) == Bit32(opcode, 23)) && BitIsSet(opcode, 21)) in EmulateVSTM()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430InstrFormats.td54 let Inst{15-12} = opcode;
67 class I8rr<bits<4> opcode,
73 class I8ri<bits<4> opcode,
82 class I8rc<bits<4> opcode,
91 let Inst{15-12} = opcode;
99 class I8rm<bits<4> opcode,
108 class I8rn<bits<4> opcode,
114 class I8rp<bits<4> opcode,
120 class I8mr<bits<4> opcode,
129 class I8mi<bits<4> opcode,
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dlegalizer-info-validation.mir21 # DEBUG-NEXT: .. opcode [[SUB_OPC]] is aliased to [[ADD_OPC]]
26 # DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
30 # DEBUG-NEXT: G_SDIV (opcode {{[0-9]+}}): 1 type index
35 # DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
44 # DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
49 # DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
54 # DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
524 # DEBUG: G_SMIN (opcode {{[0-9]+}}): 1 type index
527 # DEBUG: G_SMAX (opcode {{[0-9]+}}): 1 type index
531 # DEBUG: G_UMIN (opcode {{[0-9]+}}): 1 type index
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrFormats.td22 let Inst{0-5} = opcode;
210 class SCForm<bits<6> opcode, bits<1> xo,
213 : I<opcode, OOL, IOL, asmstr, itin> {
225 : I<opcode, OOL, IOL, asmstr, itin> {
239 : I<opcode, OOL, IOL, asmstr, itin> {
252 : I<opcode, OOL, IOL, asmstr, itin> {
276 : I<opcode, OOL, IOL, asmstr, itin> {
289 : I<opcode, OOL, IOL, asmstr, itin> {
348 : I<opcode, OOL, IOL, asmstr, itin> {
412 : I<opcode, OOL, IOL, asmstr, itin> {
[all …]
/llvm-project-15.0.7/lldb/source/Plugins/Process/Utility/
H A DARMUtils.h55 return DecodeImmShift(Bits32(opcode, 5, 4), in DecodeImmShiftThumb()
56 Bits32(opcode, 14, 12) << 2 | Bits32(opcode, 7, 6), in DecodeImmShiftThumb()
64 return DecodeImmShift(Bits32(opcode, 6, 5), Bits32(opcode, 11, 7), shift_t); in DecodeImmShiftARM()
306 const uint32_t i = bit(opcode, 26); in ThumbExpandImm_C()
307 const uint32_t imm3 = bits(opcode, 14, 12); in ThumbExpandImm_C()
308 const uint32_t abcdefgh = bits(opcode, 7, 0); in ThumbExpandImm_C()
349 const uint32_t i = bit(opcode, 26); in ThumbImm12()
350 const uint32_t imm3 = bits(opcode, 14, 12); in ThumbImm12()
351 const uint32_t imm8 = bits(opcode, 7, 0); in ThumbImm12()
358 const uint32_t imm7 = bits(opcode, 6, 0); in ThumbImm7Scaled()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZInstrFormats.td2301 : InstRIEb<opcode, (outs),
2383 : InstRRS<opcode, (outs),
2389 : InstRRS<opcode, (outs),
2411 : InstRIS<opcode, (outs),
2417 : InstRIS<opcode, (outs),
2529 : InstRSYa<opcode,
3197 : InstSSb<opcode,
3970 : InstSSd<opcode, (outs),
4102 : InstSSb<opcode,
4291 : InstSSF<opcode, (outs),
[all …]
/llvm-project-15.0.7/lldb/source/Plugins/Instruction/PPC64/
H A DEmulateInstructionPPC64.cpp204 uint32_t rt = Bits32(opcode, 25, 21); in EmulateMFSPR()
229 uint32_t rt = Bits32(opcode, 25, 21); in EmulateLD()
230 uint32_t ra = Bits32(opcode, 20, 16); in EmulateLD()
231 uint32_t ds = Bits32(opcode, 15, 2); in EmulateLD()
258 uint32_t rs = Bits32(opcode, 25, 21); in EmulateSTD()
259 uint32_t ra = Bits32(opcode, 20, 16); in EmulateSTD()
260 uint32_t ds = Bits32(opcode, 15, 2); in EmulateSTD()
261 uint32_t u = Bits32(opcode, 1, 0); in EmulateSTD()
325 uint32_t rs = Bits32(opcode, 25, 21); in EmulateOR()
326 uint32_t ra = Bits32(opcode, 20, 16); in EmulateOR()
[all …]
H A DEmulateInstructionPPC64.h73 bool (EmulateInstructionPPC64::*callback)(uint32_t opcode);
79 Opcode *GetOpcodeForInstruction(uint32_t opcode);
81 bool EmulateMFSPR(uint32_t opcode);
82 bool EmulateLD(uint32_t opcode);
83 bool EmulateSTD(uint32_t opcode);
84 bool EmulateOR(uint32_t opcode);
85 bool EmulateADDI(uint32_t opcode);
/llvm-project-15.0.7/lldb/source/Plugins/Instruction/ARM64/
H A DEmulateInstructionARM64.cpp616 const uint32_t S = Bit32(opcode, 29); in EmulateADDSUBImm()
695 uint32_t V = Bit32(opcode, 26); in EmulateLDPSTP()
696 uint32_t L = Bit32(opcode, 22); in EmulateLDPSTP()
699 uint32_t Rn = Bits32(opcode, 9, 5); in EmulateLDPSTP()
700 uint32_t Rt = Bits32(opcode, 4, 0); in EmulateLDPSTP()
919 uint32_t n = Bits32(opcode, 9, 5); in EmulateLDRSTRImm()
920 uint32_t t = Bits32(opcode, 4, 0); in EmulateLDRSTRImm()
1122 uint32_t t = Bits32(opcode, 4, 0); in EmulateCBZ()
1157 uint32_t t = Bits32(opcode, 4, 0); in EmulateTBZ()
1158 uint32_t bit_pos = (Bit32(opcode, 31) << 6) | (Bits32(opcode, 23, 19)); in EmulateTBZ()
[all …]
H A DEmulateInstructionARM64.h160 bool (EmulateInstructionARM64::*callback)(const uint32_t opcode);
164 static Opcode *GetOpcodeForInstruction(const uint32_t opcode);
174 bool EmulateADDSUBImm(const uint32_t opcode);
176 template <AddrMode a_mode> bool EmulateLDPSTP(const uint32_t opcode);
178 template <AddrMode a_mode> bool EmulateLDRSTRImm(const uint32_t opcode);
180 bool EmulateB(const uint32_t opcode);
182 bool EmulateBcond(const uint32_t opcode);
184 bool EmulateCBZ(const uint32_t opcode);
186 bool EmulateTBZ(const uint32_t opcode);
/llvm-project-15.0.7/llvm/test/tools/llvm-objdump/MachO/
H A Dbad-bind.test2 …object (for BIND_OPCODE_SET_DYLIB_ORDINAL_ULEB bad library ordinal: 355 (max 1) for opcode at: 0x0)
11 …ormed object (for BIND_OPCODE_SET_DYLIB_SPECIAL_IMM unknown special ordinal: -5 for opcode at: 0x0)
17 …: truncated or malformed object (for BIND_OPCODE_SET_TYPE_IMM bad bind type: 5 for opcode at: 0x14)
23 …d object (for BIND_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB bad segIndex (too large) for opcode at: 0x15)
29 … or malformed object (for BIND_OPCODE_ADD_ADDR_ULEB bad offset, not in section for opcode at: 0x17)
49 RUN: not llvm-objdump --macho --bind %p/Inputs/macho-bind-bad-opcode-value 2>&1 | FileCheck --check…
50 …-OPCODE-VALUE: macho-bind-bad-opcode-value': truncated or malformed object (bad bind info (bad opc…
71 … truncated or malformed object (for REBASE_OPCODE_SET_TYPE_IMM bad bind type: 5 for opcode at: 0x0)
89 …formed object (for REBASE_OPCODE_DO_REBASE_IMM_TIMES bad offset, not in section for opcode at: 0x3)
100 RUN: not llvm-objdump --macho --rebase %p/Inputs/macho-rebase-bad-opcode-value 2>&1 | FileCheck --c…
[all …]
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DInstruction.def25 #define HANDLE_TERM_INST(num, opcode, Class)
27 #define HANDLE_TERM_INST(num, opcode, Class) HANDLE_INST(num, opcode, Class)
41 #define HANDLE_UNARY_INST(num, opcode, Class) HANDLE_INST(num, opcode, Class)
55 #define HANDLE_BINARY_INST(num, opcode, Class) HANDLE_INST(num, opcode, Class)
67 #define HANDLE_MEMORY_INST(num, opcode, Class)
69 #define HANDLE_MEMORY_INST(num, opcode, Class) HANDLE_INST(num, opcode, Class)
81 #define HANDLE_CAST_INST(num, opcode, Class)
83 #define HANDLE_CAST_INST(num, opcode, Class) HANDLE_INST(num, opcode, Class)
97 #define HANDLE_FUNCLETPAD_INST(num, opcode, Class) HANDLE_INST(num, opcode, Class)
109 #define HANDLE_OTHER_INST(num, opcode, Class)
[all …]
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrFormatsC.td36 class RVInst16CR<bits<4> funct4, bits<2> opcode, dag outs, dag ins,
45 let Inst{1-0} = opcode;
51 class RVInst16CI<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
61 let Inst{1-0} = opcode;
76 let Inst{1-0} = opcode;
87 let Inst{1-0} = opcode;
102 let Inst{1-0} = opcode;
117 let Inst{1-0} = opcode;
130 let Inst{1-0} = opcode;
141 let Inst{1-0} = opcode;
[all …]
H A DRISCVInstrFormats.td444 bits<7> opcode;
457 let Opcode = opcode;
464 bits<7> opcode;
479 let Opcode = opcode;
486 bits<7> opcode;
497 let Opcode = opcode;
504 bits<7> opcode;
516 let Opcode = opcode;
523 bits<7> opcode;
544 bits<7> opcode;
[all …]
/llvm-project-15.0.7/mlir/unittests/Dialect/SPIRV/
H A DSerializationTest.cpp81 using HandleFn = llvm::function_ref<bool(spirv::Opcode opcode,
95 spirv::Opcode opcode = in scanInstruction() local
99 if (handleFn(opcode, operands)) in scanInstruction()
123 auto hasBlockDecoration = [](spirv::Opcode opcode, in TEST_F()
125 return opcode == spirv::Opcode::OpDecorate && operands.size() == 2 && in TEST_F()
141 auto countBlockDecoration = [&count](spirv::Opcode opcode, in TEST_F() argument
143 if (opcode == spirv::Opcode::OpDecorate && operands.size() == 2 && in TEST_F()
160 auto hasVarName = [](spirv::Opcode opcode, ArrayRef<uint32_t> operands) { in TEST_F() argument
162 return opcode == spirv::Opcode::OpName && in TEST_F()
176 auto hasVarName = [](spirv::Opcode opcode, ArrayRef<uint32_t> operands) { in TEST_F() argument
[all …]
/llvm-project-15.0.7/llvm/test/TableGen/
H A DSlice.td15 class Inst<bits<8> opcode, dag oopnds, dag iopnds, string asmstr,
17 bits<8> Opcode = opcode;
65 multiclass scalar<bits<8> opcode, string asmstr = "", list<list<dag>> patterns = []> {
66 def SSrr : Inst<opcode, (outs FR32:$dst), (ins FR32:$src),
69 def SSrm : Inst<opcode, (outs FR32:$dst), (ins FR32:$src),
74 multiclass vscalar<bits<8> opcode, string asmstr = "", list<list<dag>> patterns = []> {
75 def V#NAME#SSrr : Inst<opcode, (outs FR32:$dst), (ins FR32:$src),
78 def V#NAME#SSrm : Inst<opcode, (outs FR32:$dst), (ins FR32:$src),
83 multiclass myscalar<bits<8> opcode, string asmstr = "", list<list<dag>> patterns = []> :
84 scalar<opcode, asmstr, patterns>,
[all …]
H A Dcast.td21 class Inst<bits<8> opcode, dag oopnds, dag iopnds, string asmstr,
23 bits<8> Opcode = opcode;
72 multiclass arith<bits<8> opcode, string asmstr, string Intr> {
73 def PS : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
77 def PD : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
84 class IntInst<bits<8> opcode, string asmstr, Intrinsic Intr> :
85 Inst<opcode,(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
90 multiclass arith_int<bits<8> opcode, string asmstr, string Intr> {
91 def PS_Int : IntInst<opcode, asmstr, !cast<Intrinsic>(!strconcat(Intr, "_ps"))>;
93 def PD_Int : IntInst<opcode, asmstr, !cast<Intrinsic>(!strconcat(Intr, "_pd"))>;
/llvm-project-15.0.7/lldb/test/Shell/SymbolFile/DWARF/x86/
H A Ddwarf5-line-strp.s103 .byte 0 # opcode: 0x1 has 0 args
104 .byte 0x1 # opcode: 0x2 has 1 args
105 .byte 0x1 # opcode: 0x3 has 1 args
106 .byte 0x1 # opcode: 0x4 has 1 args
107 .byte 0x1 # opcode: 0x5 has 1 args
108 .byte 0 # opcode: 0x6 has 0 args
109 .byte 0 # opcode: 0x7 has 0 args
110 .byte 0 # opcode: 0x8 has 0 args
111 .byte 0x1 # opcode: 0x9 has 1 args
112 .byte 0 # opcode: 0xa has 0 args
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Difconv-regmask.ll3 %union.opcode = type { i32 }
5 @opcode = external global %union.opcode, align 4
10 …%bf.load = load i32, i32* getelementptr inbounds (%union.opcode, %union.opcode* @opcode, i32 0, i3…
H A Doptselect-regclass.ll3 %union.opcode.0.2.5.8.15.28 = type { i32 }
5 @opcode = external global %union.opcode.0.2.5.8.15.28, align 4
12 … load i32, i32* getelementptr inbounds (%union.opcode.0.2.5.8.15.28, %union.opcode.0.2.5.8.15.28* …
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchInstrFormats.td46 // <opcode | rj | rd>
59 // <opcode | rk | rj | rd>
108 // <opcode | I5 | rj | rd>
123 // <opcode | I6 | rj | rd>
138 // <opcode | I8 | rj | rd>
153 // <opcode | I12 | rj | rd>
168 // <opcode | I14 | rj | rd>
198 // <opcode | I20 | rd>
225 // <opcode | I15>
248 // <opcode[11:1] | msbw | opcode[0] | lsbw | rj | rd>
[all …]
H A DLoongArchFloatInstrFormats.td12 // opcode - operation code.
20 // <opcode | fj | fd>
33 // <opcode | fk | fj | fd>
48 // <opcode | fa | fk | fj | fd>
65 // <opcode | I12 | rj | fd>
97 // <opcode[7:2] | I21[15:0] | opcode[1:0] | cj | I21[20:16]>
104 let Inst{31-26} = opcode{7-2};
106 let Inst{9-8} = opcode{1-0};
112 // <opcode | ca | fk | fj | fd>
129 // <opcode | src | dst>
[all …]
/llvm-project-15.0.7/llvm/lib/Target/DirectX/
H A DDXIL.td57 dxil_class op_class; // name of the opcode class
96 dxil_param<1, "i32", "opcode", "DXIL opcode">,
106 dxil_param<1, "i32", "opcode", "DXIL opcode">,
116 dxil_param<1, "i32", "opcode", "DXIL opcode">,
124 dxil_param<1, "i32", "opcode", "DXIL opcode">,
133 dxil_param<1, "i32", "opcode", "DXIL opcode">,
142 dxil_param<1, "i32", "opcode", "DXIL opcode">
/llvm-project-15.0.7/llvm/test/CodeGen/LoongArch/
H A Dmisc.mir13 # opcode | imm15
59 # opcode | imm26{15-0} | imm26{25-16}
87 # opcode{11-1} | msb |opcode{0}| lsb | rj | rd
115 # opcode | msb | lsb | rj | rd
143 # opcode | rk | rj | 0x0
171 # opcode | imm12 | rj | imm5
190 # opcode | rk | rj | imm5

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