Lines Matching refs:opcode
40 // MemKey identifies a targe reg-mem opcode, while MemType can be either
42 // its corresponding target opcode. See comment at MemFoldPseudo.
2114 class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
2116 : InstRRE<opcode, (outs cls:$R1), (ins),
2122 class InherentDualRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
2123 : InstRRE<opcode, (outs cls:$R1, cls:$R2), (ins),
2126 class InherentVRIa<string mnemonic, bits<16> opcode, bits<16> value>
2127 : InstVRIa<opcode, (outs VR128:$V1), (ins), mnemonic#"\t$V1", []> {
2132 class StoreInherentS<string mnemonic, bits<16> opcode,
2134 : InstS<opcode, (outs), (ins bdaddr12only:$BD2),
2140 class SideEffectInherentE<string mnemonic, bits<16>opcode>
2141 : InstE<opcode, (outs), (ins), mnemonic, []>;
2143 class SideEffectInherentS<string mnemonic, bits<16> opcode,
2145 : InstS<opcode, (outs), (ins), mnemonic, [(operator)]> {
2149 class SideEffectInherentRRE<string mnemonic, bits<16> opcode>
2150 : InstRRE<opcode, (outs), (ins), mnemonic, []> {
2156 class CallRI<string mnemonic, bits<12> opcode>
2157 : InstRIb<opcode, (outs), (ins GR64:$R1, brtarget16tls:$RI2),
2161 class CallRIL<string mnemonic, bits<12> opcode>
2162 : InstRILb<opcode, (outs), (ins GR64:$R1, brtarget32tls:$RI2),
2165 class CallRR<string mnemonic, bits<8> opcode>
2166 : InstRR<opcode, (outs), (ins GR64:$R1, ADDR64:$R2),
2169 class CallRX<string mnemonic, bits<8> opcode>
2170 : InstRXa<opcode, (outs), (ins GR64:$R1, bdxaddr12only:$XBD2),
2173 class CondBranchRI<string mnemonic, bits<12> opcode,
2175 : InstRIc<opcode, (outs), (ins cond4:$valid, cond4:$M1, brtarget16:$RI2),
2181 class AsmCondBranchRI<string mnemonic, bits<12> opcode>
2182 : InstRIc<opcode, (outs), (ins imm32zx4:$M1, brtarget16:$RI2),
2185 class FixedCondBranchRI<CondVariant V, string mnemonic, bits<12> opcode,
2187 : InstRIc<opcode, (outs), (ins brtarget16:$RI2),
2194 class CondBranchRIL<string mnemonic, bits<12> opcode>
2195 : InstRILc<opcode, (outs), (ins cond4:$valid, cond4:$M1, brtarget32:$RI2),
2200 class AsmCondBranchRIL<string mnemonic, bits<12> opcode>
2201 : InstRILc<opcode, (outs), (ins imm32zx4:$M1, brtarget32:$RI2),
2204 class FixedCondBranchRIL<CondVariant V, string mnemonic, bits<12> opcode>
2205 : InstRILc<opcode, (outs), (ins brtarget32:$RI2),
2212 class CondBranchRR<string mnemonic, bits<8> opcode>
2213 : InstRR<opcode, (outs), (ins cond4:$valid, cond4:$R1, GR64:$R2),
2218 class AsmCondBranchRR<string mnemonic, bits<8> opcode>
2219 : InstRR<opcode, (outs), (ins imm32zx4:$R1, GR64:$R2),
2222 class FixedCondBranchRR<CondVariant V, string mnemonic, bits<8> opcode,
2224 : InstRR<opcode, (outs), (ins ADDR64:$R2),
2231 class CondBranchRX<string mnemonic, bits<8> opcode>
2232 : InstRXb<opcode, (outs), (ins cond4:$valid, cond4:$M1, bdxaddr12only:$XBD2),
2237 class AsmCondBranchRX<string mnemonic, bits<8> opcode>
2238 : InstRXb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr12only:$XBD2),
2241 class FixedCondBranchRX<CondVariant V, string mnemonic, bits<8> opcode>
2242 : InstRXb<opcode, (outs), (ins bdxaddr12only:$XBD2),
2249 class CondBranchRXY<string mnemonic, bits<16> opcode>
2250 : InstRXYb<opcode, (outs), (ins cond4:$valid, cond4:$M1, bdxaddr20only:$XBD2),
2256 class AsmCondBranchRXY<string mnemonic, bits<16> opcode>
2257 : InstRXYb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr20only:$XBD2),
2262 class FixedCondBranchRXY<CondVariant V, string mnemonic, bits<16> opcode,
2264 : InstRXYb<opcode, (outs), (ins bdxaddr20only:$XBD2),
2273 class CmpBranchRIEa<string mnemonic, bits<16> opcode,
2275 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, cond4:$M3),
2278 class AsmCmpBranchRIEa<string mnemonic, bits<16> opcode,
2280 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, imm32zx4:$M3),
2283 class FixedCmpBranchRIEa<CondVariant V, string mnemonic, bits<16> opcode,
2285 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2),
2292 multiclass CmpBranchRIEaPair<string mnemonic, bits<16> opcode,
2295 def "" : CmpBranchRIEa<mnemonic, opcode, cls, imm>;
2296 def Asm : AsmCmpBranchRIEa<mnemonic, opcode, cls, imm>;
2299 class CmpBranchRIEb<string mnemonic, bits<16> opcode,
2301 : InstRIEb<opcode, (outs),
2305 class AsmCmpBranchRIEb<string mnemonic, bits<16> opcode,
2307 : InstRIEb<opcode, (outs),
2311 class FixedCmpBranchRIEb<CondVariant V, string mnemonic, bits<16> opcode,
2313 : InstRIEb<opcode, (outs), (ins cls:$R1, cls:$R2, brtarget16:$RI4),
2320 multiclass CmpBranchRIEbPair<string mnemonic, bits<16> opcode,
2323 def "" : CmpBranchRIEb<mnemonic, opcode, cls>;
2324 def Asm : AsmCmpBranchRIEb<mnemonic, opcode, cls>;
2327 class CmpBranchRIEc<string mnemonic, bits<16> opcode,
2329 : InstRIEc<opcode, (outs),
2333 class AsmCmpBranchRIEc<string mnemonic, bits<16> opcode,
2335 : InstRIEc<opcode, (outs),
2339 class FixedCmpBranchRIEc<CondVariant V, string mnemonic, bits<16> opcode,
2341 : InstRIEc<opcode, (outs), (ins cls:$R1, imm:$I2, brtarget16:$RI4),
2348 multiclass CmpBranchRIEcPair<string mnemonic, bits<16> opcode,
2351 def "" : CmpBranchRIEc<mnemonic, opcode, cls, imm>;
2352 def Asm : AsmCmpBranchRIEc<mnemonic, opcode, cls, imm>;
2355 class CmpBranchRRFc<string mnemonic, bits<16> opcode,
2357 : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2, cond4:$M3),
2360 class AsmCmpBranchRRFc<string mnemonic, bits<16> opcode,
2362 : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2, imm32zx4:$M3),
2365 multiclass CmpBranchRRFcPair<string mnemonic, bits<16> opcode,
2368 def "" : CmpBranchRRFc<mnemonic, opcode, cls>;
2369 def Asm : AsmCmpBranchRRFc<mnemonic, opcode, cls>;
2372 class FixedCmpBranchRRFc<CondVariant V, string mnemonic, bits<16> opcode,
2374 : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2),
2381 class CmpBranchRRS<string mnemonic, bits<16> opcode,
2383 : InstRRS<opcode, (outs),
2387 class AsmCmpBranchRRS<string mnemonic, bits<16> opcode,
2389 : InstRRS<opcode, (outs),
2393 class FixedCmpBranchRRS<CondVariant V, string mnemonic, bits<16> opcode,
2395 : InstRRS<opcode, (outs), (ins cls:$R1, cls:$R2, bdaddr12only:$BD4),
2402 multiclass CmpBranchRRSPair<string mnemonic, bits<16> opcode,
2405 def "" : CmpBranchRRS<mnemonic, opcode, cls>;
2406 def Asm : AsmCmpBranchRRS<mnemonic, opcode, cls>;
2409 class CmpBranchRIS<string mnemonic, bits<16> opcode,
2411 : InstRIS<opcode, (outs),
2415 class AsmCmpBranchRIS<string mnemonic, bits<16> opcode,
2417 : InstRIS<opcode, (outs),
2421 class FixedCmpBranchRIS<CondVariant V, string mnemonic, bits<16> opcode,
2423 : InstRIS<opcode, (outs), (ins cls:$R1, imm:$I2, bdaddr12only:$BD4),
2430 multiclass CmpBranchRISPair<string mnemonic, bits<16> opcode,
2433 def "" : CmpBranchRIS<mnemonic, opcode, cls, imm>;
2434 def Asm : AsmCmpBranchRIS<mnemonic, opcode, cls, imm>;
2437 class CmpBranchRSYb<string mnemonic, bits<16> opcode,
2439 : InstRSYb<opcode, (outs), (ins cls:$R1, bdaddr20only:$BD2, cond4:$M3),
2442 class AsmCmpBranchRSYb<string mnemonic, bits<16> opcode,
2444 : InstRSYb<opcode, (outs), (ins cls:$R1, bdaddr20only:$BD2, imm32zx4:$M3),
2447 multiclass CmpBranchRSYbPair<string mnemonic, bits<16> opcode,
2450 def "" : CmpBranchRSYb<mnemonic, opcode, cls>;
2451 def Asm : AsmCmpBranchRSYb<mnemonic, opcode, cls>;
2454 class FixedCmpBranchRSYb<CondVariant V, string mnemonic, bits<16> opcode,
2456 : InstRSYb<opcode, (outs), (ins cls:$R1, bdaddr20only:$BD2),
2463 class BranchUnaryRI<string mnemonic, bits<12> opcode, RegisterOperand cls>
2464 : InstRIb<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget16:$RI2),
2470 class BranchUnaryRIL<string mnemonic, bits<12> opcode, RegisterOperand cls>
2471 : InstRILb<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget32:$RI2),
2477 class BranchUnaryRR<string mnemonic, bits<8> opcode, RegisterOperand cls>
2478 : InstRR<opcode, (outs cls:$R1), (ins cls:$R1src, GR64:$R2),
2484 class BranchUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
2485 : InstRRE<opcode, (outs cls:$R1), (ins cls:$R1src, GR64:$R2),
2491 class BranchUnaryRX<string mnemonic, bits<8> opcode, RegisterOperand cls>
2492 : InstRXa<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2),
2498 class BranchUnaryRXY<string mnemonic, bits<16> opcode, RegisterOperand cls>
2499 : InstRXYa<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr20only:$XBD2),
2505 class BranchBinaryRSI<string mnemonic, bits<8> opcode, RegisterOperand cls>
2506 : InstRSI<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, brtarget16:$RI2),
2512 class BranchBinaryRIEe<string mnemonic, bits<16> opcode, RegisterOperand cls>
2513 : InstRIEe<opcode, (outs cls:$R1),
2520 class BranchBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls>
2521 : InstRSa<opcode, (outs cls:$R1),
2528 class BranchBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
2529 : InstRSYa<opcode,
2536 class LoadMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
2538 : InstRSa<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
2543 class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
2545 : InstRSYa<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
2560 class LoadMultipleSSe<string mnemonic, bits<8> opcode, RegisterOperand cls>
2561 : InstSSe<opcode, (outs cls:$R1, cls:$R3),
2567 multiclass LoadMultipleVRSaAlign<string mnemonic, bits<16> opcode> {
2569 def Align : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3),
2573 def "" : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3),
2579 class StoreRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2581 : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2),
2591 class StoreRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2594 : InstRXa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
2603 class StoreRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2606 : InstRXYa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
2627 class StoreVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2629 : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2),
2637 class StoreVRXGeneric<string mnemonic, bits<16> opcode>
2638 : InstVRX<opcode, (outs), (ins VR128:$V1, bdxaddr12only:$XBD2, imm32zx4:$M3),
2643 multiclass StoreVRXAlign<string mnemonic, bits<16> opcode> {
2645 def Align : InstVRX<opcode, (outs),
2649 def "" : InstVRX<opcode, (outs), (ins VR128:$V1, bdxaddr12only:$XBD2),
2654 class StoreLengthVRSb<string mnemonic, bits<16> opcode,
2656 : InstVRSb<opcode, (outs), (ins VR128:$V1, GR32:$R3, bdaddr12only:$BD2),
2664 class StoreLengthVRSd<string mnemonic, bits<16> opcode,
2666 : InstVRSd<opcode, (outs), (ins VR128:$V1, GR32:$R3, bdaddr12only:$BD2),
2673 class StoreLengthVSI<string mnemonic, bits<16> opcode,
2675 : InstVSI<opcode, (outs), (ins VR128:$V1, bdaddr12only:$BD2, imm32zx8:$I3),
2682 class StoreMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
2684 : InstRSa<opcode, (outs), (ins cls:$R1, cls:$R3, mode:$BD2),
2689 class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
2691 : InstRSYa<opcode, (outs), (ins cls:$R1, cls:$R3, mode:$BD2),
2706 multiclass StoreMultipleVRSaAlign<string mnemonic, bits<16> opcode> {
2708 def Align : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3,
2712 def "" : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3,
2724 class StoreSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2726 : InstSI<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2),
2732 class StoreSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2734 : InstSIY<opcode, (outs), (ins mviaddr20pair:$BD1, imm:$I2),
2740 class StoreSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2742 : InstSIL<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2),
2758 class StoreSSE<string mnemonic, bits<16> opcode>
2759 : InstSSE<opcode, (outs), (ins bdaddr12only:$BD1, bdaddr12only:$BD2),
2764 class CondStoreRSY<string mnemonic, bits<16> opcode,
2767 : InstRSYb<opcode, (outs), (ins cls:$R1, mode:$BD2, cond4:$valid, cond4:$M3),
2776 class AsmCondStoreRSY<string mnemonic, bits<16> opcode,
2779 : InstRSYb<opcode, (outs), (ins cls:$R1, mode:$BD2, imm32zx4:$M3),
2786 class FixedCondStoreRSY<CondVariant V, string mnemonic, bits<16> opcode,
2789 : InstRSYb<opcode, (outs), (ins cls:$R1, mode:$BD2),
2798 multiclass CondStoreRSYPair<string mnemonic, bits<16> opcode,
2802 def "" : CondStoreRSY<mnemonic, opcode, cls, bytes, mode>;
2803 def Asm : AsmCondStoreRSY<mnemonic, opcode, cls, bytes, mode>;
2806 class SideEffectUnaryI<string mnemonic, bits<8> opcode, ImmOpWithPattern imm>
2807 : InstI<opcode, (outs), (ins imm:$I1),
2810 class SideEffectUnaryRR<string mnemonic, bits<8>opcode, RegisterOperand cls>
2811 : InstRR<opcode, (outs), (ins cls:$R1),
2816 class SideEffectUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
2818 : InstRRE<opcode, (outs), (ins cls:$R1),
2823 class SideEffectUnaryS<string mnemonic, bits<16> opcode,
2826 : InstS<opcode, (outs), (ins mode:$BD2),
2832 class SideEffectUnarySIY<string mnemonic, bits<16> opcode,
2835 : InstSIY<opcode, (outs), (ins mode:$BD1),
2842 class SideEffectAddressS<string mnemonic, bits<16> opcode,
2845 : InstS<opcode, (outs), (ins mode:$BD2),
2848 class LoadAddressRX<string mnemonic, bits<8> opcode,
2850 : InstRXa<opcode, (outs GR64:$R1), (ins mode:$XBD2),
2854 class LoadAddressRXY<string mnemonic, bits<16> opcode,
2856 : InstRXYa<opcode, (outs GR64:$R1), (ins mode:$XBD2),
2870 class LoadAddressRIL<string mnemonic, bits<12> opcode,
2872 : InstRILb<opcode, (outs GR64:$R1), (ins pcrel32:$RI2),
2876 class UnaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2878 : InstRR<opcode, (outs cls1:$R1), (ins cls2:$R2),
2885 class UnaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2887 : InstRRE<opcode, (outs cls1:$R1), (ins cls2:$R2),
2894 class UnaryTiedRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
2895 : InstRRE<opcode, (outs cls:$R1), (ins cls:$R1src),
2902 class UnaryMemRRFc<string mnemonic, bits<16> opcode,
2904 : InstRRFc<opcode, (outs cls2:$R2, cls1:$R1), (ins cls1:$R1src),
2911 class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2913 : InstRIa<opcode, (outs cls:$R1), (ins imm:$I2),
2917 class UnaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2919 : InstRILa<opcode, (outs cls:$R1), (ins imm:$I2),
2923 class UnaryRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2925 : InstRILb<opcode, (outs cls:$R1), (ins pcrel32:$RI2),
2935 class CondUnaryRSY<string mnemonic, bits<16> opcode,
2938 : InstRSYb<opcode, (outs cls:$R1),
2957 class AsmCondUnaryRSY<string mnemonic, bits<16> opcode,
2960 : InstRSYb<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2, imm32zx4:$M3),
2969 class FixedCondUnaryRSY<CondVariant V, string mnemonic, bits<16> opcode,
2972 : InstRSYb<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2),
2983 multiclass CondUnaryRSYPair<string mnemonic, bits<16> opcode,
2988 def "" : CondUnaryRSY<mnemonic, opcode, operator, cls, bytes, mode>;
2989 def Asm : AsmCondUnaryRSY<mnemonic, opcode, cls, bytes, mode>;
2992 class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2995 : InstRXa<opcode, (outs cls:$R1), (ins mode:$XBD2),
3004 class UnaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3006 : InstRXE<opcode, (outs cls:$R1), (ins bdxaddr12only:$XBD2),
3016 class UnaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3019 : InstRXYa<opcode, (outs cls:$R1), (ins mode:$XBD2),
3040 class UnaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3042 : InstVRIa<opcode, (outs tr.op:$V1), (ins imm:$I2),
3048 class UnaryVRIaGeneric<string mnemonic, bits<16> opcode, ImmOpWithPattern imm>
3049 : InstVRIa<opcode, (outs VR128:$V1), (ins imm:$I2, imm32zx4:$M3),
3052 class UnaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3055 : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2),
3065 class UnaryVRRaGeneric<string mnemonic, bits<16> opcode, bits<4> m4 = 0,
3067 : InstVRRa<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3),
3073 class UnaryVRRaFloatGeneric<string mnemonic, bits<16> opcode, bits<4> m5 = 0>
3074 : InstVRRa<opcode, (outs VR128:$V1),
3084 multiclass UnaryExtraVRRaSPair<string mnemonic, bits<16> opcode,
3089 def "" : InstVRRa<opcode, (outs tr1.op:$V1),
3097 def S : UnaryVRRa<mnemonic#"s", opcode, operator_cc, tr1, tr2,
3101 multiclass UnaryExtraVRRaSPairGeneric<string mnemonic, bits<16> opcode> {
3103 def "" : InstVRRa<opcode, (outs VR128:$V1),
3111 class UnaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3113 : InstVRX<opcode, (outs tr.op:$V1), (ins bdxaddr12only:$XBD2),
3121 class UnaryVRXGeneric<string mnemonic, bits<16> opcode>
3122 : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
3127 multiclass UnaryVRXAlign<string mnemonic, bits<16> opcode> {
3129 def Align : InstVRX<opcode, (outs VR128:$V1),
3133 def "" : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2),
3138 class SideEffectBinaryRX<string mnemonic, bits<8> opcode,
3140 : InstRXa<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
3143 class SideEffectBinaryRXY<string mnemonic, bits<16> opcode,
3145 : InstRXYa<opcode, (outs), (ins cls:$R1, bdxaddr20only:$XBD2),
3148 class SideEffectBinaryRILPC<string mnemonic, bits<12> opcode,
3150 : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2),
3158 class SideEffectBinaryRRE<string mnemonic, bits<16> opcode,
3160 : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2),
3163 class SideEffectBinaryRRFa<string mnemonic, bits<16> opcode,
3165 : InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2),
3171 class SideEffectBinaryRRFc<string mnemonic, bits<16> opcode,
3173 : InstRRFc<opcode, (outs), (ins cls1:$R1, cls2:$R2),
3178 class SideEffectBinaryIE<string mnemonic, bits<16> opcode,
3180 : InstIE<opcode, (outs), (ins imm1:$I1, imm2:$I2),
3183 class SideEffectBinarySI<string mnemonic, bits<8> opcode, Operand imm>
3184 : InstSI<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
3187 class SideEffectBinarySIL<string mnemonic, bits<16> opcode,
3189 : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
3192 class SideEffectBinarySSa<string mnemonic, bits<8> opcode>
3193 : InstSSa<opcode, (outs), (ins bdladdr12onlylen8:$BDL1, bdaddr12only:$BD2),
3196 class SideEffectBinarySSb<string mnemonic, bits<8> opcode>
3197 : InstSSb<opcode,
3201 class SideEffectBinarySSf<string mnemonic, bits<8> opcode>
3202 : InstSSf<opcode, (outs), (ins bdaddr12only:$BD1, bdladdr12onlylen8:$BDL2),
3205 class SideEffectBinarySSE<string mnemonic, bits<16> opcode>
3206 : InstSSE<opcode, (outs), (ins bdaddr12only:$BD1, bdaddr12only:$BD2),
3209 class SideEffectBinaryMemMemRR<string mnemonic, bits<8> opcode,
3211 : InstRR<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src),
3217 class SideEffectBinaryMemRRE<string mnemonic, bits<16> opcode,
3219 : InstRRE<opcode, (outs cls2:$R2), (ins cls1:$R1, cls2:$R2src),
3225 class SideEffectBinaryMemMemRRE<string mnemonic, bits<16> opcode,
3227 : InstRRE<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src),
3233 class SideEffectBinaryMemMemRRFc<string mnemonic, bits<16> opcode,
3235 : InstRRFc<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src),
3242 class BinaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3244 : InstRR<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
3253 class BinaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3255 : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
3264 class BinaryRRD<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3266 : InstRRD<opcode, (outs cls1:$R1), (ins cls2:$R3, cls2:$R2),
3273 class BinaryRRFa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3276 : InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3),
3308 class BinaryRRFb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3311 : InstRRFb<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3),
3317 class BinaryRRFc<string mnemonic, bits<16> opcode,
3319 : InstRRFc<opcode, (outs cls1:$R1), (ins cls2:$R2, imm32zx4:$M3),
3322 class BinaryMemRRFc<string mnemonic, bits<16> opcode,
3324 : InstRRFc<opcode, (outs cls2:$R2, cls1:$R1), (ins cls1:$R1src, imm:$M3),
3330 multiclass BinaryMemRRFcOpt<string mnemonic, bits<16> opcode,
3332 def "" : BinaryMemRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>;
3333 def Opt : UnaryMemRRFc<mnemonic, opcode, cls1, cls2>;
3336 class BinaryRRFd<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3338 : InstRRFd<opcode, (outs cls1:$R1), (ins cls2:$R2, imm32zx4:$M4),
3341 class BinaryRRFe<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3343 : InstRRFe<opcode, (outs cls1:$R1), (ins imm32zx4:$M3, cls2:$R2),
3348 class CondBinaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3350 : InstRRFc<opcode, (outs cls1:$R1),
3366 class AsmCondBinaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3368 : InstRRFc<opcode, (outs cls1:$R1),
3376 class FixedCondBinaryRRF<CondVariant V, string mnemonic, bits<16> opcode,
3378 : InstRRFc<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
3387 multiclass CondBinaryRRFPair<string mnemonic, bits<16> opcode,
3390 def "" : CondBinaryRRF<mnemonic, opcode, cls1, cls2>;
3391 def Asm : AsmCondBinaryRRF<mnemonic, opcode, cls1, cls2>;
3394 class CondBinaryRRFa<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3396 : InstRRFa<opcode, (outs cls1:$R1),
3410 class AsmCondBinaryRRFa<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3412 : InstRRFa<opcode, (outs cls1:$R1), (ins cls3:$R3, cls2:$R2, imm32zx4:$M4),
3416 class FixedCondBinaryRRFa<CondVariant V, string mnemonic, bits<16> opcode,
3419 : InstRRFa<opcode, (outs cls1:$R1), (ins cls3:$R3, cls2:$R2),
3426 multiclass CondBinaryRRFaPair<string mnemonic, bits<16> opcode,
3430 def "" : CondBinaryRRFa<mnemonic, opcode, cls1, cls2, cls3>;
3431 def Asm : AsmCondBinaryRRFa<mnemonic, opcode, cls1, cls2, cls3>;
3434 class BinaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
3436 : InstRIa<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
3443 class BinaryRIE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3445 : InstRIEd<opcode, (outs cls:$R1), (ins cls:$R3, imm:$I2),
3461 class CondBinaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
3463 : InstRIEg<opcode, (outs cls:$R1),
3475 class AsmCondBinaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
3477 : InstRIEg<opcode, (outs cls:$R1),
3485 class FixedCondBinaryRIE<CondVariant V, string mnemonic, bits<16> opcode,
3487 : InstRIEg<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
3496 multiclass CondBinaryRIEPair<string mnemonic, bits<16> opcode,
3499 def "" : CondBinaryRIE<mnemonic, opcode, cls, imm>;
3500 def Asm : AsmCondBinaryRIE<mnemonic, opcode, cls, imm>;
3503 class BinaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
3505 : InstRILa<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
3512 class BinaryRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3514 : InstRSa<opcode, (outs cls:$R1), (ins cls:$R1src, shift12only:$BD2),
3522 class BinaryRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3524 : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, shift20only:$BD2),
3539 class BinaryRSL<string mnemonic, bits<16> opcode, RegisterOperand cls>
3540 : InstRSLb<opcode, (outs cls:$R1),
3546 class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3549 : InstRXa<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
3560 class BinaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3562 : InstRXE<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2),
3575 class BinaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3578 : InstRXF<opcode, (outs cls1:$R1), (ins cls2:$R3, bdxaddr12only:$XBD2),
3587 class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3590 : InstRXYa<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
3614 class BinarySI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3616 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
3623 class BinarySIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3625 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
3643 class BinarySSF<string mnemonic, bits<12> opcode, RegisterOperand cls>
3644 : InstSSF<opcode, (outs cls:$R3), (ins bdaddr12pair:$BD1, bdaddr12pair:$BD2),
3649 class BinaryVRIb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3651 : InstVRIb<opcode, (outs tr.op:$V1), (ins imm32zx8:$I2, imm32zx8:$I3),
3657 class BinaryVRIbGeneric<string mnemonic, bits<16> opcode>
3658 : InstVRIb<opcode, (outs VR128:$V1),
3662 class BinaryVRIc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3664 : InstVRIc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, imm32zx16:$I2),
3671 class BinaryVRIcGeneric<string mnemonic, bits<16> opcode>
3672 : InstVRIc<opcode, (outs VR128:$V1),
3676 class BinaryVRIe<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3678 : InstVRIe<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx12:$I3),
3686 class BinaryVRIeFloatGeneric<string mnemonic, bits<16> opcode>
3687 : InstVRIe<opcode, (outs VR128:$V1),
3691 class BinaryVRIh<string mnemonic, bits<16> opcode>
3692 : InstVRIh<opcode, (outs VR128:$V1),
3696 class BinaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3698 : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx4:$M5),
3706 class BinaryVRRaFloatGeneric<string mnemonic, bits<16> opcode>
3707 : InstVRRa<opcode, (outs VR128:$V1),
3711 class BinaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3714 : InstVRRb<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
3722 class BinaryExtraVRRb<string mnemonic, bits<16> opcode, bits<4> type = 0>
3723 : InstVRRb<opcode, (outs VR128:$V1), (ins VR128:$V2, VR128:$V3, imm32zx4:$M5),
3728 class BinaryExtraVRRbGeneric<string mnemonic, bits<16> opcode>
3729 : InstVRRb<opcode, (outs VR128:$V1),
3735 multiclass BinaryVRRbSPair<string mnemonic, bits<16> opcode,
3739 def "" : BinaryVRRb<mnemonic, opcode, operator, tr1, tr2, type,
3742 def S : BinaryVRRb<mnemonic#"s", opcode, operator_cc, tr1, tr2, type,
3746 class BinaryVRRbSPairGeneric<string mnemonic, bits<16> opcode>
3747 : InstVRRb<opcode, (outs VR128:$V1),
3757 multiclass BinaryExtraVRRbSPair<string mnemonic, bits<16> opcode,
3762 def "" : InstVRRb<opcode, (outs tr1.op:$V1),
3771 def S : BinaryVRRb<mnemonic#"s", opcode, operator_cc, tr1, tr2, type, 1>;
3774 multiclass BinaryExtraVRRbSPairGeneric<string mnemonic, bits<16> opcode> {
3776 def "" : InstVRRb<opcode, (outs VR128:$V1),
3784 class BinaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3787 : InstVRRc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
3798 class BinaryVRRcGeneric<string mnemonic, bits<16> opcode, bits<4> m5 = 0,
3800 : InstVRRc<opcode, (outs VR128:$V1),
3807 class BinaryVRRcFloatGeneric<string mnemonic, bits<16> opcode, bits<4> m6 = 0>
3808 : InstVRRc<opcode, (outs VR128:$V1),
3816 multiclass BinaryVRRcSPair<string mnemonic, bits<16> opcode,
3821 def "" : BinaryVRRc<mnemonic, opcode, operator, tr1, tr2, type,
3824 def S : BinaryVRRc<mnemonic#"s", opcode, operator_cc, tr1, tr2, type,
3828 class BinaryVRRcSPairFloatGeneric<string mnemonic, bits<16> opcode>
3829 : InstVRRc<opcode, (outs VR128:$V1),
3834 class BinaryVRRf<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3836 : InstVRRf<opcode, (outs tr.op:$V1), (ins GR64:$R2, GR64:$R3),
3840 class BinaryVRRi<string mnemonic, bits<16> opcode, RegisterOperand cls>
3841 : InstVRRi<opcode, (outs cls:$R1), (ins VR128:$V2, imm32zx4:$M3),
3846 class BinaryVRRk<string mnemonic, bits<16> opcode>
3847 : InstVRRk<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3),
3850 class BinaryVRSa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3852 : InstVRSa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, shift12only:$BD2),
3859 class BinaryVRSaGeneric<string mnemonic, bits<16> opcode>
3860 : InstVRSa<opcode, (outs VR128:$V1),
3864 class BinaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3866 : InstVRSb<opcode, (outs VR128:$V1), (ins GR32:$R3, bdaddr12only:$BD2),
3874 class BinaryVRSc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3876 : InstVRSc<opcode, (outs GR64:$R1), (ins tr.op:$V3, shift12only:$BD2),
3882 class BinaryVRScGeneric<string mnemonic, bits<16> opcode>
3883 : InstVRSc<opcode, (outs GR64:$R1),
3887 class BinaryVRSd<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3889 : InstVRSd<opcode, (outs VR128:$V1), (ins GR32:$R3, bdaddr12only:$BD2),
3896 class BinaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3898 : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
3906 class StoreBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
3908 : InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, mode:$BD2),
3914 class StoreBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
3916 : InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, mode:$BD2),
3934 class StoreBinaryRSL<string mnemonic, bits<16> opcode, RegisterOperand cls>
3935 : InstRSLb<opcode, (outs),
3941 class BinaryVSI<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3943 : InstVSI<opcode, (outs VR128:$V1), (ins bdaddr12only:$BD2, imm32zx8:$I3),
3950 class StoreBinaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
3952 : InstVRV<opcode, (outs), (ins VR128:$V1, bdvaddr12only:$VBD2, index:$M3),
3958 class StoreBinaryVRX<string mnemonic, bits<16> opcode,
3961 : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2, index:$M3),
3968 class MemoryBinarySSd<string mnemonic, bits<8> opcode,
3970 : InstSSd<opcode, (outs),
3974 class CompareRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3976 : InstRR<opcode, (outs), (ins cls1:$R1, cls2:$R2),
3984 class CompareRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3986 : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2),
3994 class CompareRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
3996 : InstRIa<opcode, (outs), (ins cls:$R1, imm:$I2),
4002 class CompareRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
4004 : InstRILa<opcode, (outs), (ins cls:$R1, imm:$I2),
4010 class CompareRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
4012 : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2),
4023 class CompareRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
4026 : InstRXa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
4036 class CompareRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4038 : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
4049 class CompareRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4052 : InstRXYa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
4075 class CompareRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
4077 : InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, mode:$BD2),
4083 class CompareRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
4085 : InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, mode:$BD2),
4101 class CompareSSb<string mnemonic, bits<8> opcode>
4102 : InstSSb<opcode,
4109 class CompareSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
4112 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
4119 class CompareSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4121 : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
4128 class CompareSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4131 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
4150 class CompareVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4152 : InstVRRa<opcode, (outs), (ins tr.op:$V1, tr.op:$V2),
4163 class CompareVRRaGeneric<string mnemonic, bits<16> opcode>
4164 : InstVRRa<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx4:$M3),
4171 class CompareVRRaFloatGeneric<string mnemonic, bits<16> opcode>
4172 : InstVRRa<opcode, (outs),
4179 class CompareVRRh<string mnemonic, bits<16> opcode>
4180 : InstVRRh<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx4:$M3),
4185 class TestInherentS<string mnemonic, bits<16> opcode,
4187 : InstS<opcode, (outs), (ins), mnemonic, [(set CC, (operator))]> {
4191 class TestRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4193 : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
4199 class TestBinarySIL<string mnemonic, bits<16> opcode,
4201 : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
4205 class TestRSL<string mnemonic, bits<16> opcode>
4206 : InstRSLa<opcode, (outs), (ins bdladdr12onlylen4:$BDL1),
4211 class TestVRRg<string mnemonic, bits<16> opcode>
4212 : InstVRRg<opcode, (outs), (ins VR128:$V1),
4215 class SideEffectTernarySSc<string mnemonic, bits<8> opcode>
4216 : InstSSc<opcode, (outs), (ins bdladdr12onlylen4:$BDL1,
4220 class SideEffectTernaryRRFa<string mnemonic, bits<16> opcode,
4223 : InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3),
4228 class SideEffectTernaryMemMemRRFa<string mnemonic, bits<16> opcode,
4231 : InstRRFa<opcode, (outs cls1:$R1, cls2:$R2),
4239 class SideEffectTernaryRRFb<string mnemonic, bits<16> opcode,
4242 : InstRRFb<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3),
4247 class SideEffectTernaryMemMemMemRRFb<string mnemonic, bits<16> opcode,
4251 : InstRRFb<opcode, (outs cls1:$R1, cls2:$R2, cls3:$R3),
4259 class SideEffectTernaryRRFc<string mnemonic, bits<16> opcode,
4262 : InstRRFc<opcode, (outs), (ins cls1:$R1, cls2:$R2, imm:$M3),
4265 multiclass SideEffectTernaryRRFcOpt<string mnemonic, bits<16> opcode,
4268 def "" : SideEffectTernaryRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>;
4269 def Opt : SideEffectBinaryRRFc<mnemonic, opcode, cls1, cls2>;
4272 class SideEffectTernaryMemMemRRFc<string mnemonic, bits<16> opcode,
4275 : InstRRFc<opcode, (outs cls1:$R1, cls2:$R2),
4282 multiclass SideEffectTernaryMemMemRRFcOpt<string mnemonic, bits<16> opcode,
4285 def "" : SideEffectTernaryMemMemRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>;
4286 def Opt : SideEffectBinaryMemMemRRFc<mnemonic, opcode, cls1, cls2>;
4289 class SideEffectTernarySSF<string mnemonic, bits<12> opcode,
4291 : InstSSF<opcode, (outs),
4295 class TernaryRRFa<string mnemonic, bits<16> opcode,
4298 : InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3, imm32zx4:$M4),
4301 class TernaryRRFb<string mnemonic, bits<16> opcode,
4304 : InstRRFb<opcode, (outs cls1:$R1, cls3:$R3),
4311 class TernaryRRFe<string mnemonic, bits<16> opcode, RegisterOperand cls1,
4313 : InstRRFe<opcode, (outs cls1:$R1),
4317 class TernaryRRD<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4319 : InstRRD<opcode, (outs cls1:$R1), (ins cls2:$R1src, cls2:$R3, cls2:$R2),
4328 class TernaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
4330 : InstRSb<opcode, (outs cls:$R1),
4340 class TernaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
4342 : InstRSYb<opcode, (outs cls:$R1),
4362 class SideEffectTernaryRS<string mnemonic, bits<8> opcode,
4364 : InstRSa<opcode, (outs),
4368 class SideEffectTernaryRSY<string mnemonic, bits<16> opcode,
4370 : InstRSYa<opcode, (outs),
4374 class SideEffectTernaryMemMemRS<string mnemonic, bits<8> opcode,
4376 : InstRSa<opcode, (outs cls1:$R1, cls2:$R3),
4383 class SideEffectTernaryMemMemRSY<string mnemonic, bits<16> opcode,
4385 : InstRSYa<opcode, (outs cls1:$R1, cls2:$R3),
4392 class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4395 : InstRXF<opcode, (outs cls1:$R1),
4408 class TernaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4410 : InstVRIa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V1src, imm:$I2, index:$M3),
4418 class TernaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4420 : InstVRId<opcode, (outs tr1.op:$V1),
4429 class TernaryVRIi<string mnemonic, bits<16> opcode, RegisterOperand cls>
4430 : InstVRIi<opcode, (outs VR128:$V1),
4434 class TernaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4436 : InstVRRa<opcode, (outs tr1.op:$V1),
4446 class TernaryVRRaFloatGeneric<string mnemonic, bits<16> opcode>
4447 : InstVRRa<opcode, (outs VR128:$V1),
4451 class TernaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4454 : InstVRRb<opcode, (outs tr1.op:$V1),
4467 multiclass TernaryOptVRRbSPair<string mnemonic, bits<16> opcode,
4472 def "" : TernaryVRRb<mnemonic, opcode, operator, tr1, tr2, type,
4478 def S : TernaryVRRb<mnemonic#"s", opcode, operator_cc, tr1, tr2, type,
4485 multiclass TernaryOptVRRbSPairGeneric<string mnemonic, bits<16> opcode> {
4487 def "" : InstVRRb<opcode, (outs VR128:$V1),
4495 class TernaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4497 : InstVRRc<opcode, (outs tr1.op:$V1),
4507 class TernaryVRRcFloat<string mnemonic, bits<16> opcode,
4510 : InstVRRc<opcode, (outs tr1.op:$V1),
4520 class TernaryVRRcFloatGeneric<string mnemonic, bits<16> opcode>
4521 : InstVRRc<opcode, (outs VR128:$V1),
4526 class TernaryVRRd<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4528 : InstVRRd<opcode, (outs tr1.op:$V1),
4538 class TernaryVRRdGeneric<string mnemonic, bits<16> opcode>
4539 : InstVRRd<opcode, (outs VR128:$V1),
4547 multiclass TernaryExtraVRRd<string mnemonic, bits<16> opcode,
4551 def "" : InstVRRd<opcode, (outs tr1.op:$V1),
4562 multiclass TernaryExtraVRRdGeneric<string mnemonic, bits<16> opcode> {
4564 def "" : InstVRRd<opcode, (outs VR128:$V1),
4573 class TernaryVRRe<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4576 : InstVRRe<opcode, (outs tr1.op:$V1),
4588 class TernaryVRReFloatGeneric<string mnemonic, bits<16> opcode>
4589 : InstVRRe<opcode, (outs VR128:$V1),
4593 class TernaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4595 : InstVRSb<opcode, (outs tr1.op:$V1),
4606 class TernaryVRRi<string mnemonic, bits<16> opcode, RegisterOperand cls>
4607 : InstVRRi<opcode, (outs cls:$R1), (ins VR128:$V2,
4611 class TernaryVRRj<string mnemonic, bits<16> opcode>
4612 : InstVRRj<opcode, (outs VR128:$V1), (ins VR128:$V2,
4616 class TernaryVRSbGeneric<string mnemonic, bits<16> opcode>
4617 : InstVRSb<opcode, (outs VR128:$V1),
4624 class TernaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
4626 : InstVRV<opcode, (outs VR128:$V1),
4635 class TernaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4637 : InstVRX<opcode, (outs tr1.op:$V1),
4649 class QuaternaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4651 : InstVRId<opcode, (outs tr1.op:$V1),
4663 class QuaternaryVRIdGeneric<string mnemonic, bits<16> opcode>
4664 : InstVRId<opcode, (outs VR128:$V1),
4672 class QuaternaryVRIf<string mnemonic, bits<16> opcode>
4673 : InstVRIf<opcode, (outs VR128:$V1),
4678 class QuaternaryVRIg<string mnemonic, bits<16> opcode>
4679 : InstVRIg<opcode, (outs VR128:$V1),
4684 class QuaternaryVRRd<string mnemonic, bits<16> opcode,
4688 : InstVRRd<opcode, (outs tr1.op:$V1),
4699 class QuaternaryVRRdGeneric<string mnemonic, bits<16> opcode>
4700 : InstVRRd<opcode, (outs VR128:$V1),
4707 multiclass QuaternaryOptVRRdSPair<string mnemonic, bits<16> opcode,
4712 def "" : QuaternaryVRRd<mnemonic, opcode, operator,
4719 def S : QuaternaryVRRd<mnemonic#"s", opcode, operator_cc,
4727 multiclass QuaternaryOptVRRdSPairGeneric<string mnemonic, bits<16> opcode> {
4729 def "" : QuaternaryVRRdGeneric<mnemonic, opcode>;
4735 class SideEffectQuaternaryRRFa<string mnemonic, bits<16> opcode,
4738 : InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3, imm32zx4:$M4),
4741 multiclass SideEffectQuaternaryRRFaOptOpt<string mnemonic, bits<16> opcode,
4745 def "" : SideEffectQuaternaryRRFa<mnemonic, opcode, cls1, cls2, cls3>;
4746 def Opt : SideEffectTernaryRRFa<mnemonic, opcode, cls1, cls2, cls3>;
4747 def OptOpt : SideEffectBinaryRRFa<mnemonic, opcode, cls1, cls2>;
4750 class SideEffectQuaternaryRRFb<string mnemonic, bits<16> opcode,
4753 : InstRRFb<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3, imm32zx4:$M4),
4756 multiclass SideEffectQuaternaryRRFbOpt<string mnemonic, bits<16> opcode,
4760 def "" : SideEffectQuaternaryRRFb<mnemonic, opcode, cls1, cls2, cls3>;
4761 def Opt : SideEffectTernaryRRFb<mnemonic, opcode, cls1, cls2, cls3>;
4764 class SideEffectQuaternarySSe<string mnemonic, bits<8> opcode,
4766 : InstSSe<opcode, (outs),
4770 class LoadAndOpRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4772 : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, mode:$BD2),
4779 class CmpSwapRRE<string mnemonic, bits<16> opcode,
4781 : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
4789 class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
4791 : InstRSa<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
4800 class CmpSwapRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4802 : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
4821 class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
4823 : InstRIEf<opcode, (outs cls1:$R1),
4831 class PrefetchRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator>
4832 : InstRXYb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr20only:$XBD2),
4836 class PrefetchRILPC<string mnemonic, bits<12> opcode,
4838 : InstRILc<opcode, (outs), (ins imm32zx4_timm:$M1, pcrel32:$RI2),
4847 class BranchPreloadSMI<string mnemonic, bits<8> opcode>
4848 : InstSMI<opcode, (outs),
4852 class BranchPreloadMII<string mnemonic, bits<8> opcode>
4853 : InstMII<opcode, (outs),
4862 multiclass LoadAndTestRRE<string mnemonic, bits<16> opcode,
4864 def "" : UnaryRRE<mnemonic, opcode, null_frag, cls, cls>;
4866 def Compare : CompareRRE<mnemonic, opcode, null_frag, cls, cls>;
5273 multiclass BinaryRXYAndPseudo<string mnemonic, bits<16> opcode,
5277 def "" : BinaryRXY<mnemonic, opcode, operator, cls, load, bytes, mode> {
5303 multiclass BinaryRXEAndPseudo<string mnemonic, bits<16> opcode,
5306 def "" : BinaryRXE<mnemonic, opcode, operator, cls, load, bytes> {
5313 multiclass TernaryRXFAndPseudo<string mnemonic, bits<16> opcode,
5317 def "" : TernaryRXF<mnemonic, opcode, operator, cls1, cls2, load, bytes> {
5324 multiclass CondUnaryRSYPairAndMemFold<string mnemonic, bits<16> opcode,
5328 defm "" : CondUnaryRSYPair<mnemonic, opcode, operator, cls, bytes, mode>;
5346 multiclass MemorySS<string mnemonic, bits<8> opcode, SDPatternOperator memop> {
5347 def "" : SideEffectBinarySSa<mnemonic, opcode>;
5361 multiclass CompareMemorySS<string mnemonic, bits<8> opcode,
5363 def "" : SideEffectBinarySSa<mnemonic, opcode>;
5381 multiclass StringRRE<string mnemonic, bits<16> opcode,
5384 def "" : SideEffectBinaryMemMemRRE<mnemonic, opcode, GR64, GR64>;