Lines Matching refs:opcode
889 bool EmulateInstructionARM::EmulatePUSH(const uint32_t opcode, in EmulatePUSH() argument
919 if (ConditionPassed(opcode)) { in EmulatePUSH()
928 registers = Bits32(opcode, 7, 0); in EmulatePUSH()
930 if (Bit32(opcode, 8)) in EmulatePUSH()
938 registers = Bits32(opcode, 15, 0) & ~0xa000; in EmulatePUSH()
944 Rt = Bits32(opcode, 15, 12); in EmulatePUSH()
951 registers = Bits32(opcode, 15, 0); in EmulatePUSH()
957 Rt = Bits32(opcode, 15, 12); in EmulatePUSH()
1011 bool EmulateInstructionARM::EmulatePOP(const uint32_t opcode, in EmulatePOP() argument
1034 if (ConditionPassed(opcode)) { in EmulatePOP()
1043 registers = Bits32(opcode, 7, 0); in EmulatePOP()
1045 if (Bit32(opcode, 8)) in EmulatePOP()
1053 registers = Bits32(opcode, 15, 0) & ~0x2000; in EmulatePOP()
1056 if (BitCount(registers) < 2 || (Bit32(opcode, 15) && Bit32(opcode, 14))) in EmulatePOP()
1064 Rt = Bits32(opcode, 15, 12); in EmulatePOP()
1074 registers = Bits32(opcode, 15, 0); in EmulatePOP()
1080 if (BitIsSet(opcode, 13) && ArchVersion() >= ARMv7) in EmulatePOP()
1084 Rt = Bits32(opcode, 15, 12); in EmulatePOP()
1139 bool EmulateInstructionARM::EmulateADDRdSPImm(const uint32_t opcode, in EmulateADDRdSPImm() argument
1161 if (ConditionPassed(opcode)) { in EmulateADDRdSPImm()
1170 imm32 = Bits32(opcode, 7, 0) << 2; // imm32 = ZeroExtend(imm8:'00', 32) in EmulateADDRdSPImm()
1173 Rd = Bits32(opcode, 15, 12); in EmulateADDRdSPImm()
1174 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateADDRdSPImm()
1200 bool EmulateInstructionARM::EmulateMOVRdSP(const uint32_t opcode, in EmulateMOVRdSP() argument
1222 if (ConditionPassed(opcode)) { in EmulateMOVRdSP()
1255 bool EmulateInstructionARM::EmulateMOVLowHigh(const uint32_t opcode, in EmulateMOVLowHigh() argument
1257 return EmulateMOVRdRm(opcode, encoding); in EmulateMOVLowHigh()
1262 bool EmulateInstructionARM::EmulateMOVRdRm(const uint32_t opcode, in EmulateMOVRdRm() argument
1284 if (ConditionPassed(opcode)) { in EmulateMOVRdRm()
1290 Rd = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0); in EmulateMOVRdRm()
1291 Rm = Bits32(opcode, 6, 3); in EmulateMOVRdRm()
1297 Rd = Bits32(opcode, 2, 0); in EmulateMOVRdRm()
1298 Rm = Bits32(opcode, 5, 3); in EmulateMOVRdRm()
1304 Rd = Bits32(opcode, 11, 8); in EmulateMOVRdRm()
1305 Rm = Bits32(opcode, 3, 0); in EmulateMOVRdRm()
1306 setflags = BitIsSet(opcode, 20); in EmulateMOVRdRm()
1316 Rd = Bits32(opcode, 15, 12); in EmulateMOVRdRm()
1317 Rm = Bits32(opcode, 3, 0); in EmulateMOVRdRm()
1318 setflags = BitIsSet(opcode, 20); in EmulateMOVRdRm()
1323 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateMOVRdRm()
1353 bool EmulateInstructionARM::EmulateMOVRdImm(const uint32_t opcode, in EmulateMOVRdImm() argument
1373 if (ConditionPassed(opcode)) { in EmulateMOVRdImm()
1383 Rd = Bits32(opcode, 10, 8); in EmulateMOVRdImm()
1385 imm32 = Bits32(opcode, 7, 0); // imm32 = ZeroExtend(imm8, 32) in EmulateMOVRdImm()
1391 Rd = Bits32(opcode, 11, 8); in EmulateMOVRdImm()
1392 setflags = BitIsSet(opcode, 20); in EmulateMOVRdImm()
1393 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); in EmulateMOVRdImm()
1402 Rd = Bits32(opcode, 11, 8); in EmulateMOVRdImm()
1404 uint32_t imm4 = Bits32(opcode, 19, 16); in EmulateMOVRdImm()
1405 uint32_t imm3 = Bits32(opcode, 14, 12); in EmulateMOVRdImm()
1406 uint32_t i = Bit32(opcode, 26); in EmulateMOVRdImm()
1407 uint32_t imm8 = Bits32(opcode, 7, 0); in EmulateMOVRdImm()
1418 Rd = Bits32(opcode, 15, 12); in EmulateMOVRdImm()
1419 setflags = BitIsSet(opcode, 20); in EmulateMOVRdImm()
1420 imm32 = ARMExpandImm_C(opcode, APSR_C, carry); in EmulateMOVRdImm()
1425 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateMOVRdImm()
1431 Rd = Bits32(opcode, 15, 12); in EmulateMOVRdImm()
1433 uint32_t imm4 = Bits32(opcode, 19, 16); in EmulateMOVRdImm()
1434 uint32_t imm12 = Bits32(opcode, 11, 0); in EmulateMOVRdImm()
1466 bool EmulateInstructionARM::EmulateMUL(const uint32_t opcode, in EmulateMUL() argument
1484 if (ConditionPassed(opcode)) { in EmulateMUL()
1494 d = Bits32(opcode, 2, 0); in EmulateMUL()
1495 n = Bits32(opcode, 5, 3); in EmulateMUL()
1496 m = Bits32(opcode, 2, 0); in EmulateMUL()
1507 d = Bits32(opcode, 11, 8); in EmulateMUL()
1508 n = Bits32(opcode, 19, 16); in EmulateMUL()
1509 m = Bits32(opcode, 3, 0); in EmulateMUL()
1520 d = Bits32(opcode, 19, 16); in EmulateMUL()
1521 n = Bits32(opcode, 3, 0); in EmulateMUL()
1522 m = Bits32(opcode, 11, 8); in EmulateMUL()
1523 setflags = BitIsSet(opcode, 20); in EmulateMUL()
1595 bool EmulateInstructionARM::EmulateMVNImm(const uint32_t opcode, in EmulateMVNImm() argument
1615 if (ConditionPassed(opcode)) { in EmulateMVNImm()
1622 Rd = Bits32(opcode, 11, 8); in EmulateMVNImm()
1623 setflags = BitIsSet(opcode, 20); in EmulateMVNImm()
1624 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); in EmulateMVNImm()
1627 Rd = Bits32(opcode, 15, 12); in EmulateMVNImm()
1628 setflags = BitIsSet(opcode, 20); in EmulateMVNImm()
1629 imm32 = ARMExpandImm_C(opcode, APSR_C, carry); in EmulateMVNImm()
1634 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateMVNImm()
1655 bool EmulateInstructionARM::EmulateMVNReg(const uint32_t opcode, in EmulateMVNReg() argument
1676 if (ConditionPassed(opcode)) { in EmulateMVNReg()
1685 Rd = Bits32(opcode, 2, 0); in EmulateMVNReg()
1686 Rm = Bits32(opcode, 5, 3); in EmulateMVNReg()
1694 Rd = Bits32(opcode, 11, 8); in EmulateMVNReg()
1695 Rm = Bits32(opcode, 3, 0); in EmulateMVNReg()
1696 setflags = BitIsSet(opcode, 20); in EmulateMVNReg()
1697 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateMVNReg()
1703 Rd = Bits32(opcode, 15, 12); in EmulateMVNReg()
1704 Rm = Bits32(opcode, 3, 0); in EmulateMVNReg()
1705 setflags = BitIsSet(opcode, 20); in EmulateMVNReg()
1706 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateMVNReg()
1736 bool EmulateInstructionARM::EmulateLDRRtPCRelative(const uint32_t opcode, in EmulateLDRRtPCRelative() argument
1758 if (ConditionPassed(opcode)) { in EmulateLDRRtPCRelative()
1779 Rt = Bits32(opcode, 10, 8); in EmulateLDRRtPCRelative()
1780 imm32 = Bits32(opcode, 7, 0) << 2; // imm32 = ZeroExtend(imm8:'00', 32); in EmulateLDRRtPCRelative()
1784 Rt = Bits32(opcode, 15, 12); in EmulateLDRRtPCRelative()
1785 imm32 = Bits32(opcode, 11, 0) << 2; // imm32 = ZeroExtend(imm12, 32); in EmulateLDRRtPCRelative()
1786 add = BitIsSet(opcode, 23); in EmulateLDRRtPCRelative()
1824 bool EmulateInstructionARM::EmulateADDSPImm(const uint32_t opcode, in EmulateADDSPImm() argument
1846 if (ConditionPassed(opcode)) { in EmulateADDSPImm()
1856 d = Bits32(opcode, 10, 8); in EmulateADDSPImm()
1857 imm32 = (Bits32(opcode, 7, 0) << 2); in EmulateADDSPImm()
1864 imm32 = ThumbImm7Scaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32) in EmulateADDSPImm()
1871 d = Bits32(opcode, 11, 8); in EmulateADDSPImm()
1872 imm32 = ThumbExpandImm(opcode); in EmulateADDSPImm()
1873 setflags = Bit32(opcode, 20); in EmulateADDSPImm()
1887 d = Bits32(opcode, 11, 8); in EmulateADDSPImm()
1889 uint32_t i = Bit32(opcode, 26); in EmulateADDSPImm()
1890 uint32_t imm3 = Bits32(opcode, 14, 12); in EmulateADDSPImm()
1891 uint32_t imm8 = Bits32(opcode, 7, 0); in EmulateADDSPImm()
1935 bool EmulateInstructionARM::EmulateADDSPRm(const uint32_t opcode, in EmulateADDSPRm() argument
1958 if (ConditionPassed(opcode)) { in EmulateADDSPRm()
1965 Rm = Bits32(opcode, 6, 3); in EmulateADDSPRm()
1996 bool EmulateInstructionARM::EmulateBLXImmediate(const uint32_t opcode, in EmulateBLXImmediate() argument
2018 if (ConditionPassed(opcode)) { in EmulateBLXImmediate()
2030 uint32_t S = Bit32(opcode, 26); in EmulateBLXImmediate()
2031 uint32_t imm10 = Bits32(opcode, 25, 16); in EmulateBLXImmediate()
2032 uint32_t J1 = Bit32(opcode, 13); in EmulateBLXImmediate()
2033 uint32_t J2 = Bit32(opcode, 11); in EmulateBLXImmediate()
2034 uint32_t imm11 = Bits32(opcode, 10, 0); in EmulateBLXImmediate()
2049 uint32_t S = Bit32(opcode, 26); in EmulateBLXImmediate()
2050 uint32_t imm10H = Bits32(opcode, 25, 16); in EmulateBLXImmediate()
2051 uint32_t J1 = Bit32(opcode, 13); in EmulateBLXImmediate()
2052 uint32_t J2 = Bit32(opcode, 11); in EmulateBLXImmediate()
2053 uint32_t imm10L = Bits32(opcode, 10, 1); in EmulateBLXImmediate()
2068 imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2); in EmulateBLXImmediate()
2075 imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2 | in EmulateBLXImmediate()
2076 Bits32(opcode, 24, 24) << 1); in EmulateBLXImmediate()
2100 bool EmulateInstructionARM::EmulateBLXRm(const uint32_t opcode, in EmulateBLXRm() argument
2120 if (ConditionPassed(opcode)) { in EmulateBLXRm()
2131 Rm = Bits32(opcode, 6, 3); in EmulateBLXRm()
2140 Rm = Bits32(opcode, 3, 0); in EmulateBLXRm()
2165 bool EmulateInstructionARM::EmulateBXRm(const uint32_t opcode, in EmulateBXRm() argument
2176 if (ConditionPassed(opcode)) { in EmulateBXRm()
2182 Rm = Bits32(opcode, 6, 3); in EmulateBXRm()
2187 Rm = Bits32(opcode, 3, 0); in EmulateBXRm()
2213 bool EmulateInstructionARM::EmulateBXJRm(const uint32_t opcode, in EmulateBXJRm() argument
2230 if (ConditionPassed(opcode)) { in EmulateBXJRm()
2236 Rm = Bits32(opcode, 19, 16); in EmulateBXJRm()
2243 Rm = Bits32(opcode, 3, 0); in EmulateBXJRm()
2266 bool EmulateInstructionARM::EmulateSUBR7IPImm(const uint32_t opcode, in EmulateSUBR7IPImm() argument
2286 if (ConditionPassed(opcode)) { in EmulateSUBR7IPImm()
2294 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateSUBR7IPImm()
2316 bool EmulateInstructionARM::EmulateSUBIPSPImm(const uint32_t opcode, in EmulateSUBIPSPImm() argument
2336 if (ConditionPassed(opcode)) { in EmulateSUBIPSPImm()
2344 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateSUBIPSPImm()
2369 bool EmulateInstructionARM::EmulateSUBSPImm(const uint32_t opcode, in EmulateSUBSPImm() argument
2390 if (ConditionPassed(opcode)) { in EmulateSUBSPImm()
2402 imm32 = ThumbImm7Scaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32) in EmulateSUBSPImm()
2405 Rd = Bits32(opcode, 11, 8); in EmulateSUBSPImm()
2406 setflags = BitIsSet(opcode, 20); in EmulateSUBSPImm()
2407 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) in EmulateSUBSPImm()
2409 return EmulateCMPImm(opcode, eEncodingT2); in EmulateSUBSPImm()
2414 Rd = Bits32(opcode, 11, 8); in EmulateSUBSPImm()
2416 imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32) in EmulateSUBSPImm()
2421 Rd = Bits32(opcode, 15, 12); in EmulateSUBSPImm()
2422 setflags = BitIsSet(opcode, 20); in EmulateSUBSPImm()
2423 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateSUBSPImm()
2428 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateSUBSPImm()
2455 bool EmulateInstructionARM::EmulateSTRRtSP(const uint32_t opcode, in EmulateSTRRtSP() argument
2470 if (ConditionPassed(opcode)) { in EmulateSTRRtSP()
2485 Rt = Bits32(opcode, 15, 12); in EmulateSTRRtSP()
2486 imm12 = Bits32(opcode, 11, 0); in EmulateSTRRtSP()
2487 Rn = Bits32(opcode, 19, 16); in EmulateSTRRtSP()
2492 index = BitIsSet(opcode, 24); in EmulateSTRRtSP()
2493 add = BitIsSet(opcode, 23); in EmulateSTRRtSP()
2494 wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21)); in EmulateSTRRtSP()
2549 bool EmulateInstructionARM::EmulateVPUSH(const uint32_t opcode, in EmulateVPUSH() argument
2572 if (ConditionPassed(opcode)) { in EmulateVPUSH()
2585 d = Bit32(opcode, 22) << 4 | Bits32(opcode, 15, 12); in EmulateVPUSH()
2586 imm32 = Bits32(opcode, 7, 0) * addr_byte_size; in EmulateVPUSH()
2588 regs = Bits32(opcode, 7, 0) / 2; in EmulateVPUSH()
2596 d = Bits32(opcode, 15, 12) << 1 | Bit32(opcode, 22); in EmulateVPUSH()
2597 imm32 = Bits32(opcode, 7, 0) * addr_byte_size; in EmulateVPUSH()
2598 regs = Bits32(opcode, 7, 0); in EmulateVPUSH()
2642 bool EmulateInstructionARM::EmulateVPOP(const uint32_t opcode, in EmulateVPOP() argument
2664 if (ConditionPassed(opcode)) { in EmulateVPOP()
2677 d = Bit32(opcode, 22) << 4 | Bits32(opcode, 15, 12); in EmulateVPOP()
2678 imm32 = Bits32(opcode, 7, 0) * addr_byte_size; in EmulateVPOP()
2680 regs = Bits32(opcode, 7, 0) / 2; in EmulateVPOP()
2688 d = Bits32(opcode, 15, 12) << 1 | Bit32(opcode, 22); in EmulateVPOP()
2689 imm32 = Bits32(opcode, 7, 0) * addr_byte_size; in EmulateVPOP()
2690 regs = Bits32(opcode, 7, 0); in EmulateVPOP()
2733 bool EmulateInstructionARM::EmulateSVC(const uint32_t opcode, in EmulateSVC() argument
2746 if (ConditionPassed(opcode)) { in EmulateSVC()
2756 imm32 = Bits32(opcode, 7, 0); in EmulateSVC()
2761 imm32 = Bits32(opcode, 23, 0); in EmulateSVC()
2779 bool EmulateInstructionARM::EmulateIT(const uint32_t opcode, in EmulateIT() argument
2787 m_it_session.InitIT(Bits32(opcode, 7, 0)); in EmulateIT()
2791 bool EmulateInstructionARM::EmulateNop(const uint32_t opcode, in EmulateNop() argument
2798 bool EmulateInstructionARM::EmulateB(const uint32_t opcode, in EmulateB() argument
2811 if (ConditionPassed(opcode)) { in EmulateB()
2822 imm32 = llvm::SignExtend32<9>(Bits32(opcode, 7, 0) << 1); in EmulateB()
2827 imm32 = llvm::SignExtend32<12>(Bits32(opcode, 10, 0) << 1); in EmulateB()
2834 if (Bits32(opcode, 25, 23) == 7) in EmulateB()
2838 uint32_t S = Bit32(opcode, 26); in EmulateB()
2839 uint32_t imm6 = Bits32(opcode, 21, 16); in EmulateB()
2840 uint32_t J1 = Bit32(opcode, 13); in EmulateB()
2841 uint32_t J2 = Bit32(opcode, 11); in EmulateB()
2842 uint32_t imm11 = Bits32(opcode, 10, 0); in EmulateB()
2851 uint32_t S = Bit32(opcode, 26); in EmulateB()
2852 uint32_t imm10 = Bits32(opcode, 25, 16); in EmulateB()
2853 uint32_t J1 = Bit32(opcode, 13); in EmulateB()
2854 uint32_t J2 = Bit32(opcode, 11); in EmulateB()
2855 uint32_t imm11 = Bits32(opcode, 10, 0); in EmulateB()
2866 imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2); in EmulateB()
2882 bool EmulateInstructionARM::EmulateCB(const uint32_t opcode, in EmulateCB() argument
2894 uint32_t reg_val = ReadCoreReg(Bits32(opcode, 2, 0), &success); in EmulateCB()
2909 imm32 = Bit32(opcode, 9) << 6 | Bits32(opcode, 7, 3) << 1; in EmulateCB()
2910 nonzero = BitIsSet(opcode, 11); in EmulateCB()
2936 bool EmulateInstructionARM::EmulateTB(const uint32_t opcode, in EmulateTB() argument
2950 if (ConditionPassed(opcode)) { in EmulateTB()
2958 Rn = Bits32(opcode, 19, 16); in EmulateTB()
2959 Rm = Bits32(opcode, 3, 0); in EmulateTB()
2960 is_tbh = BitIsSet(opcode, 4); in EmulateTB()
3010 bool EmulateInstructionARM::EmulateADDImmThumb(const uint32_t opcode, in EmulateADDImmThumb() argument
3026 if (ConditionPassed(opcode)) { in EmulateADDImmThumb()
3038 d = Bits32(opcode, 2, 0); in EmulateADDImmThumb()
3039 n = Bits32(opcode, 5, 3); in EmulateADDImmThumb()
3041 imm32 = Bits32(opcode, 8, 6); in EmulateADDImmThumb()
3048 d = Bits32(opcode, 10, 8); in EmulateADDImmThumb()
3049 n = Bits32(opcode, 10, 8); in EmulateADDImmThumb()
3051 imm32 = Bits32(opcode, 7, 0); in EmulateADDImmThumb()
3059 d = Bits32(opcode, 11, 8); in EmulateADDImmThumb()
3060 n = Bits32(opcode, 19, 16); in EmulateADDImmThumb()
3061 setflags = BitIsSet(opcode, 20); in EmulateADDImmThumb()
3062 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry_out); in EmulateADDImmThumb()
3066 return EmulateADDSPImm(opcode, eEncodingT3); in EmulateADDImmThumb()
3078 d = Bits32(opcode, 11, 8); in EmulateADDImmThumb()
3079 n = Bits32(opcode, 19, 16); in EmulateADDImmThumb()
3081 uint32_t i = Bit32(opcode, 26); in EmulateADDImmThumb()
3082 uint32_t imm3 = Bits32(opcode, 14, 12); in EmulateADDImmThumb()
3083 uint32_t imm8 = Bits32(opcode, 7, 0); in EmulateADDImmThumb()
3088 return EmulateADDSPImm(opcode, eEncodingT4); in EmulateADDImmThumb()
3132 bool EmulateInstructionARM::EmulateADDImmARM(const uint32_t opcode, in EmulateADDImmARM() argument
3152 if (ConditionPassed(opcode)) { in EmulateADDImmARM()
3159 Rd = Bits32(opcode, 15, 12); in EmulateADDImmARM()
3160 Rn = Bits32(opcode, 19, 16); in EmulateADDImmARM()
3161 setflags = BitIsSet(opcode, 20); in EmulateADDImmARM()
3162 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateADDImmARM()
3197 bool EmulateInstructionARM::EmulateADDReg(const uint32_t opcode, in EmulateADDReg() argument
3218 if (ConditionPassed(opcode)) { in EmulateADDReg()
3225 Rd = Bits32(opcode, 2, 0); in EmulateADDReg()
3226 Rn = Bits32(opcode, 5, 3); in EmulateADDReg()
3227 Rm = Bits32(opcode, 8, 6); in EmulateADDReg()
3233 Rd = Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0); in EmulateADDReg()
3234 Rm = Bits32(opcode, 6, 3); in EmulateADDReg()
3244 Rd = Bits32(opcode, 15, 12); in EmulateADDReg()
3245 Rn = Bits32(opcode, 19, 16); in EmulateADDReg()
3246 Rm = Bits32(opcode, 3, 0); in EmulateADDReg()
3247 setflags = BitIsSet(opcode, 20); in EmulateADDReg()
3248 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateADDReg()
3286 bool EmulateInstructionARM::EmulateCMNImm(const uint32_t opcode, in EmulateCMNImm() argument
3305 Rn = Bits32(opcode, 19, 16); in EmulateCMNImm()
3306 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) in EmulateCMNImm()
3311 Rn = Bits32(opcode, 19, 16); in EmulateCMNImm()
3312 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateCMNImm()
3333 bool EmulateInstructionARM::EmulateCMNReg(const uint32_t opcode, in EmulateCMNReg() argument
3355 Rn = Bits32(opcode, 2, 0); in EmulateCMNReg()
3356 Rm = Bits32(opcode, 5, 3); in EmulateCMNReg()
3361 Rn = Bits32(opcode, 19, 16); in EmulateCMNReg()
3362 Rm = Bits32(opcode, 3, 0); in EmulateCMNReg()
3363 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateCMNReg()
3369 Rn = Bits32(opcode, 19, 16); in EmulateCMNReg()
3370 Rm = Bits32(opcode, 3, 0); in EmulateCMNReg()
3371 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateCMNReg()
3399 bool EmulateInstructionARM::EmulateCMPImm(const uint32_t opcode, in EmulateCMPImm() argument
3418 Rn = Bits32(opcode, 10, 8); in EmulateCMPImm()
3419 imm32 = Bits32(opcode, 7, 0); in EmulateCMPImm()
3422 Rn = Bits32(opcode, 19, 16); in EmulateCMPImm()
3423 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) in EmulateCMPImm()
3428 Rn = Bits32(opcode, 19, 16); in EmulateCMPImm()
3429 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateCMPImm()
3450 bool EmulateInstructionARM::EmulateCMPReg(const uint32_t opcode, in EmulateCMPReg() argument
3472 Rn = Bits32(opcode, 2, 0); in EmulateCMPReg()
3473 Rm = Bits32(opcode, 5, 3); in EmulateCMPReg()
3478 Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0); in EmulateCMPReg()
3479 Rm = Bits32(opcode, 6, 3); in EmulateCMPReg()
3488 Rn = Bits32(opcode, 19, 16); in EmulateCMPReg()
3489 Rm = Bits32(opcode, 3, 0); in EmulateCMPReg()
3490 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateCMPReg()
3495 Rn = Bits32(opcode, 19, 16); in EmulateCMPReg()
3496 Rm = Bits32(opcode, 3, 0); in EmulateCMPReg()
3497 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateCMPReg()
3527 bool EmulateInstructionARM::EmulateASRImm(const uint32_t opcode, in EmulateASRImm() argument
3545 return EmulateShiftImm(opcode, encoding, SRType_ASR); in EmulateASRImm()
3553 bool EmulateInstructionARM::EmulateASRReg(const uint32_t opcode, in EmulateASRReg() argument
3569 return EmulateShiftReg(opcode, encoding, SRType_ASR); in EmulateASRReg()
3575 bool EmulateInstructionARM::EmulateLSLImm(const uint32_t opcode, in EmulateLSLImm() argument
3593 return EmulateShiftImm(opcode, encoding, SRType_LSL); in EmulateLSLImm()
3600 bool EmulateInstructionARM::EmulateLSLReg(const uint32_t opcode, in EmulateLSLReg() argument
3616 return EmulateShiftReg(opcode, encoding, SRType_LSL); in EmulateLSLReg()
3623 bool EmulateInstructionARM::EmulateLSRImm(const uint32_t opcode, in EmulateLSRImm() argument
3641 return EmulateShiftImm(opcode, encoding, SRType_LSR); in EmulateLSRImm()
3648 bool EmulateInstructionARM::EmulateLSRReg(const uint32_t opcode, in EmulateLSRReg() argument
3664 return EmulateShiftReg(opcode, encoding, SRType_LSR); in EmulateLSRReg()
3671 bool EmulateInstructionARM::EmulateRORImm(const uint32_t opcode, in EmulateRORImm() argument
3689 return EmulateShiftImm(opcode, encoding, SRType_ROR); in EmulateRORImm()
3697 bool EmulateInstructionARM::EmulateRORReg(const uint32_t opcode, in EmulateRORReg() argument
3713 return EmulateShiftReg(opcode, encoding, SRType_ROR); in EmulateRORReg()
3721 bool EmulateInstructionARM::EmulateRRX(const uint32_t opcode, in EmulateRRX() argument
3739 return EmulateShiftImm(opcode, encoding, SRType_RRX); in EmulateRRX()
3742 bool EmulateInstructionARM::EmulateShiftImm(const uint32_t opcode, in EmulateShiftImm() argument
3753 if (ConditionPassed(opcode)) { in EmulateShiftImm()
3776 Rd = Bits32(opcode, 2, 0); in EmulateShiftImm()
3777 Rm = Bits32(opcode, 5, 3); in EmulateShiftImm()
3779 imm5 = Bits32(opcode, 10, 6); in EmulateShiftImm()
3787 Rd = Bits32(opcode, 11, 8); in EmulateShiftImm()
3788 Rm = Bits32(opcode, 3, 0); in EmulateShiftImm()
3789 setflags = BitIsSet(opcode, 20); in EmulateShiftImm()
3790 imm5 = Bits32(opcode, 14, 12) << 2 | Bits32(opcode, 7, 6); in EmulateShiftImm()
3795 Rd = Bits32(opcode, 15, 12); in EmulateShiftImm()
3796 Rm = Bits32(opcode, 3, 0); in EmulateShiftImm()
3797 setflags = BitIsSet(opcode, 20); in EmulateShiftImm()
3798 imm5 = Bits32(opcode, 11, 7); in EmulateShiftImm()
3832 bool EmulateInstructionARM::EmulateShiftReg(const uint32_t opcode, in EmulateShiftReg() argument
3842 if (ConditionPassed(opcode)) { in EmulateShiftReg()
3851 Rd = Bits32(opcode, 2, 0); in EmulateShiftReg()
3853 Rm = Bits32(opcode, 5, 3); in EmulateShiftReg()
3857 Rd = Bits32(opcode, 11, 8); in EmulateShiftReg()
3858 Rn = Bits32(opcode, 19, 16); in EmulateShiftReg()
3859 Rm = Bits32(opcode, 3, 0); in EmulateShiftReg()
3860 setflags = BitIsSet(opcode, 20); in EmulateShiftReg()
3865 Rd = Bits32(opcode, 15, 12); in EmulateShiftReg()
3866 Rn = Bits32(opcode, 3, 0); in EmulateShiftReg()
3867 Rm = Bits32(opcode, 11, 8); in EmulateShiftReg()
3868 setflags = BitIsSet(opcode, 20); in EmulateShiftReg()
3906 bool EmulateInstructionARM::EmulateLDM(const uint32_t opcode, in EmulateLDM() argument
3926 if (ConditionPassed(opcode)) { in EmulateLDM()
3935 n = Bits32(opcode, 10, 8); in EmulateLDM()
3936 registers = Bits32(opcode, 7, 0); in EmulateLDM()
3946 n = Bits32(opcode, 19, 16); in EmulateLDM()
3947 registers = Bits32(opcode, 15, 0); in EmulateLDM()
3949 wback = BitIsSet(opcode, 21); in EmulateLDM()
3954 (BitIsSet(opcode, 14) && BitIsSet(opcode, 15))) in EmulateLDM()
3968 n = Bits32(opcode, 19, 16); in EmulateLDM()
3969 registers = Bits32(opcode, 15, 0); in EmulateLDM()
3970 wback = BitIsSet(opcode, 21); in EmulateLDM()
4049 bool EmulateInstructionARM::EmulateLDMDA(const uint32_t opcode, in EmulateLDMDA() argument
4070 if (ConditionPassed(opcode)) { in EmulateLDMDA()
4080 n = Bits32(opcode, 19, 16); in EmulateLDMDA()
4081 registers = Bits32(opcode, 15, 0); in EmulateLDMDA()
4082 wback = BitIsSet(opcode, 21); in EmulateLDMDA()
4166 bool EmulateInstructionARM::EmulateLDMDB(const uint32_t opcode, in EmulateLDMDB() argument
4186 if (ConditionPassed(opcode)) { in EmulateLDMDB()
4194 n = Bits32(opcode, 19, 16); in EmulateLDMDB()
4195 registers = Bits32(opcode, 15, 0); in EmulateLDMDB()
4197 wback = BitIsSet(opcode, 21); in EmulateLDMDB()
4202 (BitIsSet(opcode, 14) && BitIsSet(opcode, 15))) in EmulateLDMDB()
4218 n = Bits32(opcode, 19, 16); in EmulateLDMDB()
4219 registers = Bits32(opcode, 15, 0); in EmulateLDMDB()
4220 wback = BitIsSet(opcode, 21); in EmulateLDMDB()
4305 bool EmulateInstructionARM::EmulateLDMIB(const uint32_t opcode, in EmulateLDMIB() argument
4324 if (ConditionPassed(opcode)) { in EmulateLDMIB()
4332 n = Bits32(opcode, 19, 16); in EmulateLDMIB()
4333 registers = Bits32(opcode, 15, 0); in EmulateLDMIB()
4334 wback = BitIsSet(opcode, 21); in EmulateLDMIB()
4417 bool EmulateInstructionARM::EmulateLDRRtRnImm(const uint32_t opcode, in EmulateLDRRtRnImm() argument
4438 if (ConditionPassed(opcode)) { in EmulateLDRRtRnImm()
4448 Rt = Bits32(opcode, 2, 0); in EmulateLDRRtRnImm()
4449 Rn = Bits32(opcode, 5, 3); in EmulateLDRRtRnImm()
4450 imm32 = Bits32(opcode, 10, 6) << 2; // imm32 = ZeroExtend(imm5:'00', 32); in EmulateLDRRtRnImm()
4460 Rt = Bits32(opcode, 10, 8); in EmulateLDRRtRnImm()
4462 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateLDRRtRnImm()
4474 Rt = Bits32(opcode, 15, 12); in EmulateLDRRtRnImm()
4475 Rn = Bits32(opcode, 19, 16); in EmulateLDRRtRnImm()
4476 imm32 = Bits32(opcode, 11, 0); in EmulateLDRRtRnImm()
4495 if (BitIsClear(opcode, 10) && BitIsClear(opcode, 8)) in EmulateLDRRtRnImm()
4499 Rt = Bits32(opcode, 15, 12); in EmulateLDRRtRnImm()
4500 Rn = Bits32(opcode, 19, 16); in EmulateLDRRtRnImm()
4501 imm32 = Bits32(opcode, 7, 0); in EmulateLDRRtRnImm()
4504 index = BitIsSet(opcode, 10); in EmulateLDRRtRnImm()
4505 add = BitIsSet(opcode, 9); in EmulateLDRRtRnImm()
4506 wback = BitIsSet(opcode, 8); in EmulateLDRRtRnImm()
4580 bool EmulateInstructionARM::EmulateSTM(const uint32_t opcode, in EmulateSTM() argument
4602 if (ConditionPassed(opcode)) { in EmulateSTM()
4612 n = Bits32(opcode, 10, 8); in EmulateSTM()
4613 registers = Bits32(opcode, 7, 0); in EmulateSTM()
4625 n = Bits32(opcode, 19, 16); in EmulateSTM()
4626 registers = Bits32(opcode, 15, 0); in EmulateSTM()
4628 wback = BitIsSet(opcode, 21); in EmulateSTM()
4642 n = Bits32(opcode, 19, 16); in EmulateSTM()
4643 registers = Bits32(opcode, 15, 0); in EmulateSTM()
4644 wback = BitIsSet(opcode, 21); in EmulateSTM()
4732 bool EmulateInstructionARM::EmulateSTMDA(const uint32_t opcode, in EmulateSTMDA() argument
4755 if (ConditionPassed(opcode)) { in EmulateSTMDA()
4765 n = Bits32(opcode, 19, 16); in EmulateSTMDA()
4766 registers = Bits32(opcode, 15, 0); in EmulateSTMDA()
4767 wback = BitIsSet(opcode, 21); in EmulateSTMDA()
4854 bool EmulateInstructionARM::EmulateSTMDB(const uint32_t opcode, in EmulateSTMDB() argument
4877 if (ConditionPassed(opcode)) { in EmulateSTMDB()
4887 if ((BitIsSet(opcode, 21)) && (Bits32(opcode, 19, 16) == 13)) { in EmulateSTMDB()
4891 n = Bits32(opcode, 19, 16); in EmulateSTMDB()
4892 registers = Bits32(opcode, 15, 0); in EmulateSTMDB()
4894 wback = BitIsSet(opcode, 21); in EmulateSTMDB()
4906 if (BitIsSet(opcode, 21) && (Bits32(opcode, 19, 16) == 13) && in EmulateSTMDB()
4907 BitCount(Bits32(opcode, 15, 0)) >= 2) { in EmulateSTMDB()
4911 n = Bits32(opcode, 19, 16); in EmulateSTMDB()
4912 registers = Bits32(opcode, 15, 0); in EmulateSTMDB()
4913 wback = BitIsSet(opcode, 21); in EmulateSTMDB()
5003 bool EmulateInstructionARM::EmulateSTMIB(const uint32_t opcode, in EmulateSTMIB() argument
5026 if (ConditionPassed(opcode)) { in EmulateSTMIB()
5036 n = Bits32(opcode, 19, 16); in EmulateSTMIB()
5037 registers = Bits32(opcode, 15, 0); in EmulateSTMIB()
5038 wback = BitIsSet(opcode, 21); in EmulateSTMIB()
5125 bool EmulateInstructionARM::EmulateSTRThumb(const uint32_t opcode, in EmulateSTRThumb() argument
5141 if (ConditionPassed(opcode)) { in EmulateSTRThumb()
5154 t = Bits32(opcode, 2, 0); in EmulateSTRThumb()
5155 n = Bits32(opcode, 5, 3); in EmulateSTRThumb()
5156 imm32 = Bits32(opcode, 10, 6) << 2; in EmulateSTRThumb()
5166 t = Bits32(opcode, 10, 8); in EmulateSTRThumb()
5168 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateSTRThumb()
5178 if (Bits32(opcode, 19, 16) == 15) in EmulateSTRThumb()
5182 t = Bits32(opcode, 15, 12); in EmulateSTRThumb()
5183 n = Bits32(opcode, 19, 16); in EmulateSTRThumb()
5184 imm32 = Bits32(opcode, 11, 0); in EmulateSTRThumb()
5201 if ((Bits32(opcode, 19, 16) == 15) || in EmulateSTRThumb()
5202 (BitIsClear(opcode, 10) && BitIsClear(opcode, 8))) in EmulateSTRThumb()
5206 t = Bits32(opcode, 15, 12); in EmulateSTRThumb()
5207 n = Bits32(opcode, 19, 16); in EmulateSTRThumb()
5208 imm32 = Bits32(opcode, 7, 0); in EmulateSTRThumb()
5211 index = BitIsSet(opcode, 10); in EmulateSTRThumb()
5212 add = BitIsSet(opcode, 9); in EmulateSTRThumb()
5213 wback = BitIsSet(opcode, 8); in EmulateSTRThumb()
5292 bool EmulateInstructionARM::EmulateSTRRegister(const uint32_t opcode, in EmulateSTRRegister() argument
5313 if (ConditionPassed(opcode)) { in EmulateSTRRegister()
5331 t = Bits32(opcode, 2, 0); in EmulateSTRRegister()
5332 n = Bits32(opcode, 5, 3); in EmulateSTRRegister()
5333 m = Bits32(opcode, 8, 6); in EmulateSTRRegister()
5347 if (Bits32(opcode, 19, 16) == 15) in EmulateSTRRegister()
5351 t = Bits32(opcode, 15, 12); in EmulateSTRRegister()
5352 n = Bits32(opcode, 19, 16); in EmulateSTRRegister()
5353 m = Bits32(opcode, 3, 0); in EmulateSTRRegister()
5362 shift_n = Bits32(opcode, 5, 4); in EmulateSTRRegister()
5372 t = Bits32(opcode, 15, 12); in EmulateSTRRegister()
5373 n = Bits32(opcode, 19, 16); in EmulateSTRRegister()
5374 m = Bits32(opcode, 3, 0); in EmulateSTRRegister()
5378 index = BitIsSet(opcode, 24); in EmulateSTRRegister()
5379 add = BitIsSet(opcode, 23); in EmulateSTRRegister()
5380 wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21)); in EmulateSTRRegister()
5383 uint32_t typ = Bits32(opcode, 6, 5); in EmulateSTRRegister()
5384 uint32_t imm5 = Bits32(opcode, 11, 7); in EmulateSTRRegister()
5482 bool EmulateInstructionARM::EmulateSTRBThumb(const uint32_t opcode, in EmulateSTRBThumb() argument
5495 if (ConditionPassed(opcode)) { in EmulateSTRBThumb()
5506 t = Bits32(opcode, 2, 0); in EmulateSTRBThumb()
5507 n = Bits32(opcode, 5, 3); in EmulateSTRBThumb()
5508 imm32 = Bits32(opcode, 10, 6); in EmulateSTRBThumb()
5518 if (Bits32(opcode, 19, 16) == 15) in EmulateSTRBThumb()
5522 t = Bits32(opcode, 15, 12); in EmulateSTRBThumb()
5523 n = Bits32(opcode, 19, 16); in EmulateSTRBThumb()
5524 imm32 = Bits32(opcode, 11, 0); in EmulateSTRBThumb()
5539 if (Bits32(opcode, 19, 16) == 15) in EmulateSTRBThumb()
5543 t = Bits32(opcode, 15, 12); in EmulateSTRBThumb()
5544 n = Bits32(opcode, 19, 16); in EmulateSTRBThumb()
5545 imm32 = Bits32(opcode, 7, 0); in EmulateSTRBThumb()
5548 index = BitIsSet(opcode, 10); in EmulateSTRBThumb()
5549 add = BitIsSet(opcode, 9); in EmulateSTRBThumb()
5550 wback = BitIsSet(opcode, 8); in EmulateSTRBThumb()
5619 bool EmulateInstructionARM::EmulateSTRHRegister(const uint32_t opcode, in EmulateSTRHRegister() argument
5636 if (ConditionPassed(opcode)) { in EmulateSTRHRegister()
5652 t = Bits32(opcode, 2, 0); in EmulateSTRHRegister()
5653 n = Bits32(opcode, 5, 3); in EmulateSTRHRegister()
5654 m = Bits32(opcode, 8, 6); in EmulateSTRHRegister()
5670 t = Bits32(opcode, 15, 12); in EmulateSTRHRegister()
5671 n = Bits32(opcode, 19, 16); in EmulateSTRHRegister()
5672 m = Bits32(opcode, 3, 0); in EmulateSTRHRegister()
5683 shift_n = Bits32(opcode, 5, 4); in EmulateSTRHRegister()
5694 t = Bits32(opcode, 15, 12); in EmulateSTRHRegister()
5695 n = Bits32(opcode, 19, 16); in EmulateSTRHRegister()
5696 m = Bits32(opcode, 3, 0); in EmulateSTRHRegister()
5700 index = BitIsSet(opcode, 24); in EmulateSTRHRegister()
5701 add = BitIsSet(opcode, 23); in EmulateSTRHRegister()
5702 wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21)); in EmulateSTRHRegister()
5797 bool EmulateInstructionARM::EmulateADCImm(const uint32_t opcode, in EmulateADCImm() argument
5817 if (ConditionPassed(opcode)) { in EmulateADCImm()
5824 Rd = Bits32(opcode, 11, 8); in EmulateADCImm()
5825 Rn = Bits32(opcode, 19, 16); in EmulateADCImm()
5826 setflags = BitIsSet(opcode, 20); in EmulateADCImm()
5827 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) in EmulateADCImm()
5832 Rd = Bits32(opcode, 15, 12); in EmulateADCImm()
5833 Rn = Bits32(opcode, 19, 16); in EmulateADCImm()
5834 setflags = BitIsSet(opcode, 20); in EmulateADCImm()
5835 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateADCImm()
5838 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateADCImm()
5866 bool EmulateInstructionARM::EmulateADCReg(const uint32_t opcode, in EmulateADCReg() argument
5887 if (ConditionPassed(opcode)) { in EmulateADCReg()
5894 Rd = Rn = Bits32(opcode, 2, 0); in EmulateADCReg()
5895 Rm = Bits32(opcode, 5, 3); in EmulateADCReg()
5901 Rd = Bits32(opcode, 11, 8); in EmulateADCReg()
5902 Rn = Bits32(opcode, 19, 16); in EmulateADCReg()
5903 Rm = Bits32(opcode, 3, 0); in EmulateADCReg()
5904 setflags = BitIsSet(opcode, 20); in EmulateADCReg()
5905 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateADCReg()
5910 Rd = Bits32(opcode, 15, 12); in EmulateADCReg()
5911 Rn = Bits32(opcode, 19, 16); in EmulateADCReg()
5912 Rm = Bits32(opcode, 3, 0); in EmulateADCReg()
5913 setflags = BitIsSet(opcode, 20); in EmulateADCReg()
5914 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateADCReg()
5917 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateADCReg()
5951 bool EmulateInstructionARM::EmulateADR(const uint32_t opcode, in EmulateADR() argument
5966 if (ConditionPassed(opcode)) { in EmulateADR()
5972 Rd = Bits32(opcode, 10, 8); in EmulateADR()
5973 imm32 = ThumbImm8Scaled(opcode); // imm32 = ZeroExtend(imm8:'00', 32) in EmulateADR()
5978 Rd = Bits32(opcode, 11, 8); in EmulateADR()
5979 imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32) in EmulateADR()
5980 add = (Bits32(opcode, 24, 21) == 0); // 0b0000 => ADD; 0b0101 => SUB in EmulateADR()
5986 Rd = Bits32(opcode, 15, 12); in EmulateADR()
5987 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateADR()
5988 add = (Bits32(opcode, 24, 21) == 0x4); // 0b0100 => ADD; 0b0010 => SUB in EmulateADR()
6014 bool EmulateInstructionARM::EmulateANDImm(const uint32_t opcode, in EmulateANDImm() argument
6034 if (ConditionPassed(opcode)) { in EmulateANDImm()
6042 Rd = Bits32(opcode, 11, 8); in EmulateANDImm()
6043 Rn = Bits32(opcode, 19, 16); in EmulateANDImm()
6044 setflags = BitIsSet(opcode, 20); in EmulateANDImm()
6046 opcode, APSR_C, in EmulateANDImm()
6050 return EmulateTSTImm(opcode, eEncodingT1); in EmulateANDImm()
6055 Rd = Bits32(opcode, 15, 12); in EmulateANDImm()
6056 Rn = Bits32(opcode, 19, 16); in EmulateANDImm()
6057 setflags = BitIsSet(opcode, 20); in EmulateANDImm()
6059 ARMExpandImm_C(opcode, APSR_C, in EmulateANDImm()
6063 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateANDImm()
6089 bool EmulateInstructionARM::EmulateANDReg(const uint32_t opcode, in EmulateANDReg() argument
6110 if (ConditionPassed(opcode)) { in EmulateANDReg()
6118 Rd = Rn = Bits32(opcode, 2, 0); in EmulateANDReg()
6119 Rm = Bits32(opcode, 5, 3); in EmulateANDReg()
6125 Rd = Bits32(opcode, 11, 8); in EmulateANDReg()
6126 Rn = Bits32(opcode, 19, 16); in EmulateANDReg()
6127 Rm = Bits32(opcode, 3, 0); in EmulateANDReg()
6128 setflags = BitIsSet(opcode, 20); in EmulateANDReg()
6129 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateANDReg()
6132 return EmulateTSTReg(opcode, eEncodingT2); in EmulateANDReg()
6137 Rd = Bits32(opcode, 15, 12); in EmulateANDReg()
6138 Rn = Bits32(opcode, 19, 16); in EmulateANDReg()
6139 Rm = Bits32(opcode, 3, 0); in EmulateANDReg()
6140 setflags = BitIsSet(opcode, 20); in EmulateANDReg()
6141 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateANDReg()
6144 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateANDReg()
6179 bool EmulateInstructionARM::EmulateBICImm(const uint32_t opcode, in EmulateBICImm() argument
6199 if (ConditionPassed(opcode)) { in EmulateBICImm()
6207 Rd = Bits32(opcode, 11, 8); in EmulateBICImm()
6208 Rn = Bits32(opcode, 19, 16); in EmulateBICImm()
6209 setflags = BitIsSet(opcode, 20); in EmulateBICImm()
6211 opcode, APSR_C, in EmulateBICImm()
6217 Rd = Bits32(opcode, 15, 12); in EmulateBICImm()
6218 Rn = Bits32(opcode, 19, 16); in EmulateBICImm()
6219 setflags = BitIsSet(opcode, 20); in EmulateBICImm()
6221 ARMExpandImm_C(opcode, APSR_C, in EmulateBICImm()
6227 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateBICImm()
6254 bool EmulateInstructionARM::EmulateBICReg(const uint32_t opcode, in EmulateBICReg() argument
6275 if (ConditionPassed(opcode)) { in EmulateBICReg()
6283 Rd = Rn = Bits32(opcode, 2, 0); in EmulateBICReg()
6284 Rm = Bits32(opcode, 5, 3); in EmulateBICReg()
6290 Rd = Bits32(opcode, 11, 8); in EmulateBICReg()
6291 Rn = Bits32(opcode, 19, 16); in EmulateBICReg()
6292 Rm = Bits32(opcode, 3, 0); in EmulateBICReg()
6293 setflags = BitIsSet(opcode, 20); in EmulateBICReg()
6294 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateBICReg()
6299 Rd = Bits32(opcode, 15, 12); in EmulateBICReg()
6300 Rn = Bits32(opcode, 19, 16); in EmulateBICReg()
6301 Rm = Bits32(opcode, 3, 0); in EmulateBICReg()
6302 setflags = BitIsSet(opcode, 20); in EmulateBICReg()
6303 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateBICReg()
6308 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateBICReg()
6343 bool EmulateInstructionARM::EmulateLDRImmediateARM(const uint32_t opcode, in EmulateLDRImmediateARM() argument
6362 if (ConditionPassed(opcode)) { in EmulateLDRImmediateARM()
6379 t = Bits32(opcode, 15, 12); in EmulateLDRImmediateARM()
6380 n = Bits32(opcode, 19, 16); in EmulateLDRImmediateARM()
6381 imm32 = Bits32(opcode, 11, 0); in EmulateLDRImmediateARM()
6385 index = BitIsSet(opcode, 24); in EmulateLDRImmediateARM()
6386 add = BitIsSet(opcode, 23); in EmulateLDRImmediateARM()
6387 wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21)); in EmulateLDRImmediateARM()
6480 bool EmulateInstructionARM::EmulateLDRRegister(const uint32_t opcode, in EmulateLDRRegister() argument
6503 if (ConditionPassed(opcode)) { in EmulateLDRRegister()
6520 t = Bits32(opcode, 2, 0); in EmulateLDRRegister()
6521 n = Bits32(opcode, 5, 3); in EmulateLDRRegister()
6522 m = Bits32(opcode, 8, 6); in EmulateLDRRegister()
6538 t = Bits32(opcode, 15, 12); in EmulateLDRRegister()
6539 n = Bits32(opcode, 19, 16); in EmulateLDRRegister()
6540 m = Bits32(opcode, 3, 0); in EmulateLDRRegister()
6549 shift_n = Bits32(opcode, 5, 4); in EmulateLDRRegister()
6564 t = Bits32(opcode, 15, 12); in EmulateLDRRegister()
6565 n = Bits32(opcode, 19, 16); in EmulateLDRRegister()
6566 m = Bits32(opcode, 3, 0); in EmulateLDRRegister()
6570 index = BitIsSet(opcode, 24); in EmulateLDRRegister()
6571 add = BitIsSet(opcode, 23); in EmulateLDRRegister()
6572 wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21)); in EmulateLDRRegister()
6575 uint32_t type = Bits32(opcode, 6, 5); in EmulateLDRRegister()
6576 uint32_t imm5 = Bits32(opcode, 11, 7); in EmulateLDRRegister()
6687 bool EmulateInstructionARM::EmulateLDRBImmediate(const uint32_t opcode, in EmulateLDRBImmediate() argument
6700 if (ConditionPassed(opcode)) { in EmulateLDRBImmediate()
6712 t = Bits32(opcode, 2, 0); in EmulateLDRBImmediate()
6713 n = Bits32(opcode, 5, 3); in EmulateLDRBImmediate()
6714 imm32 = Bits32(opcode, 10, 6); in EmulateLDRBImmediate()
6725 t = Bits32(opcode, 15, 12); in EmulateLDRBImmediate()
6726 n = Bits32(opcode, 19, 16); in EmulateLDRBImmediate()
6727 imm32 = Bits32(opcode, 11, 0); in EmulateLDRBImmediate()
6740 return EmulateLDRBLiteral(opcode, eEncodingT1); in EmulateLDRBImmediate()
6751 if (BitIsClear(opcode, 10) && BitIsClear(opcode, 8)) in EmulateLDRBImmediate()
6755 t = Bits32(opcode, 15, 12); in EmulateLDRBImmediate()
6756 n = Bits32(opcode, 19, 16); in EmulateLDRBImmediate()
6757 imm32 = Bits32(opcode, 7, 0); in EmulateLDRBImmediate()
6760 index = BitIsSet(opcode, 10); in EmulateLDRBImmediate()
6761 add = BitIsSet(opcode, 9); in EmulateLDRBImmediate()
6762 wback = BitIsSet(opcode, 8); in EmulateLDRBImmediate()
6770 return EmulateLDRBLiteral(opcode, eEncodingT1); in EmulateLDRBImmediate()
6834 bool EmulateInstructionARM::EmulateLDRBLiteral(const uint32_t opcode, in EmulateLDRBLiteral() argument
6846 if (ConditionPassed(opcode)) { in EmulateLDRBLiteral()
6853 t = Bits32(opcode, 15, 12); in EmulateLDRBLiteral()
6854 imm32 = Bits32(opcode, 11, 0); in EmulateLDRBLiteral()
6855 add = BitIsSet(opcode, 23); in EmulateLDRBLiteral()
6869 t = Bits32(opcode, 15, 12); in EmulateLDRBLiteral()
6870 imm32 = Bits32(opcode, 11, 0); in EmulateLDRBLiteral()
6871 add = BitIsSet(opcode, 23); in EmulateLDRBLiteral()
6915 bool EmulateInstructionARM::EmulateLDRBRegister(const uint32_t opcode, in EmulateLDRBRegister() argument
6929 if (ConditionPassed(opcode)) { in EmulateLDRBRegister()
6943 t = Bits32(opcode, 2, 0); in EmulateLDRBRegister()
6944 n = Bits32(opcode, 5, 3); in EmulateLDRBRegister()
6945 m = Bits32(opcode, 8, 6); in EmulateLDRBRegister()
6959 t = Bits32(opcode, 15, 12); in EmulateLDRBRegister()
6960 n = Bits32(opcode, 19, 16); in EmulateLDRBRegister()
6961 m = Bits32(opcode, 3, 0); in EmulateLDRBRegister()
6970 shift_n = Bits32(opcode, 5, 4); in EmulateLDRBRegister()
6978 return EmulateLDRBLiteral(opcode, eEncodingT1); in EmulateLDRBRegister()
6988 t = Bits32(opcode, 15, 12); in EmulateLDRBRegister()
6989 n = Bits32(opcode, 19, 16); in EmulateLDRBRegister()
6990 m = Bits32(opcode, 3, 0); in EmulateLDRBRegister()
6994 index = BitIsSet(opcode, 24); in EmulateLDRBRegister()
6995 add = BitIsSet(opcode, 23); in EmulateLDRBRegister()
6996 wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21)); in EmulateLDRBRegister()
6999 uint32_t type = Bits32(opcode, 6, 5); in EmulateLDRBRegister()
7000 uint32_t imm5 = Bits32(opcode, 11, 7); in EmulateLDRBRegister()
7077 bool EmulateInstructionARM::EmulateLDRHImmediate(const uint32_t opcode, in EmulateLDRHImmediate() argument
7094 if (ConditionPassed(opcode)) { in EmulateLDRHImmediate()
7106 t = Bits32(opcode, 2, 0); in EmulateLDRHImmediate()
7107 n = Bits32(opcode, 5, 3); in EmulateLDRHImmediate()
7108 imm32 = Bits32(opcode, 10, 6) << 1; in EmulateLDRHImmediate()
7121 t = Bits32(opcode, 15, 12); in EmulateLDRHImmediate()
7122 n = Bits32(opcode, 19, 16); in EmulateLDRHImmediate()
7123 imm32 = Bits32(opcode, 11, 0); in EmulateLDRHImmediate()
7141 if (BitIsClear(opcode, 10) && BitIsClear(opcode, 8)) in EmulateLDRHImmediate()
7145 t = Bits32(opcode, 15, 12); in EmulateLDRHImmediate()
7146 n = Bits32(opcode, 19, 16); in EmulateLDRHImmediate()
7147 imm32 = Bits32(opcode, 7, 0); in EmulateLDRHImmediate()
7150 index = BitIsSet(opcode, 10); in EmulateLDRHImmediate()
7151 add = BitIsSet(opcode, 9); in EmulateLDRHImmediate()
7152 wback = BitIsSet(opcode, 8); in EmulateLDRHImmediate()
7224 bool EmulateInstructionARM::EmulateLDRHLiteral(const uint32_t opcode, in EmulateLDRHLiteral() argument
7240 if (ConditionPassed(opcode)) { in EmulateLDRHLiteral()
7250 t = Bits32(opcode, 15, 12); in EmulateLDRHLiteral()
7251 imm32 = Bits32(opcode, 11, 0); in EmulateLDRHLiteral()
7252 add = BitIsSet(opcode, 23); in EmulateLDRHLiteral()
7261 uint32_t imm4H = Bits32(opcode, 11, 8); in EmulateLDRHLiteral()
7262 uint32_t imm4L = Bits32(opcode, 3, 0); in EmulateLDRHLiteral()
7265 t = Bits32(opcode, 15, 12); in EmulateLDRHLiteral()
7267 add = BitIsSet(opcode, 23); in EmulateLDRHLiteral()
7328 bool EmulateInstructionARM::EmulateLDRHRegister(const uint32_t opcode, in EmulateLDRHRegister() argument
7346 if (ConditionPassed(opcode)) { in EmulateLDRHRegister()
7362 t = Bits32(opcode, 2, 0); in EmulateLDRHRegister()
7363 n = Bits32(opcode, 5, 3); in EmulateLDRHRegister()
7364 m = Bits32(opcode, 8, 6); in EmulateLDRHRegister()
7381 t = Bits32(opcode, 15, 12); in EmulateLDRHRegister()
7382 n = Bits32(opcode, 19, 16); in EmulateLDRHRegister()
7383 m = Bits32(opcode, 3, 0); in EmulateLDRHRegister()
7392 shift_n = Bits32(opcode, 5, 4); in EmulateLDRHRegister()
7402 t = Bits32(opcode, 15, 12); in EmulateLDRHRegister()
7403 n = Bits32(opcode, 19, 16); in EmulateLDRHRegister()
7404 m = Bits32(opcode, 3, 0); in EmulateLDRHRegister()
7408 index = BitIsSet(opcode, 24); in EmulateLDRHRegister()
7409 add = BitIsSet(opcode, 23); in EmulateLDRHRegister()
7410 wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21)); in EmulateLDRHRegister()
7504 bool EmulateInstructionARM::EmulateLDRSBImmediate(const uint32_t opcode, in EmulateLDRSBImmediate() argument
7517 if (ConditionPassed(opcode)) { in EmulateLDRSBImmediate()
7531 t = Bits32(opcode, 15, 12); in EmulateLDRSBImmediate()
7532 n = Bits32(opcode, 19, 16); in EmulateLDRSBImmediate()
7533 imm32 = Bits32(opcode, 11, 0); in EmulateLDRSBImmediate()
7551 if (BitIsClear(opcode, 10) && BitIsClear(opcode, 8)) in EmulateLDRSBImmediate()
7555 t = Bits32(opcode, 15, 12); in EmulateLDRSBImmediate()
7556 n = Bits32(opcode, 19, 16); in EmulateLDRSBImmediate()
7557 imm32 = Bits32(opcode, 7, 0); in EmulateLDRSBImmediate()
7560 index = BitIsSet(opcode, 10); in EmulateLDRSBImmediate()
7561 add = BitIsSet(opcode, 9); in EmulateLDRSBImmediate()
7562 wback = BitIsSet(opcode, 8); in EmulateLDRSBImmediate()
7566 ((t == 15) && (BitIsClear(opcode, 10) || BitIsSet(opcode, 9) || in EmulateLDRSBImmediate()
7567 BitIsSet(opcode, 8)))) || in EmulateLDRSBImmediate()
7577 t = Bits32(opcode, 15, 12); in EmulateLDRSBImmediate()
7578 n = Bits32(opcode, 19, 16); in EmulateLDRSBImmediate()
7580 uint32_t imm4H = Bits32(opcode, 11, 8); in EmulateLDRSBImmediate()
7581 uint32_t imm4L = Bits32(opcode, 3, 0); in EmulateLDRSBImmediate()
7586 index = BitIsSet(opcode, 24); in EmulateLDRSBImmediate()
7587 add = BitIsSet(opcode, 23); in EmulateLDRSBImmediate()
7588 wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21)); in EmulateLDRSBImmediate()
7653 bool EmulateInstructionARM::EmulateLDRSBLiteral(const uint32_t opcode, in EmulateLDRSBLiteral() argument
7665 if (ConditionPassed(opcode)) { in EmulateLDRSBLiteral()
7675 t = Bits32(opcode, 15, 12); in EmulateLDRSBLiteral()
7676 imm32 = Bits32(opcode, 11, 0); in EmulateLDRSBLiteral()
7677 add = BitIsSet(opcode, 23); in EmulateLDRSBLiteral()
7687 t = Bits32(opcode, 15, 12); in EmulateLDRSBLiteral()
7688 uint32_t imm4H = Bits32(opcode, 11, 8); in EmulateLDRSBLiteral()
7689 uint32_t imm4L = Bits32(opcode, 3, 0); in EmulateLDRSBLiteral()
7691 add = BitIsSet(opcode, 23); in EmulateLDRSBLiteral()
7741 bool EmulateInstructionARM::EmulateLDRSBRegister(const uint32_t opcode, in EmulateLDRSBRegister() argument
7755 if (ConditionPassed(opcode)) { in EmulateLDRSBRegister()
7769 t = Bits32(opcode, 2, 0); in EmulateLDRSBRegister()
7770 n = Bits32(opcode, 5, 3); in EmulateLDRSBRegister()
7771 m = Bits32(opcode, 8, 6); in EmulateLDRSBRegister()
7788 t = Bits32(opcode, 15, 12); in EmulateLDRSBRegister()
7789 n = Bits32(opcode, 19, 16); in EmulateLDRSBRegister()
7790 m = Bits32(opcode, 3, 0); in EmulateLDRSBRegister()
7799 shift_n = Bits32(opcode, 5, 4); in EmulateLDRSBRegister()
7809 t = Bits32(opcode, 15, 12); in EmulateLDRSBRegister()
7810 n = Bits32(opcode, 19, 16); in EmulateLDRSBRegister()
7811 m = Bits32(opcode, 3, 0); in EmulateLDRSBRegister()
7815 index = BitIsSet(opcode, 24); in EmulateLDRSBRegister()
7816 add = BitIsSet(opcode, 23); in EmulateLDRSBRegister()
7817 wback = BitIsClear(opcode, 24) || BitIsSet(opcode, 21); in EmulateLDRSBRegister()
7901 bool EmulateInstructionARM::EmulateLDRSHImmediate(const uint32_t opcode, in EmulateLDRSHImmediate() argument
7918 if (ConditionPassed(opcode)) { in EmulateLDRSHImmediate()
7932 t = Bits32(opcode, 15, 12); in EmulateLDRSHImmediate()
7933 n = Bits32(opcode, 19, 16); in EmulateLDRSHImmediate()
7934 imm32 = Bits32(opcode, 11, 0); in EmulateLDRSHImmediate()
7953 if (BitIsClear(opcode, 10) && BitIsClear(opcode, 8)) in EmulateLDRSHImmediate()
7957 t = Bits32(opcode, 15, 12); in EmulateLDRSHImmediate()
7958 n = Bits32(opcode, 19, 16); in EmulateLDRSHImmediate()
7959 imm32 = Bits32(opcode, 7, 0); in EmulateLDRSHImmediate()
7962 index = BitIsSet(opcode, 10); in EmulateLDRSHImmediate()
7963 add = BitIsSet(opcode, 9); in EmulateLDRSHImmediate()
7964 wback = BitIsSet(opcode, 8); in EmulateLDRSHImmediate()
7976 t = Bits32(opcode, 15, 12); in EmulateLDRSHImmediate()
7977 n = Bits32(opcode, 19, 16); in EmulateLDRSHImmediate()
7978 uint32_t imm4H = Bits32(opcode, 11, 8); in EmulateLDRSHImmediate()
7979 uint32_t imm4L = Bits32(opcode, 3, 0); in EmulateLDRSHImmediate()
7984 index = BitIsSet(opcode, 24); in EmulateLDRSHImmediate()
7985 add = BitIsSet(opcode, 23); in EmulateLDRSHImmediate()
7986 wback = BitIsClear(opcode, 24) || BitIsSet(opcode, 21); in EmulateLDRSHImmediate()
8060 bool EmulateInstructionARM::EmulateLDRSHLiteral(const uint32_t opcode, in EmulateLDRSHLiteral() argument
8076 if (ConditionPassed(opcode)) { in EmulateLDRSHLiteral()
8086 t = Bits32(opcode, 15, 12); in EmulateLDRSHLiteral()
8087 imm32 = Bits32(opcode, 11, 0); in EmulateLDRSHLiteral()
8088 add = BitIsSet(opcode, 23); in EmulateLDRSHLiteral()
8098 t = Bits32(opcode, 15, 12); in EmulateLDRSHLiteral()
8099 uint32_t imm4H = Bits32(opcode, 11, 8); in EmulateLDRSHLiteral()
8100 uint32_t imm4L = Bits32(opcode, 3, 0); in EmulateLDRSHLiteral()
8102 add = BitIsSet(opcode, 23); in EmulateLDRSHLiteral()
8161 bool EmulateInstructionARM::EmulateLDRSHRegister(const uint32_t opcode, in EmulateLDRSHRegister() argument
8179 if (ConditionPassed(opcode)) { in EmulateLDRSHRegister()
8195 t = Bits32(opcode, 2, 0); in EmulateLDRSHRegister()
8196 n = Bits32(opcode, 5, 3); in EmulateLDRSHRegister()
8197 m = Bits32(opcode, 8, 6); in EmulateLDRSHRegister()
8214 t = Bits32(opcode, 15, 12); in EmulateLDRSHRegister()
8215 n = Bits32(opcode, 19, 16); in EmulateLDRSHRegister()
8216 m = Bits32(opcode, 3, 0); in EmulateLDRSHRegister()
8225 shift_n = Bits32(opcode, 5, 4); in EmulateLDRSHRegister()
8236 t = Bits32(opcode, 15, 12); in EmulateLDRSHRegister()
8237 n = Bits32(opcode, 19, 16); in EmulateLDRSHRegister()
8238 m = Bits32(opcode, 3, 0); in EmulateLDRSHRegister()
8242 index = BitIsSet(opcode, 24); in EmulateLDRSHRegister()
8243 add = BitIsSet(opcode, 23); in EmulateLDRSHRegister()
8244 wback = BitIsClear(opcode, 24) || BitIsSet(opcode, 21); in EmulateLDRSHRegister()
8341 bool EmulateInstructionARM::EmulateSXTB(const uint32_t opcode, in EmulateSXTB() argument
8352 if (ConditionPassed(opcode)) { in EmulateSXTB()
8361 d = Bits32(opcode, 2, 0); in EmulateSXTB()
8362 m = Bits32(opcode, 5, 3); in EmulateSXTB()
8369 d = Bits32(opcode, 11, 8); in EmulateSXTB()
8370 m = Bits32(opcode, 3, 0); in EmulateSXTB()
8371 rotation = Bits32(opcode, 5, 4) << 3; in EmulateSXTB()
8381 d = Bits32(opcode, 15, 12); in EmulateSXTB()
8382 m = Bits32(opcode, 3, 0); in EmulateSXTB()
8383 rotation = Bits32(opcode, 11, 10) << 3; in EmulateSXTB()
8426 bool EmulateInstructionARM::EmulateSXTH(const uint32_t opcode, in EmulateSXTH() argument
8437 if (ConditionPassed(opcode)) { in EmulateSXTH()
8446 d = Bits32(opcode, 2, 0); in EmulateSXTH()
8447 m = Bits32(opcode, 5, 3); in EmulateSXTH()
8454 d = Bits32(opcode, 11, 8); in EmulateSXTH()
8455 m = Bits32(opcode, 3, 0); in EmulateSXTH()
8456 rotation = Bits32(opcode, 5, 4) << 3; in EmulateSXTH()
8466 d = Bits32(opcode, 15, 12); in EmulateSXTH()
8467 m = Bits32(opcode, 3, 0); in EmulateSXTH()
8468 rotation = Bits32(opcode, 11, 10) << 3; in EmulateSXTH()
8511 bool EmulateInstructionARM::EmulateUXTB(const uint32_t opcode, in EmulateUXTB() argument
8522 if (ConditionPassed(opcode)) { in EmulateUXTB()
8531 d = Bits32(opcode, 2, 0); in EmulateUXTB()
8532 m = Bits32(opcode, 5, 3); in EmulateUXTB()
8539 d = Bits32(opcode, 11, 8); in EmulateUXTB()
8540 m = Bits32(opcode, 3, 0); in EmulateUXTB()
8541 rotation = Bits32(opcode, 5, 4) << 3; in EmulateUXTB()
8551 d = Bits32(opcode, 15, 12); in EmulateUXTB()
8552 m = Bits32(opcode, 3, 0); in EmulateUXTB()
8553 rotation = Bits32(opcode, 11, 10) << 3; in EmulateUXTB()
8594 bool EmulateInstructionARM::EmulateUXTH(const uint32_t opcode, in EmulateUXTH() argument
8605 if (ConditionPassed(opcode)) { in EmulateUXTH()
8613 d = Bits32(opcode, 2, 0); in EmulateUXTH()
8614 m = Bits32(opcode, 5, 3); in EmulateUXTH()
8621 d = Bits32(opcode, 11, 8); in EmulateUXTH()
8622 m = Bits32(opcode, 3, 0); in EmulateUXTH()
8623 rotation = Bits32(opcode, 5, 4) << 3; in EmulateUXTH()
8633 d = Bits32(opcode, 15, 12); in EmulateUXTH()
8634 m = Bits32(opcode, 3, 0); in EmulateUXTH()
8635 rotation = Bits32(opcode, 11, 10) << 3; in EmulateUXTH()
8675 bool EmulateInstructionARM::EmulateRFE(const uint32_t opcode, in EmulateRFE() argument
8692 if (ConditionPassed(opcode)) { in EmulateRFE()
8703 n = Bits32(opcode, 19, 16); in EmulateRFE()
8704 wback = BitIsSet(opcode, 21); in EmulateRFE()
8720 n = Bits32(opcode, 19, 16); in EmulateRFE()
8721 wback = BitIsSet(opcode, 21); in EmulateRFE()
8737 n = Bits32(opcode, 19, 16); in EmulateRFE()
8740 wback = BitIsSet(opcode, 21); in EmulateRFE()
8741 increment = BitIsSet(opcode, 23); in EmulateRFE()
8742 wordhigher = (Bit32(opcode, 24) == Bit32(opcode, 23)); in EmulateRFE()
8821 bool EmulateInstructionARM::EmulateEORImm(const uint32_t opcode, in EmulateEORImm() argument
8841 if (ConditionPassed(opcode)) { in EmulateEORImm()
8849 Rd = Bits32(opcode, 11, 8); in EmulateEORImm()
8850 Rn = Bits32(opcode, 19, 16); in EmulateEORImm()
8851 setflags = BitIsSet(opcode, 20); in EmulateEORImm()
8853 opcode, APSR_C, in EmulateEORImm()
8857 return EmulateTEQImm(opcode, eEncodingT1); in EmulateEORImm()
8862 Rd = Bits32(opcode, 15, 12); in EmulateEORImm()
8863 Rn = Bits32(opcode, 19, 16); in EmulateEORImm()
8864 setflags = BitIsSet(opcode, 20); in EmulateEORImm()
8866 ARMExpandImm_C(opcode, APSR_C, in EmulateEORImm()
8872 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateEORImm()
8899 bool EmulateInstructionARM::EmulateEORReg(const uint32_t opcode, in EmulateEORReg() argument
8920 if (ConditionPassed(opcode)) { in EmulateEORReg()
8928 Rd = Rn = Bits32(opcode, 2, 0); in EmulateEORReg()
8929 Rm = Bits32(opcode, 5, 3); in EmulateEORReg()
8935 Rd = Bits32(opcode, 11, 8); in EmulateEORReg()
8936 Rn = Bits32(opcode, 19, 16); in EmulateEORReg()
8937 Rm = Bits32(opcode, 3, 0); in EmulateEORReg()
8938 setflags = BitIsSet(opcode, 20); in EmulateEORReg()
8939 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateEORReg()
8942 return EmulateTEQReg(opcode, eEncodingT1); in EmulateEORReg()
8947 Rd = Bits32(opcode, 15, 12); in EmulateEORReg()
8948 Rn = Bits32(opcode, 19, 16); in EmulateEORReg()
8949 Rm = Bits32(opcode, 3, 0); in EmulateEORReg()
8950 setflags = BitIsSet(opcode, 20); in EmulateEORReg()
8951 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateEORReg()
8956 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateEORReg()
8990 bool EmulateInstructionARM::EmulateORRImm(const uint32_t opcode, in EmulateORRImm() argument
9010 if (ConditionPassed(opcode)) { in EmulateORRImm()
9018 Rd = Bits32(opcode, 11, 8); in EmulateORRImm()
9019 Rn = Bits32(opcode, 19, 16); in EmulateORRImm()
9020 setflags = BitIsSet(opcode, 20); in EmulateORRImm()
9022 opcode, APSR_C, in EmulateORRImm()
9026 return EmulateMOVRdImm(opcode, eEncodingT2); in EmulateORRImm()
9031 Rd = Bits32(opcode, 15, 12); in EmulateORRImm()
9032 Rn = Bits32(opcode, 19, 16); in EmulateORRImm()
9033 setflags = BitIsSet(opcode, 20); in EmulateORRImm()
9035 ARMExpandImm_C(opcode, APSR_C, in EmulateORRImm()
9039 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateORRImm()
9066 bool EmulateInstructionARM::EmulateORRReg(const uint32_t opcode, in EmulateORRReg() argument
9087 if (ConditionPassed(opcode)) { in EmulateORRReg()
9095 Rd = Rn = Bits32(opcode, 2, 0); in EmulateORRReg()
9096 Rm = Bits32(opcode, 5, 3); in EmulateORRReg()
9102 Rd = Bits32(opcode, 11, 8); in EmulateORRReg()
9103 Rn = Bits32(opcode, 19, 16); in EmulateORRReg()
9104 Rm = Bits32(opcode, 3, 0); in EmulateORRReg()
9105 setflags = BitIsSet(opcode, 20); in EmulateORRReg()
9106 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateORRReg()
9109 return EmulateMOVRdRm(opcode, eEncodingT3); in EmulateORRReg()
9114 Rd = Bits32(opcode, 15, 12); in EmulateORRReg()
9115 Rn = Bits32(opcode, 19, 16); in EmulateORRReg()
9116 Rm = Bits32(opcode, 3, 0); in EmulateORRReg()
9117 setflags = BitIsSet(opcode, 20); in EmulateORRReg()
9118 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateORRReg()
9121 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateORRReg()
9155 bool EmulateInstructionARM::EmulateRSBImm(const uint32_t opcode, in EmulateRSBImm() argument
9182 Rd = Bits32(opcode, 2, 0); in EmulateRSBImm()
9183 Rn = Bits32(opcode, 5, 3); in EmulateRSBImm()
9188 Rd = Bits32(opcode, 11, 8); in EmulateRSBImm()
9189 Rn = Bits32(opcode, 19, 16); in EmulateRSBImm()
9190 setflags = BitIsSet(opcode, 20); in EmulateRSBImm()
9191 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) in EmulateRSBImm()
9196 Rd = Bits32(opcode, 15, 12); in EmulateRSBImm()
9197 Rn = Bits32(opcode, 19, 16); in EmulateRSBImm()
9198 setflags = BitIsSet(opcode, 20); in EmulateRSBImm()
9199 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateRSBImm()
9204 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateRSBImm()
9227 bool EmulateInstructionARM::EmulateRSBReg(const uint32_t opcode, in EmulateRSBReg() argument
9256 Rd = Bits32(opcode, 11, 8); in EmulateRSBReg()
9257 Rn = Bits32(opcode, 19, 16); in EmulateRSBReg()
9258 Rm = Bits32(opcode, 3, 0); in EmulateRSBReg()
9259 setflags = BitIsSet(opcode, 20); in EmulateRSBReg()
9260 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateRSBReg()
9266 Rd = Bits32(opcode, 15, 12); in EmulateRSBReg()
9267 Rn = Bits32(opcode, 19, 16); in EmulateRSBReg()
9268 Rm = Bits32(opcode, 3, 0); in EmulateRSBReg()
9269 setflags = BitIsSet(opcode, 20); in EmulateRSBReg()
9270 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateRSBReg()
9275 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateRSBReg()
9306 bool EmulateInstructionARM::EmulateRSCImm(const uint32_t opcode, in EmulateRSCImm() argument
9333 Rd = Bits32(opcode, 15, 12); in EmulateRSCImm()
9334 Rn = Bits32(opcode, 19, 16); in EmulateRSCImm()
9335 setflags = BitIsSet(opcode, 20); in EmulateRSCImm()
9336 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateRSCImm()
9341 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateRSCImm()
9365 bool EmulateInstructionARM::EmulateRSCReg(const uint32_t opcode, in EmulateRSCReg() argument
9394 Rd = Bits32(opcode, 15, 12); in EmulateRSCReg()
9395 Rn = Bits32(opcode, 19, 16); in EmulateRSCReg()
9396 Rm = Bits32(opcode, 3, 0); in EmulateRSCReg()
9397 setflags = BitIsSet(opcode, 20); in EmulateRSCReg()
9398 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateRSCReg()
9403 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateRSCReg()
9435 bool EmulateInstructionARM::EmulateSBCImm(const uint32_t opcode, in EmulateSBCImm() argument
9462 Rd = Bits32(opcode, 11, 8); in EmulateSBCImm()
9463 Rn = Bits32(opcode, 19, 16); in EmulateSBCImm()
9464 setflags = BitIsSet(opcode, 20); in EmulateSBCImm()
9465 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) in EmulateSBCImm()
9470 Rd = Bits32(opcode, 15, 12); in EmulateSBCImm()
9471 Rn = Bits32(opcode, 19, 16); in EmulateSBCImm()
9472 setflags = BitIsSet(opcode, 20); in EmulateSBCImm()
9473 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateSBCImm()
9478 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateSBCImm()
9503 bool EmulateInstructionARM::EmulateSBCReg(const uint32_t opcode, in EmulateSBCReg() argument
9532 Rd = Rn = Bits32(opcode, 2, 0); in EmulateSBCReg()
9533 Rm = Bits32(opcode, 5, 3); in EmulateSBCReg()
9539 Rd = Bits32(opcode, 11, 8); in EmulateSBCReg()
9540 Rn = Bits32(opcode, 19, 16); in EmulateSBCReg()
9541 Rm = Bits32(opcode, 3, 0); in EmulateSBCReg()
9542 setflags = BitIsSet(opcode, 20); in EmulateSBCReg()
9543 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateSBCReg()
9548 Rd = Bits32(opcode, 15, 12); in EmulateSBCReg()
9549 Rn = Bits32(opcode, 19, 16); in EmulateSBCReg()
9550 Rm = Bits32(opcode, 3, 0); in EmulateSBCReg()
9551 setflags = BitIsSet(opcode, 20); in EmulateSBCReg()
9552 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateSBCReg()
9557 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateSBCReg()
9587 bool EmulateInstructionARM::EmulateSUBImmThumb(const uint32_t opcode, in EmulateSUBImmThumb() argument
9611 Rd = Bits32(opcode, 2, 0); in EmulateSUBImmThumb()
9612 Rn = Bits32(opcode, 5, 3); in EmulateSUBImmThumb()
9614 imm32 = Bits32(opcode, 8, 6); // imm32 = ZeroExtend(imm3, 32) in EmulateSUBImmThumb()
9617 Rd = Rn = Bits32(opcode, 10, 8); in EmulateSUBImmThumb()
9619 imm32 = Bits32(opcode, 7, 0); // imm32 = ZeroExtend(imm8, 32) in EmulateSUBImmThumb()
9622 Rd = Bits32(opcode, 11, 8); in EmulateSUBImmThumb()
9623 Rn = Bits32(opcode, 19, 16); in EmulateSUBImmThumb()
9624 setflags = BitIsSet(opcode, 20); in EmulateSUBImmThumb()
9625 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8) in EmulateSUBImmThumb()
9629 return EmulateCMPImm(opcode, eEncodingT2); in EmulateSUBImmThumb()
9633 return EmulateSUBSPImm(opcode, eEncodingT2); in EmulateSUBImmThumb()
9640 Rd = Bits32(opcode, 11, 8); in EmulateSUBImmThumb()
9641 Rn = Bits32(opcode, 19, 16); in EmulateSUBImmThumb()
9642 setflags = BitIsSet(opcode, 20); in EmulateSUBImmThumb()
9643 imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32) in EmulateSUBImmThumb()
9647 return EmulateADR(opcode, eEncodingT2); in EmulateSUBImmThumb()
9651 return EmulateSUBSPImm(opcode, eEncodingT3); in EmulateSUBImmThumb()
9677 bool EmulateInstructionARM::EmulateSUBImmARM(const uint32_t opcode, in EmulateSUBImmARM() argument
9697 if (ConditionPassed(opcode)) { in EmulateSUBImmARM()
9705 Rd = Bits32(opcode, 15, 12); in EmulateSUBImmARM()
9706 Rn = Bits32(opcode, 19, 16); in EmulateSUBImmARM()
9707 setflags = BitIsSet(opcode, 20); in EmulateSUBImmARM()
9708 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateSUBImmARM()
9712 return EmulateADR(opcode, eEncodingA2); in EmulateSUBImmARM()
9716 return EmulateSUBSPImm(opcode, eEncodingA1); in EmulateSUBImmARM()
9721 return EmulateSUBSPcLrEtc(opcode, encoding); in EmulateSUBImmARM()
9754 bool EmulateInstructionARM::EmulateTEQImm(const uint32_t opcode, in EmulateTEQImm() argument
9769 if (ConditionPassed(opcode)) { in EmulateTEQImm()
9776 Rn = Bits32(opcode, 19, 16); in EmulateTEQImm()
9778 opcode, APSR_C, in EmulateTEQImm()
9784 Rn = Bits32(opcode, 19, 16); in EmulateTEQImm()
9786 ARMExpandImm_C(opcode, APSR_C, in EmulateTEQImm()
9813 bool EmulateInstructionARM::EmulateTEQReg(const uint32_t opcode, in EmulateTEQReg() argument
9829 if (ConditionPassed(opcode)) { in EmulateTEQReg()
9836 Rn = Bits32(opcode, 19, 16); in EmulateTEQReg()
9837 Rm = Bits32(opcode, 3, 0); in EmulateTEQReg()
9838 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateTEQReg()
9843 Rn = Bits32(opcode, 19, 16); in EmulateTEQReg()
9844 Rm = Bits32(opcode, 3, 0); in EmulateTEQReg()
9845 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateTEQReg()
9879 bool EmulateInstructionARM::EmulateTSTImm(const uint32_t opcode, in EmulateTSTImm() argument
9894 if (ConditionPassed(opcode)) { in EmulateTSTImm()
9901 Rn = Bits32(opcode, 19, 16); in EmulateTSTImm()
9903 opcode, APSR_C, in EmulateTSTImm()
9909 Rn = Bits32(opcode, 19, 16); in EmulateTSTImm()
9911 ARMExpandImm_C(opcode, APSR_C, in EmulateTSTImm()
9938 bool EmulateInstructionARM::EmulateTSTReg(const uint32_t opcode, in EmulateTSTReg() argument
9954 if (ConditionPassed(opcode)) { in EmulateTSTReg()
9961 Rn = Bits32(opcode, 2, 0); in EmulateTSTReg()
9962 Rm = Bits32(opcode, 5, 3); in EmulateTSTReg()
9967 Rn = Bits32(opcode, 19, 16); in EmulateTSTReg()
9968 Rm = Bits32(opcode, 3, 0); in EmulateTSTReg()
9969 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateTSTReg()
9974 Rn = Bits32(opcode, 19, 16); in EmulateTSTReg()
9975 Rm = Bits32(opcode, 3, 0); in EmulateTSTReg()
9976 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateTSTReg()
10008 bool EmulateInstructionARM::EmulateSUBSPReg(const uint32_t opcode, in EmulateSUBSPReg() argument
10028 if (ConditionPassed(opcode)) { in EmulateSUBSPReg()
10038 d = Bits32(opcode, 11, 8); in EmulateSUBSPReg()
10039 m = Bits32(opcode, 3, 0); in EmulateSUBSPReg()
10040 setflags = BitIsSet(opcode, 20); in EmulateSUBSPReg()
10043 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateSUBSPReg()
10057 d = Bits32(opcode, 15, 12); in EmulateSUBSPReg()
10058 m = Bits32(opcode, 3, 0); in EmulateSUBSPReg()
10059 setflags = BitIsSet(opcode, 20); in EmulateSUBSPReg()
10064 EmulateSUBSPcLrEtc(opcode, encoding); in EmulateSUBSPReg()
10067 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateSUBSPReg()
10106 bool EmulateInstructionARM::EmulateADDRegShift(const uint32_t opcode, in EmulateADDRegShift() argument
10124 if (ConditionPassed(opcode)) { in EmulateADDRegShift()
10135 d = Bits32(opcode, 15, 12); in EmulateADDRegShift()
10136 n = Bits32(opcode, 19, 16); in EmulateADDRegShift()
10137 m = Bits32(opcode, 3, 0); in EmulateADDRegShift()
10138 s = Bits32(opcode, 11, 8); in EmulateADDRegShift()
10141 setflags = BitIsSet(opcode, 20); in EmulateADDRegShift()
10142 shift_t = DecodeRegShift(Bits32(opcode, 6, 5)); in EmulateADDRegShift()
10202 bool EmulateInstructionARM::EmulateSUBReg(const uint32_t opcode, in EmulateSUBReg() argument
10222 if (ConditionPassed(opcode)) { in EmulateSUBReg()
10233 d = Bits32(opcode, 2, 0); in EmulateSUBReg()
10234 n = Bits32(opcode, 5, 3); in EmulateSUBReg()
10235 m = Bits32(opcode, 8, 6); in EmulateSUBReg()
10246 d = Bits32(opcode, 11, 8); in EmulateSUBReg()
10247 n = Bits32(opcode, 19, 16); in EmulateSUBReg()
10248 m = Bits32(opcode, 3, 0); in EmulateSUBReg()
10249 setflags = BitIsSet(opcode, 20); in EmulateSUBReg()
10253 return EmulateCMPImm(opcode, eEncodingT3); in EmulateSUBReg()
10257 return EmulateSUBSPReg(opcode, eEncodingT1); in EmulateSUBReg()
10260 shift_n = DecodeImmShiftThumb(opcode, shift_t); in EmulateSUBReg()
10264 if ((d == 13) || ((d == 15) && BitIsClear(opcode, 20)) || (n == 15) || in EmulateSUBReg()
10273 d = Bits32(opcode, 15, 12); in EmulateSUBReg()
10274 n = Bits32(opcode, 19, 16); in EmulateSUBReg()
10275 m = Bits32(opcode, 3, 0); in EmulateSUBReg()
10276 setflags = BitIsSet(opcode, 20); in EmulateSUBReg()
10281 EmulateSUBSPcLrEtc(opcode, encoding); in EmulateSUBReg()
10284 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateSUBReg()
10336 bool EmulateInstructionARM::EmulateSTREX(const uint32_t opcode, in EmulateSTREX() argument
10351 if (ConditionPassed(opcode)) { in EmulateSTREX()
10363 d = Bits32(opcode, 11, 8); in EmulateSTREX()
10364 t = Bits32(opcode, 15, 12); in EmulateSTREX()
10365 n = Bits32(opcode, 19, 16); in EmulateSTREX()
10366 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateSTREX()
10381 d = Bits32(opcode, 15, 12); in EmulateSTREX()
10382 t = Bits32(opcode, 3, 0); in EmulateSTREX()
10383 n = Bits32(opcode, 19, 16); in EmulateSTREX()
10447 bool EmulateInstructionARM::EmulateSTRBImmARM(const uint32_t opcode, in EmulateSTRBImmARM() argument
10460 if (ConditionPassed(opcode)) { in EmulateSTRBImmARM()
10472 t = Bits32(opcode, 15, 12); in EmulateSTRBImmARM()
10473 n = Bits32(opcode, 19, 16); in EmulateSTRBImmARM()
10474 imm32 = Bits32(opcode, 11, 0); in EmulateSTRBImmARM()
10477 index = BitIsSet(opcode, 24); in EmulateSTRBImmARM()
10478 add = BitIsSet(opcode, 23); in EmulateSTRBImmARM()
10479 wback = BitIsClear(opcode, 24) || BitIsSet(opcode, 21); in EmulateSTRBImmARM()
10540 bool EmulateInstructionARM::EmulateSTRImmARM(const uint32_t opcode, in EmulateSTRImmARM() argument
10553 if (ConditionPassed(opcode)) { in EmulateSTRImmARM()
10569 t = Bits32(opcode, 15, 12); in EmulateSTRImmARM()
10570 n = Bits32(opcode, 19, 16); in EmulateSTRImmARM()
10571 imm32 = Bits32(opcode, 11, 0); in EmulateSTRImmARM()
10574 index = BitIsSet(opcode, 24); in EmulateSTRImmARM()
10575 add = BitIsSet(opcode, 23); in EmulateSTRImmARM()
10576 wback = BitIsClear(opcode, 24) || BitIsSet(opcode, 21); in EmulateSTRImmARM()
10649 bool EmulateInstructionARM::EmulateLDRDImmediate(const uint32_t opcode, in EmulateLDRDImmediate() argument
10663 if (ConditionPassed(opcode)) { in EmulateLDRDImmediate()
10678 t = Bits32(opcode, 15, 12); in EmulateLDRDImmediate()
10679 t2 = Bits32(opcode, 11, 8); in EmulateLDRDImmediate()
10680 n = Bits32(opcode, 19, 16); in EmulateLDRDImmediate()
10681 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateLDRDImmediate()
10684 index = BitIsSet(opcode, 24); in EmulateLDRDImmediate()
10685 add = BitIsSet(opcode, 23); in EmulateLDRDImmediate()
10686 wback = BitIsSet(opcode, 21); in EmulateLDRDImmediate()
10703 t = Bits32(opcode, 15, 12); in EmulateLDRDImmediate()
10707 n = Bits32(opcode, 19, 16); in EmulateLDRDImmediate()
10708 imm32 = (Bits32(opcode, 11, 8) << 4) | Bits32(opcode, 3, 0); in EmulateLDRDImmediate()
10711 index = BitIsSet(opcode, 24); in EmulateLDRDImmediate()
10712 add = BitIsSet(opcode, 23); in EmulateLDRDImmediate()
10713 wback = BitIsClear(opcode, 24) || BitIsSet(opcode, 21); in EmulateLDRDImmediate()
10716 if (BitIsClear(opcode, 24) && BitIsSet(opcode, 21)) in EmulateLDRDImmediate()
10797 bool EmulateInstructionARM::EmulateLDRDRegister(const uint32_t opcode, in EmulateLDRDRegister() argument
10811 if (ConditionPassed(opcode)) { in EmulateLDRDRegister()
10824 t = Bits32(opcode, 15, 12); in EmulateLDRDRegister()
10828 n = Bits32(opcode, 19, 16); in EmulateLDRDRegister()
10829 m = Bits32(opcode, 3, 0); in EmulateLDRDRegister()
10832 index = BitIsSet(opcode, 24); in EmulateLDRDRegister()
10833 add = BitIsSet(opcode, 23); in EmulateLDRDRegister()
10834 wback = BitIsClear(opcode, 24) || BitIsSet(opcode, 21); in EmulateLDRDRegister()
10837 if (BitIsClear(opcode, 24) && BitIsSet(opcode, 21)) in EmulateLDRDRegister()
10926 bool EmulateInstructionARM::EmulateSTRDImm(const uint32_t opcode, in EmulateSTRDImm() argument
10940 if (ConditionPassed(opcode)) { in EmulateSTRDImm()
10954 t = Bits32(opcode, 15, 12); in EmulateSTRDImm()
10955 t2 = Bits32(opcode, 11, 8); in EmulateSTRDImm()
10956 n = Bits32(opcode, 19, 16); in EmulateSTRDImm()
10957 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateSTRDImm()
10960 index = BitIsSet(opcode, 24); in EmulateSTRDImm()
10961 add = BitIsSet(opcode, 23); in EmulateSTRDImm()
10962 wback = BitIsSet(opcode, 21); in EmulateSTRDImm()
10978 t = Bits32(opcode, 15, 12); in EmulateSTRDImm()
10983 n = Bits32(opcode, 19, 16); in EmulateSTRDImm()
10984 imm32 = (Bits32(opcode, 11, 8) << 4) | Bits32(opcode, 3, 0); in EmulateSTRDImm()
10987 index = BitIsSet(opcode, 24); in EmulateSTRDImm()
10988 add = BitIsSet(opcode, 23); in EmulateSTRDImm()
10989 wback = BitIsClear(opcode, 24) || BitIsSet(opcode, 21); in EmulateSTRDImm()
10992 if (BitIsClear(opcode, 24) && BitIsSet(opcode, 21)) in EmulateSTRDImm()
11079 bool EmulateInstructionARM::EmulateSTRDReg(const uint32_t opcode, in EmulateSTRDReg() argument
11093 if (ConditionPassed(opcode)) { in EmulateSTRDReg()
11106 t = Bits32(opcode, 15, 12); in EmulateSTRDReg()
11111 n = Bits32(opcode, 19, 16); in EmulateSTRDReg()
11112 m = Bits32(opcode, 3, 0); in EmulateSTRDReg()
11115 index = BitIsSet(opcode, 24); in EmulateSTRDReg()
11116 add = BitIsSet(opcode, 23); in EmulateSTRDReg()
11117 wback = BitIsClear(opcode, 24) || BitIsSet(opcode, 21); in EmulateSTRDReg()
11120 if (BitIsClear(opcode, 24) && BitIsSet(opcode, 21)) in EmulateSTRDReg()
11217 bool EmulateInstructionARM::EmulateVLDM(const uint32_t opcode, in EmulateVLDM() argument
11236 if (ConditionPassed(opcode)) { in EmulateVLDM()
11252 if ((Bit32(opcode, 24) == Bit32(opcode, 23)) && BitIsSet(opcode, 21)) in EmulateVLDM()
11259 add = BitIsSet(opcode, 23); in EmulateVLDM()
11260 wback = BitIsSet(opcode, 21); in EmulateVLDM()
11263 d = (Bit32(opcode, 22) << 4) | Bits32(opcode, 15, 12); in EmulateVLDM()
11264 n = Bits32(opcode, 19, 16); in EmulateVLDM()
11265 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateVLDM()
11268 regs = Bits32(opcode, 7, 0) / 2; in EmulateVLDM()
11287 if ((Bit32(opcode, 24) == Bit32(opcode, 23)) && BitIsSet(opcode, 21)) in EmulateVLDM()
11295 add = BitIsSet(opcode, 23); in EmulateVLDM()
11296 wback = BitIsSet(opcode, 21); in EmulateVLDM()
11297 d = (Bits32(opcode, 15, 12) << 1) | Bit32(opcode, 22); in EmulateVLDM()
11298 n = Bits32(opcode, 19, 16); in EmulateVLDM()
11301 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateVLDM()
11302 regs = Bits32(opcode, 7, 0); in EmulateVLDM()
11410 bool EmulateInstructionARM::EmulateVSTM(const uint32_t opcode, in EmulateVSTM() argument
11430 if (ConditionPassed(opcode)) { in EmulateVSTM()
11446 if ((Bit32(opcode, 24) == Bit32(opcode, 23)) && BitIsSet(opcode, 21)) in EmulateVSTM()
11453 add = BitIsSet(opcode, 23); in EmulateVSTM()
11454 wback = BitIsSet(opcode, 21); in EmulateVSTM()
11457 d = (Bit32(opcode, 22) << 4) | Bits32(opcode, 15, 12); in EmulateVSTM()
11458 n = Bits32(opcode, 19, 16); in EmulateVSTM()
11459 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateVSTM()
11462 regs = Bits32(opcode, 7, 0) / 2; in EmulateVSTM()
11481 if ((Bit32(opcode, 24) == Bit32(opcode, 23)) && BitIsSet(opcode, 21)) in EmulateVSTM()
11489 add = BitIsSet(opcode, 23); in EmulateVSTM()
11490 wback = BitIsSet(opcode, 21); in EmulateVSTM()
11491 d = (Bits32(opcode, 15, 12) << 1) | Bit32(opcode, 22); in EmulateVSTM()
11492 n = Bits32(opcode, 19, 16); in EmulateVSTM()
11495 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateVSTM()
11496 regs = Bits32(opcode, 7, 0); in EmulateVSTM()
11615 bool EmulateInstructionARM::EmulateVLDR(const uint32_t opcode, in EmulateVLDR() argument
11633 if (ConditionPassed(opcode)) { in EmulateVLDR()
11646 add = BitIsSet(opcode, 23); in EmulateVLDR()
11647 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateVLDR()
11650 d = (Bit32(opcode, 22) << 4) | Bits32(opcode, 15, 12); in EmulateVLDR()
11651 n = Bits32(opcode, 19, 16); in EmulateVLDR()
11659 add = BitIsSet(opcode, 23); in EmulateVLDR()
11660 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateVLDR()
11663 d = (Bits32(opcode, 15, 12) << 1) | Bit32(opcode, 22); in EmulateVLDR()
11664 n = Bits32(opcode, 19, 16); in EmulateVLDR()
11742 bool EmulateInstructionARM::EmulateVSTR(const uint32_t opcode, in EmulateVSTR() argument
11759 if (ConditionPassed(opcode)) { in EmulateVSTR()
11772 add = BitIsSet(opcode, 23); in EmulateVSTR()
11773 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateVSTR()
11776 d = (Bit32(opcode, 22) << 4) | Bits32(opcode, 15, 12); in EmulateVSTR()
11777 n = Bits32(opcode, 19, 16); in EmulateVSTR()
11789 add = BitIsSet(opcode, 23); in EmulateVSTR()
11790 imm32 = Bits32(opcode, 7, 0) << 2; in EmulateVSTR()
11793 d = (Bits32(opcode, 15, 12) << 1) | Bit32(opcode, 22); in EmulateVSTR()
11794 n = Bits32(opcode, 19, 16); in EmulateVSTR()
11875 bool EmulateInstructionARM::EmulateVLD1Multiple(const uint32_t opcode, in EmulateVLD1Multiple() argument
11890 if (ConditionPassed(opcode)) { in EmulateVLD1Multiple()
11916 uint32_t type = Bits32(opcode, 11, 8); in EmulateVLD1Multiple()
11917 uint32_t align = Bits32(opcode, 5, 4); in EmulateVLD1Multiple()
11947 ebytes = 1 << Bits32(opcode, 7, 6); in EmulateVLD1Multiple()
11952 d = (Bit32(opcode, 22) << 4) | Bits32(opcode, 15, 12); in EmulateVLD1Multiple()
11953 n = Bits32(opcode, 19, 15); in EmulateVLD1Multiple()
11954 m = Bits32(opcode, 3, 0); in EmulateVLD1Multiple()
12033 bool EmulateInstructionARM::EmulateVLD1Single(const uint32_t opcode, in EmulateVLD1Single() argument
12045 if (ConditionPassed(opcode)) { in EmulateVLD1Single()
12059 uint32_t size = Bits32(opcode, 11, 10); in EmulateVLD1Single()
12060 uint32_t index_align = Bits32(opcode, 7, 4); in EmulateVLD1Single()
12063 return EmulateVLD1SingleAll(opcode, encoding); in EmulateVLD1Single()
12118 d = (Bit32(opcode, 22) << 4) | Bits32(opcode, 15, 12); in EmulateVLD1Single()
12119 n = Bits32(opcode, 19, 16); in EmulateVLD1Single()
12120 m = Bits32(opcode, 3, 0); in EmulateVLD1Single()
12210 bool EmulateInstructionARM::EmulateVST1Multiple(const uint32_t opcode, in EmulateVST1Multiple() argument
12225 if (ConditionPassed(opcode)) { in EmulateVST1Multiple()
12240 uint32_t type = Bits32(opcode, 11, 8); in EmulateVST1Multiple()
12241 uint32_t align = Bits32(opcode, 5, 4); in EmulateVST1Multiple()
12276 ebytes = 1 << Bits32(opcode, 7, 6); in EmulateVST1Multiple()
12281 d = (Bit32(opcode, 22) << 4) | Bits32(opcode, 15, 12); in EmulateVST1Multiple()
12282 n = Bits32(opcode, 19, 16); in EmulateVST1Multiple()
12283 m = Bits32(opcode, 3, 0); in EmulateVST1Multiple()
12366 bool EmulateInstructionARM::EmulateVST1Single(const uint32_t opcode, in EmulateVST1Single() argument
12378 if (ConditionPassed(opcode)) { in EmulateVST1Single()
12392 uint32_t size = Bits32(opcode, 11, 10); in EmulateVST1Single()
12393 uint32_t index_align = Bits32(opcode, 7, 4); in EmulateVST1Single()
12452 d = (Bit32(opcode, 22) << 4) | Bits32(opcode, 15, 12); in EmulateVST1Single()
12453 n = Bits32(opcode, 19, 16); in EmulateVST1Single()
12454 m = Bits32(opcode, 3, 0); in EmulateVST1Single()
12525 bool EmulateInstructionARM::EmulateVLD1SingleAll(const uint32_t opcode, in EmulateVLD1SingleAll() argument
12539 if (ConditionPassed(opcode)) { in EmulateVLD1SingleAll()
12554 uint32_t size = Bits32(opcode, 7, 6); in EmulateVLD1SingleAll()
12555 if ((size == 3) || ((size == 0) && BitIsSet(opcode, 4))) in EmulateVLD1SingleAll()
12562 if (BitIsClear(opcode, 5)) in EmulateVLD1SingleAll()
12568 if (BitIsClear(opcode, 4)) in EmulateVLD1SingleAll()
12574 d = (Bit32(opcode, 22) << 4) | Bits32(opcode, 15, 12); in EmulateVLD1SingleAll()
12575 n = Bits32(opcode, 19, 16); in EmulateVLD1SingleAll()
12576 m = Bits32(opcode, 3, 0); in EmulateVLD1SingleAll()
12656 bool EmulateInstructionARM::EmulateSUBSPcLrEtc(const uint32_t opcode, in EmulateSUBSPcLrEtc() argument
12664 case opcode of in EmulateSUBSPcLrEtc()
12683 if (ConditionPassed(opcode)) { in EmulateSUBSPcLrEtc()
12698 imm32 = Bits32(opcode, 7, 0); in EmulateSUBSPcLrEtc()
12710 n = Bits32(opcode, 19, 16); in EmulateSUBSPcLrEtc()
12711 imm32 = ARMExpandImm(opcode); in EmulateSUBSPcLrEtc()
12713 code = Bits32(opcode, 24, 21); in EmulateSUBSPcLrEtc()
12719 n = Bits32(opcode, 19, 16); in EmulateSUBSPcLrEtc()
12720 m = Bits32(opcode, 3, 0); in EmulateSUBSPcLrEtc()
12724 shift_n = DecodeImmShiftARM(opcode, shift_t); in EmulateSUBSPcLrEtc()
12840 EmulateInstructionARM::GetARMOpcodeForInstruction(const uint32_t opcode, in GetARMOpcodeForInstruction() argument
13204 if ((g_arm_opcodes[i].mask & opcode) == g_arm_opcodes[i].value && in GetARMOpcodeForInstruction()
13212 EmulateInstructionARM::GetThumbOpcodeForInstruction(const uint32_t opcode, in GetThumbOpcodeForInstruction() argument
13754 if ((g_thumb_opcodes[i].mask & opcode) == g_thumb_opcodes[i].value && in GetThumbOpcodeForInstruction()
13874 bool EmulateInstructionARM::ConditionPassed(const uint32_t opcode) { in ConditionPassed() argument
13881 const uint32_t cond = CurrentCond(opcode); in ConditionPassed()
13947 uint32_t EmulateInstructionARM::CurrentCond(const uint32_t opcode) { in CurrentCond() argument
13953 return UnsignedBits(opcode, 31, 28); in CurrentCond()
13961 if (Bits32(opcode, 15, 12) == 0x0d && Bits32(opcode, 11, 8) != 0x0f) in CurrentCond()
13962 return Bits32(opcode, 11, 8); in CurrentCond()
13964 if (Bits32(opcode, 31, 27) == 0x1e && Bits32(opcode, 15, 14) == 0x02 && in CurrentCond()
13965 Bits32(opcode, 12, 12) == 0x00 && Bits32(opcode, 25, 22) <= 0x0d) { in CurrentCond()
13966 return Bits32(opcode, 25, 22); in CurrentCond()