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/llvm-project-15.0.7/llvm/test/CodeGen/Mips/msa/
H A Dspill.ll4 ; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
142 %res = call i32 @llvm.mips.copy.s.b(<16 x i8> %rx33, i32 0)
146 declare <16 x i8> @llvm.mips.addv.b(<16 x i8>, <16 x i8>) nounwind
147 declare i32 @llvm.mips.copy.s.b(<16 x i8>, i32) nounwind
291 %res = call i32 @llvm.mips.copy.s.h(<8 x i16> %rx33, i32 0)
295 declare <8 x i16> @llvm.mips.addv.h(<8 x i16>, <8 x i16>) nounwind
296 declare i32 @llvm.mips.copy.s.h(<8 x i16>, i32) nounwind
440 %res = call i32 @llvm.mips.copy.s.w(<4 x i32> %rx33, i32 0)
444 declare <4 x i32> @llvm.mips.addv.w(<4 x i32>, <4 x i32>) nounwind
445 declare i32 @llvm.mips.copy.s.w(<4 x i32>, i32) nounwind
[all …]
H A Dimmediates-bad.ll98 %r = call <16 x i8> @llvm.mips.ldi.b(i32 1025)
321 %r = call <4 x i32> @llvm.mips.ldi.w(i32 1024)
496 %r = call <8 x i16> @llvm.mips.ldi.h(i32 1024)
698 %r = call <2 x i64> @llvm.mips.ldi.d(i32 1024)
898 %r = call <16 x i8> @llvm.mips.ldi.b(i32 -3)
1495 %r = call <2 x i64> @llvm.mips.ldi.d(i32 -3)
1580 declare <8 x i16> @llvm.mips.ldi.h(i32)
1608 declare <4 x i32> @llvm.mips.ldi.w(i32)
1624 declare <2 x i64> @llvm.mips.ldi.d(i32)
1646 declare <16 x i8> @llvm.mips.ldi.b(i32)
[all …]
H A Delm_cxcmsa.ll9 %0 = tail call i32 @llvm.mips.cfcmsa(i32 0)
19 %0 = tail call i32 @llvm.mips.cfcmsa(i32 1)
29 %0 = tail call i32 @llvm.mips.cfcmsa(i32 2)
39 %0 = tail call i32 @llvm.mips.cfcmsa(i32 3)
49 %0 = tail call i32 @llvm.mips.cfcmsa(i32 4)
59 %0 = tail call i32 @llvm.mips.cfcmsa(i32 5)
69 %0 = tail call i32 @llvm.mips.cfcmsa(i32 6)
79 %0 = tail call i32 @llvm.mips.cfcmsa(i32 7)
89 %0 = tail call i32 @llvm.mips.cfcmsa(i32 8)
98 tail call void @llvm.mips.ctcmsa(i32 0, i32 1)
[all …]
H A Di5_ld_st.ll13 %1 = tail call <16 x i8> @llvm.mips.ld.b(i8* %0, i32 16)
18 declare <16 x i8> @llvm.mips.ld.b(i8*, i32) nounwind
29 %1 = tail call <16 x i8> @llvm.mips.ld.b(i8* %0, i32 9)
43 %1 = tail call <16 x i8> @llvm.mips.ld.b(i8* %0, i32 -512)
45 %2 = tail call <16 x i8> @llvm.mips.ld.b(i8* %0, i32 511)
63 %2 = tail call <16 x i8> @llvm.mips.ld.b(i8* %0, i32 512)
84 %1 = tail call <8 x i16> @llvm.mips.ld.h(i8* %0, i32 16)
89 declare <8 x i16> @llvm.mips.ld.h(i8*, i32) nounwind
100 %1 = tail call <8 x i16> @llvm.mips.ld.h(i8* %0, i32 9)
161 declare <4 x i32> @llvm.mips.ld.w(i8*, i32) nounwind
[all …]
H A Di10.ll20 declare i32 @llvm.mips.bnz.b(<16 x i8>) nounwind
41 declare i32 @llvm.mips.bnz.h(<8 x i16>) nounwind
95 %0 = call <16 x i8> @llvm.mips.ldi.b(i32 3)
97 %1 = call <16 x i8> @llvm.mips.ldi.b(i32 -3)
102 declare <16 x i8> @llvm.mips.ldi.b(i32)
113 %0 = call <8 x i16> @llvm.mips.ldi.h(i32 3)
120 declare <8 x i16> @llvm.mips.ldi.h(i32)
131 %0 = call <4 x i32> @llvm.mips.ldi.w(i32 3)
138 declare <4 x i32> @llvm.mips.ldi.w(i32)
149 %0 = call <2 x i64> @llvm.mips.ldi.d(i32 3)
[all …]
H A Dbit.ll3 ; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
12 %1 = tail call <16 x i8> @llvm.mips.sat.s.b(<16 x i8> %0, i32 7)
17 declare <16 x i8> @llvm.mips.sat.s.b(<16 x i8>, i32) nounwind
36 declare <8 x i16> @llvm.mips.sat.s.h(<8 x i16>, i32) nounwind
55 declare <4 x i32> @llvm.mips.sat.s.w(<4 x i32>, i32) nounwind
74 declare <2 x i64> @llvm.mips.sat.s.d(<2 x i64>, i32) nounwind
93 declare <16 x i8> @llvm.mips.sat.u.b(<16 x i8>, i32) nounwind
112 declare <8 x i16> @llvm.mips.sat.u.h(<8 x i16>, i32) nounwind
169 declare <16 x i8> @llvm.mips.slli.b(<16 x i8>, i32) nounwind
188 declare <8 x i16> @llvm.mips.slli.h(<8 x i16>, i32) nounwind
[all …]
H A Di5-c.ll4 ; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
14 %1 = tail call <16 x i8> @llvm.mips.ceqi.b(<16 x i8> %0, i32 14)
16 %2 = tail call <16 x i8> @llvm.mips.ceqi.b(<16 x i8> %0, i32 -14)
21 declare <16 x i8> @llvm.mips.ceqi.b(<16 x i8>, i32) nounwind
45 declare <8 x i16> @llvm.mips.ceqi.h(<8 x i16>, i32) nounwind
69 declare <4 x i32> @llvm.mips.ceqi.w(<4 x i32>, i32) nounwind
93 declare <2 x i64> @llvm.mips.ceqi.d(<2 x i64>, i32) nounwind
117 declare <16 x i8> @llvm.mips.clei.s.b(<16 x i8>, i32) nounwind
141 declare <8 x i16> @llvm.mips.clei.s.h(<8 x i16>, i32) nounwind
165 declare <4 x i32> @llvm.mips.clei.s.w(<4 x i32>, i32) nounwind
[all …]
H A Di5-m.ll4 ; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
14 %1 = tail call <16 x i8> @llvm.mips.maxi.s.b(<16 x i8> %0, i32 14)
21 declare <16 x i8> @llvm.mips.maxi.s.b(<16 x i8>, i32) nounwind
45 declare <8 x i16> @llvm.mips.maxi.s.h(<8 x i16>, i32) nounwind
69 declare <4 x i32> @llvm.mips.maxi.s.w(<4 x i32>, i32) nounwind
93 declare <2 x i64> @llvm.mips.maxi.s.d(<2 x i64>, i32) nounwind
114 declare <16 x i8> @llvm.mips.maxi.u.b(<16 x i8>, i32) nounwind
133 declare <8 x i16> @llvm.mips.maxi.u.h(<8 x i16>, i32) nounwind
152 declare <4 x i32> @llvm.mips.maxi.u.w(<4 x i32>, i32) nounwind
171 declare <2 x i64> @llvm.mips.maxi.u.d(<2 x i64>, i32) nounwind
[all …]
H A D3rf_int_float.ll4 ; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s | FileCheck %s
15 %2 = tail call <4 x i32> @llvm.mips.fcaf.w(<4 x float> %0, <4 x float> %1)
20 declare <4 x i32> @llvm.mips.fcaf.w(<4 x float>, <4 x float>) nounwind
42 declare <2 x i64> @llvm.mips.fcaf.d(<2 x double>, <2 x double>) nounwind
64 declare <4 x i32> @llvm.mips.fceq.w(<4 x float>, <4 x float>) nounwind
86 declare <2 x i64> @llvm.mips.fceq.d(<2 x double>, <2 x double>) nounwind
108 declare <4 x i32> @llvm.mips.fcle.w(<4 x float>, <4 x float>) nounwind
130 declare <2 x i64> @llvm.mips.fcle.d(<2 x double>, <2 x double>) nounwind
152 declare <4 x i32> @llvm.mips.fclt.w(<4 x float>, <4 x float>) nounwind
196 declare <4 x i32> @llvm.mips.fcor.w(<4 x float>, <4 x float>) nounwind
[all …]
H A Dimmediates.ll351 %r = call <16 x i8> @llvm.mips.ldi.b(i32 3)
972 %r = call <4 x i32> @llvm.mips.ldi.w(i32 3)
1461 %r = call <8 x i16> @llvm.mips.ldi.h(i32 3)
2289 declare <8 x i16> @llvm.mips.ldi.h(i32)
2317 declare <4 x i32> @llvm.mips.ldi.w(i32)
2333 declare <2 x i64> @llvm.mips.ldi.d(i32)
2355 declare <16 x i8> @llvm.mips.ldi.b(i32)
2391 declare <16 x i8> @llvm.mips.ld.b(i8*, i32)
2392 declare <8 x i16> @llvm.mips.ld.h(i8*, i32)
2393 declare <4 x i32> @llvm.mips.ld.w(i8*, i32)
[all …]
H A Dshift_no_and.ll19 declare <16 x i8> @llvm.mips.bclr.b(<16 x i8>, <16 x i8>) nounwind
38 declare <8 x i16> @llvm.mips.bclr.h(<8 x i16>, <8 x i16>) nounwind
57 declare <4 x i32> @llvm.mips.bclr.w(<4 x i32>, <4 x i32>) nounwind
76 declare <2 x i64> @llvm.mips.bclr.d(<2 x i64>, <2 x i64>) nounwind
95 declare <16 x i8> @llvm.mips.bneg.b(<16 x i8>, <16 x i8>) nounwind
114 declare <8 x i16> @llvm.mips.bneg.h(<8 x i16>, <8 x i16>) nounwind
133 declare <4 x i32> @llvm.mips.bneg.w(<4 x i32>, <4 x i32>) nounwind
152 declare <2 x i64> @llvm.mips.bneg.d(<2 x i64>, <2 x i64>) nounwind
171 declare <16 x i8> @llvm.mips.bset.b(<16 x i8>, <16 x i8>) nounwind
247 declare <16 x i8> @llvm.mips.sll.b(<16 x i8>, <16 x i8>) nounwind
[all …]
/llvm-project-15.0.7/clang/lib/Driver/ToolChains/Arch/
H A DMips.cpp78 case llvm::Triple::mips: in getMipsCPUAndABI()
152 mips::FloatABI mips::getMipsFloatABI(const Driver &D, const ArgList &Args, in getMipsFloatABI()
154 mips::FloatABI ABI = mips::FloatABI::Invalid; in getMipsFloatABI()
159 ABI = mips::FloatABI::Soft; in getMipsFloatABI()
161 ABI = mips::FloatABI::Hard; in getMipsFloatABI()
283 mips::FloatABI FloatABI = mips::getMipsFloatABI(D, Args, Triple); in getMIPSTargetFeatures()
294 if (mips::getIEEE754Standard(CPUName) & mips::Std2008) in getMIPSTargetFeatures()
301 if (mips::getIEEE754Standard(CPUName) & mips::Legacy) in getMIPSTargetFeatures()
315 if (mips::getIEEE754Standard(CPUName) & mips::Std2008) { in getMIPSTargetFeatures()
322 if (mips::getIEEE754Standard(CPUName) & mips::Legacy) { in getMIPSTargetFeatures()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Ddsp-r1.ll8 %1 = tail call i32 @llvm.mips.extr.w(i64 %a0, i32 15)
12 declare i32 @llvm.mips.extr.w(i64, i32) nounwind
30 declare i32 @llvm.mips.extr.r.w(i64, i32) nounwind
40 declare i32 @llvm.mips.extr.s.h(i64, i32) nounwind
50 declare i32 @llvm.mips.extr.rs.w(i64, i32) nounwind
84 declare i32 @llvm.mips.extp(i64, i32) nounwind
102 declare i32 @llvm.mips.extpdp(i64, i32) nounwind
296 %0 = tail call i32 @llvm.mips.bposge32()
661 %2 = tail call i32 @llvm.mips.rddsp(i32 31)
676 %2 = tail call i32 @llvm.mips.rddsp(i32 31)
[all …]
H A Dbrind-tailcall.ll1 ; RUN: llc -mtriple=mips -debug-only=isel -mips-tail-calls=1 \
3 ; RUN: llc -mtriple=mips -debug-only=isel -mips-tail-calls=1 \
5 ; RUN: llc -mtriple=mips64 -debug-only=isel -mips-tail-calls=1 \
7 ; RUN: llc -mtriple=mips64 -debug-only=isel -mips-tail-calls=1 \
9 ; RUN: llc -mtriple=mips -debug-only=isel -mips-tail-calls=1 \
11 ; RUN: llc -mtriple=mips -debug-only=isel -mips-tail-calls=1 \
13 ; RUN: llc -mtriple=mips -mcpu=mips32r6 -debug-only=isel -mips-tail-calls=1 \
15 ; RUN: llc -mtriple=mips -mcpu=mips32r6 -debug-only=isel -mips-tail-calls=1 \
17 ; RUN: llc -mtriple=mips -debug-only=isel -mips-tail-calls=1 \
19 ; RUN: llc -mtriple=mips -debug-only=isel -mips-tail-calls=1 \
H A Ddsp-r2.ll332 %1 = tail call <4 x i8> @llvm.mips.absq.s.qb(<4 x i8> %0)
338 declare <4 x i8> @llvm.mips.absq.s.qb(<4 x i8>) nounwind
372 %0 = tail call i32 @llvm.mips.mulq.rs.w(i32 %a0, i32 %a1)
376 declare i32 @llvm.mips.mulq.rs.w(i32, i32) nounwind
382 %0 = tail call i32 @llvm.mips.mulq.s.w(i32 %a0, i32 %a1)
386 declare i32 @llvm.mips.mulq.s.w(i32, i32) nounwind
476 %0 = tail call i32 @llvm.mips.addqh.w(i32 %a0, i32 %a1)
480 declare i32 @llvm.mips.addqh.w(i32, i32) nounwind readnone
486 %0 = tail call i32 @llvm.mips.addqh.r.w(i32 %a0, i32 %a1)
524 %0 = tail call i32 @llvm.mips.subqh.w(i32 %a0, i32 %a1)
[all …]
H A Dreloc-jalr.ll1 ; RUN: llc -mtriple=mips-linux-gnu -relocation-model=pic -mips-tail-calls=1 \
9 ; RUN: llc -mtriple=mips-linux-gnu -relocation-model=pic -mips-tail-calls=1 \
17 ; RUN: llc -mtriple=mips-linux-gnu -relocation-model=pic -mips-tail-calls=1 \
25 ; RUN: llc -mtriple=mips-linux-gnu -relocation-model=pic -mips-tail-calls=1 \
29 ; RUN: llc -mtriple=mips-linux-gnu -relocation-model=pic -mips-tail-calls=1 \
63 ; RUN: llc -mtriple=mips-linux-gnu -relocation-model=pic -mips-tail-calls=1 \
64 ; RUN: -O2 -mips-jalr-reloc=false < %s | \
67 ; RUN: llc -mtriple=mips-linux-gnu -relocation-model=static -mips-tail-calls=1 \
71 ; RUN: llc -mtriple=mips-linux-gnu -relocation-model=pic -mips-tail-calls=1 \
72 ; RUN: -O0 -mips-jalr-reloc=false < %s | \
[all …]
H A Dadjust-callstack-sp.ll1 ; RUN: llc < %s -march=mips -mattr=mips16 | FileCheck %s -check-prefix=M16
2 ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefix=GP32
3 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefix=GP32
4 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefix=GP32
5 ; RUN: llc < %s -march=mips -mcpu=mips3 -target-abi n64 | FileCheck %s -check-prefix=GP64
6 ; RUN: llc < %s -march=mips -mcpu=mips64 -target-abi n64 | FileCheck %s -check-prefix=GP64
7 ; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 | FileCheck %s -check-prefix=GP64
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/llvm-ir/
H A Dcall.ll3 ; RUN: llc -march=mips -mcpu=mips32 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck …
4 ; RUN: llc -march=mips -mcpu=mips32r2 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck …
5 ; RUN: llc -march=mips -mcpu=mips32r3 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck …
6 ; RUN: llc -march=mips -mcpu=mips32r5 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck …
7 ; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic -disable-mips-delay-filler -mips-tai…
8 ; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic -mattr=+fp64,+nooddspreg -disable-mip…
14 ; RUN: llc -march=mips64 -mcpu=mips64r6 -relocation-model=pic -disable-mips-delay-filler -mips-ta…
15 ; RUN: llc -march=mips -mcpu=mips32 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck …
16 ; RUN: llc -march=mips -mcpu=mips32r2 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck …
19 ; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic -disable-mips-delay-filler -mips-tai…
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/Fast-ISel/
H A Dcheck-disabled-mcpus.ll2 ; RUN: llc -march=mips -mcpu=mips2 -O0 -relocation-model=pic \
4 ; RUN: llc -march=mips -mcpu=mips3 -O0 -relocation-model=pic -target-abi n64 \
6 ; RUN: llc -march=mips -mcpu=mips4 -O0 -relocation-model=pic -target-abi n64 \
9 ; RUN: llc -march=mips -mcpu=mips32r6 -O0 -relocation-model=pic \
12 ; RUN: llc -march=mips -mattr=mips16 -O0 -relocation-model=pic \
15 ; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+micromips -O0 -relocation-model=pic \
22 ; RUN: llc -march=mips -mcpu=mips64 -O0 -relocation-model=pic -target-abi n64 \
24 ; RUN: llc -march=mips -mcpu=mips64r2 -O0 -relocation-model=pic -target-abi n64 \
30 ; RUN: llc -march=mips -mcpu=mips32r6 -O0 -relocation-model=pic \
34 ; RUN: llc -march=mips -mcpu=mips32r0 -O0 -relocation-model=pic \
[all …]
/llvm-project-15.0.7/lld/test/ELF/
H A Dmips-non-zero-gp0.s1 # REQUIRES: mips
10 # && ld.bfd -m elf32btsmip -r test.o -o mips-gp0-non-zero.o
12 # && ld.bfd -m elf64btsmip -r test.o -o mips-n64-gp0-non-zero.o
14 # Source code for mips-gp0-non-zero.o:
29 # Source code for mips-n64-gp0-non-zero.o and mips-micro-gp0-non-zero.o:
36 # RUN: ld.lld -r -o %t-32.r %S/Inputs/mips-gp0-non-zero.o
40 # RUN: ld.lld -r -o %t-64.r %S/Inputs/mips-n64-gp0-non-zero.o
42 # RUN: llvm-readobj -r %S/Inputs/mips-n64-gp0-non-zero.o %t-64.r \
51 # ADDEND64: File: {{.*}}{{/|\\}}mips-n64-gp0-non-zero.o
53 # ADDEND64: File: {{.*}}{{/|\\}}mips-non-zero-gp0.s.tmp-64.r
H A Dmips-elf-flags-err.s1 # REQUIRES: mips
4 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
5 # RUN: -mcpu=mips32 %S/Inputs/mips-dynamic.s -o %t1.o
6 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
13 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
14 # RUN: -mcpu=mips3 %S/Inputs/mips-dynamic.s -o %t1.o
15 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
22 # RUN: -mcpu=mips64r6 %S/Inputs/mips-dynamic.s -o %t1.o
50 # R3R32-NEXT: >>> {{.+}}mips-elf-flags-err.s.tmp1.o: mips3
51 # R3R32-NEXT: >>> {{.+}}mips-elf-flags-err.s.tmp2.o: mips32
[all …]
H A Dmips-npic-call-pic.s1 # REQUIRES: mips
9 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux -mcpu=mips32r2 \
10 # RUN: %p/Inputs/mips-fpic.s -o %t-fpic.o
11 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux -mcpu=mips32r2 \
12 # RUN: %p/Inputs/mips-fnpic.s -o %t-fnpic.o
14 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux -mcpu=mips32r2 \
15 # RUN: %p/Inputs/mips-pic.s -o %t-pic-r2.o
16 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux -mcpu=mips32r2 \
24 # RUN: %p/Inputs/mips-fpic.s -o %t-fpic.o
26 # RUN: %p/Inputs/mips-fnpic.s -o %t-fnpic.o
[all …]
H A Dmips-micro-jal.s1 # REQUIRES: mips
9 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
10 # RUN: -mattr=micromips %S/Inputs/mips-micro.s -o %t1eb.o
12 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
20 # RUN: -mattr=micromips %S/Inputs/mips-micro.s -o %t1el.o
29 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
32 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
47 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
50 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
51 # RUN: %S/Inputs/mips-fpic.s -o %t-reg.o
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/mirparser/
H A Dtarget-flags-pic-mxgot-tls.mir148 %57 = LUi64 target-flags(mips-gpoff-hi) @_Z2k1i
150 %6 = DADDiu %58, target-flags(mips-gpoff-lo) @_Z2k1i
153 %7 = LUi64 target-flags(mips-call-hi16) @_Z1gi
163 %13 = LUi64 target-flags(mips-got-hi16) @v
172 %20 = DADDiu %6, target-flags(mips-tlsldm) @__tls_guard
190 %42 = DADDiu %6, target-flags(mips-tlsgd) @k
216 %31 = LUi64 target-flags(mips-call-hi16) @_Z1gi
227 %37 = DADDiu %6, target-flags(mips-tlsgd) @k
241 %44 = LUi64 target-flags(mips-got-hi16) @_ZTH1j
251 %47 = LUi64 target-flags(mips-call-hi16) @_ZTH1j
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/tailcall/
H A Dtailcall-wrong-isa.ll1 ; RUN: llc -filetype=obj -mtriple=mipsel -relocation-model=pic -verify-machineinstrs -mips-tail-cal…
4 ; RUN: llc -filetype=obj -mtriple=mipsel -relocation-model=static -verify-machineinstrs -mips-tail-…
7 …triple=mips64el -relocation-model=pic -mcpu=mips64 -verify-machineinstrs -mips-tail-calls=1 < %s -…
10 …ple=mips64el -relocation-model=static -mcpu=mips64 -verify-machineinstrs -mips-tail-calls=1 < %s -…
13 ; RUN: llc -filetype=obj -mtriple=mipsel -relocation-model=pic -mattr=+micromips -mips-tail-calls=1…
16 ; RUN: llc -filetype=obj -mtriple=mipsel -relocation-model=static -mattr=+micromips -mips-tail-call…
19 ; RUN: llc -filetype=obj -mtriple=mipsel -relocation-model=pic -mcpu=mips32r6 -mips-tail-calls=1 < …
21 ; RUN: llc -filetype=obj -mtriple=mipsel -relocation-model=static -mcpu=mips32r6 -mips-tail-calls=1…
24 ; RUN: llc -filetype=obj -mtriple=mips64el -relocation-model=pic -mcpu=mips64r6 -mips-tail-calls=1 …
26 ; RUN: llc -filetype=obj -mtriple=mips64el -relocation-model=static -mcpu=mips64r6 -mips-tail-calls…

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