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/llvm-project-15.0.7/clang/test/CodeGenCXX/
H A Datomic-inline.cpp8 AM8 m8; variable
15 __atomic_load(&m8, &am, 0); in load8()
25 __atomic_store(&m8, &s8, 0); in store8()
34 return __atomic_compare_exchange(&m8, &s8, &am, 0, 0, 0); in cmpxchg8()
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/
H A Dvsplats-i64.ll10 ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
21 ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
33 ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
51 ; RV32V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
61 ; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
77 ; RV32V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
84 ; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, mu
95 ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
107 ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
120 ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
[all …]
H A Dvpscatter-sdnode.ll183 ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
341 ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
364 ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
388 ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
412 ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
546 ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
569 ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
593 ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
617 ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
640 ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
[all …]
H A Dvpgather-sdnode.ll244 ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
271 ; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, mu
279 ; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, mu
311 ; RV64-NEXT: vsetvli t0, zero, e64, m8, ta, mu
326 ; RV64-NEXT: vsetvli a5, zero, e64, m8, ta, mu
334 ; RV64-NEXT: vsetvli a4, zero, e64, m8, ta, mu
343 ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
551 ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
574 ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
598 ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
[all …]
H A Dmscatter-sdnode.ll185 ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
347 ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
370 ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
394 ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
418 ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
557 ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
579 ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
602 ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
625 ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
647 ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
[all …]
H A Dactive_lane_mask.ll108 ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
127 ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
138 ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
146 ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
162 ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
173 ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
181 ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
189 ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
197 ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
205 ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
[all …]
H A Dfixed-vectors-vpgather.ll280 ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, mu
297 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
308 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
1938 ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, mu
1945 ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, mu
1962 ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
1969 ; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, mu
1987 ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, mu
1990 ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
2002 ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu
[all …]
H A Dstepvector.ll139 ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, mu
280 ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu
352 ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
505 ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
514 ; RV64-NEXT: vsetvli a0, zero, e64, m8, ta, mu
556 ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
566 ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
583 ; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
596 ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
618 ; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
[all …]
H A Dmgather-sdnode.ll261 ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
485 ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
510 ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
536 ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
562 ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
743 ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
767 ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
792 ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
817 ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
841 ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
[all …]
H A Dfixed-vectors-reduction-int.ll127 ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
131 ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
146 ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
153 ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
473 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
477 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
530 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
550 ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
553 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
573 ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
[all …]
H A Dinsertelt-fp-rv32.ll183 ; CHECK-NEXT: vsetvli a0, zero, e16, m8, tu, mu
193 ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu
195 ; CHECK-NEXT: vsetivli zero, 4, e16, m8, tu, mu
205 ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, mu
208 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, tu, mu
358 ; CHECK-NEXT: vsetvli a0, zero, e32, m8, tu, mu
368 ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
370 ; CHECK-NEXT: vsetivli zero, 4, e32, m8, tu, mu
380 ; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, mu
383 ; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, mu
[all …]
H A Dinsertelt-fp-rv64.ll183 ; CHECK-NEXT: vsetvli a0, zero, e16, m8, tu, mu
193 ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu
195 ; CHECK-NEXT: vsetivli zero, 4, e16, m8, tu, mu
205 ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, mu
208 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, tu, mu
358 ; CHECK-NEXT: vsetvli a0, zero, e32, m8, tu, mu
368 ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
370 ; CHECK-NEXT: vsetivli zero, 4, e32, m8, tu, mu
380 ; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, mu
383 ; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, mu
[all …]
H A Dfixed-vectors-reduction-fp.ll196 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
200 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
213 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
217 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
232 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
239 ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
253 ; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu
258 ; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu
263 ; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu
1134 ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, mu
[all …]
H A Dsetcc-fp.ll1681 ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
1691 ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
1703 ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
1715 ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
1725 ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
1737 ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
1747 ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
1759 ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
1771 ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
2518 ; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
[all …]
H A Dinsertelt-int-rv64.ll218 ; CHECK-NEXT: vsetvli a1, zero, e8, m8, tu, mu
228 ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, mu
230 ; CHECK-NEXT: vsetivli zero, 4, e8, m8, tu, mu
240 ; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, mu
243 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu
428 ; CHECK-NEXT: vsetvli a1, zero, e16, m8, tu, mu
438 ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, mu
440 ; CHECK-NEXT: vsetivli zero, 4, e16, m8, tu, mu
450 ; CHECK-NEXT: vsetvli a2, zero, e16, m8, ta, mu
453 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, mu
[all …]
H A Dfixed-vectors-bitcast-large-vector.ll11 ; VLEN256-NEXT: vsetvli zero, a2, e8, m8, ta, mu
21 ; VLEN512-NEXT: vsetvli zero, a0, e8, m8, ta, mu
H A Dcalling-conv.ll14 ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
42 ; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, mu
70 ; RV64-NEXT: vsetvli a0, zero, e32, m8, ta, mu
H A Dinsertelt-int-rv32.ll218 ; CHECK-NEXT: vsetvli a1, zero, e8, m8, tu, mu
228 ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, mu
230 ; CHECK-NEXT: vsetivli zero, 4, e8, m8, tu, mu
240 ; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, mu
243 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu
428 ; CHECK-NEXT: vsetvli a1, zero, e16, m8, tu, mu
438 ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, mu
440 ; CHECK-NEXT: vsetivli zero, 4, e16, m8, tu, mu
450 ; CHECK-NEXT: vsetvli a2, zero, e16, m8, ta, mu
453 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, mu
[all …]
H A Dsetcc-integer.ll2247 ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
2255 ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
2272 ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
2280 ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
2343 ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
2351 ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
2368 ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
2376 ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
2415 ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu
2423 ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
[all …]
H A Dfixed-vectors-zext-vp.ll165 ; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, mu
167 ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
174 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
192 ; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, mu
194 ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
201 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
H A Dfixed-vectors-sext-vp.ll165 ; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, mu
167 ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
174 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
192 ; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, mu
194 ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
201 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
/llvm-project-15.0.7/llvm/test/Transforms/LoopStrengthReduce/
H A Dgnarly-setupcost.ll30 %m8 = mul i32 %a8, %m7
31 %a9 = add i32 %m8, 1
32 %m9 = mul i32 %a9, %m8
/llvm-project-15.0.7/llvm/test/MC/RISCV/rvv/
H A Dsnippet.s19 vsetvli x0, a0, e32,m8,ta,ma # Operate on 32b values
20 # CHECK-INST: 57 70 35 0d vsetvli zero, a0, e32, m8, ta, ma
/llvm-project-15.0.7/clang/test/CXX/module/module.unit/p7/
H A Dt8.cpp7 import m8; variable
/llvm-project-15.0.7/clang/test/CXX/module/module.unit/p7/Inputs/
H A Dm8.cppm3 export module m8;

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