1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV32 3; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV64 4 5declare <vscale x 1 x i8> @llvm.experimental.stepvector.nxv1i8() 6 7define <vscale x 1 x i8> @stepvector_nxv1i8() { 8; CHECK-LABEL: stepvector_nxv1i8: 9; CHECK: # %bb.0: 10; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, mu 11; CHECK-NEXT: vid.v v8 12; CHECK-NEXT: ret 13 %v = call <vscale x 1 x i8> @llvm.experimental.stepvector.nxv1i8() 14 ret <vscale x 1 x i8> %v 15} 16 17declare <vscale x 2 x i8> @llvm.experimental.stepvector.nxv2i8() 18 19define <vscale x 2 x i8> @stepvector_nxv2i8() { 20; CHECK-LABEL: stepvector_nxv2i8: 21; CHECK: # %bb.0: 22; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu 23; CHECK-NEXT: vid.v v8 24; CHECK-NEXT: ret 25 %v = call <vscale x 2 x i8> @llvm.experimental.stepvector.nxv2i8() 26 ret <vscale x 2 x i8> %v 27} 28 29declare <vscale x 3 x i8> @llvm.experimental.stepvector.nxv3i8() 30 31define <vscale x 3 x i8> @stepvector_nxv3i8() { 32; CHECK-LABEL: stepvector_nxv3i8: 33; CHECK: # %bb.0: 34; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu 35; CHECK-NEXT: vid.v v8 36; CHECK-NEXT: ret 37 %v = call <vscale x 3 x i8> @llvm.experimental.stepvector.nxv3i8() 38 ret <vscale x 3 x i8> %v 39} 40 41declare <vscale x 4 x i8> @llvm.experimental.stepvector.nxv4i8() 42 43define <vscale x 4 x i8> @stepvector_nxv4i8() { 44; CHECK-LABEL: stepvector_nxv4i8: 45; CHECK: # %bb.0: 46; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, mu 47; CHECK-NEXT: vid.v v8 48; CHECK-NEXT: ret 49 %v = call <vscale x 4 x i8> @llvm.experimental.stepvector.nxv4i8() 50 ret <vscale x 4 x i8> %v 51} 52 53declare <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8() 54 55define <vscale x 8 x i8> @stepvector_nxv8i8() { 56; CHECK-LABEL: stepvector_nxv8i8: 57; CHECK: # %bb.0: 58; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu 59; CHECK-NEXT: vid.v v8 60; CHECK-NEXT: ret 61 %v = call <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8() 62 ret <vscale x 8 x i8> %v 63} 64 65define <vscale x 8 x i8> @add_stepvector_nxv8i8() { 66; CHECK-LABEL: add_stepvector_nxv8i8: 67; CHECK: # %bb.0: # %entry 68; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu 69; CHECK-NEXT: vid.v v8 70; CHECK-NEXT: vsll.vi v8, v8, 1 71; CHECK-NEXT: ret 72entry: 73 %0 = call <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8() 74 %1 = call <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8() 75 %2 = add <vscale x 8 x i8> %0, %1 76 ret <vscale x 8 x i8> %2 77} 78 79define <vscale x 8 x i8> @mul_stepvector_nxv8i8() { 80; CHECK-LABEL: mul_stepvector_nxv8i8: 81; CHECK: # %bb.0: # %entry 82; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu 83; CHECK-NEXT: vid.v v8 84; CHECK-NEXT: li a0, 3 85; CHECK-NEXT: vmul.vx v8, v8, a0 86; CHECK-NEXT: ret 87entry: 88 %0 = insertelement <vscale x 8 x i8> poison, i8 3, i32 0 89 %1 = shufflevector <vscale x 8 x i8> %0, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 90 %2 = call <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8() 91 %3 = mul <vscale x 8 x i8> %2, %1 92 ret <vscale x 8 x i8> %3 93} 94 95define <vscale x 8 x i8> @shl_stepvector_nxv8i8() { 96; CHECK-LABEL: shl_stepvector_nxv8i8: 97; CHECK: # %bb.0: # %entry 98; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu 99; CHECK-NEXT: vid.v v8 100; CHECK-NEXT: vsll.vi v8, v8, 2 101; CHECK-NEXT: ret 102entry: 103 %0 = insertelement <vscale x 8 x i8> poison, i8 2, i32 0 104 %1 = shufflevector <vscale x 8 x i8> %0, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 105 %2 = call <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8() 106 %3 = shl <vscale x 8 x i8> %2, %1 107 ret <vscale x 8 x i8> %3 108} 109 110declare <vscale x 16 x i8> @llvm.experimental.stepvector.nxv16i8() 111 112define <vscale x 16 x i8> @stepvector_nxv16i8() { 113; CHECK-LABEL: stepvector_nxv16i8: 114; CHECK: # %bb.0: 115; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, mu 116; CHECK-NEXT: vid.v v8 117; CHECK-NEXT: ret 118 %v = call <vscale x 16 x i8> @llvm.experimental.stepvector.nxv16i8() 119 ret <vscale x 16 x i8> %v 120} 121 122declare <vscale x 32 x i8> @llvm.experimental.stepvector.nxv32i8() 123 124define <vscale x 32 x i8> @stepvector_nxv32i8() { 125; CHECK-LABEL: stepvector_nxv32i8: 126; CHECK: # %bb.0: 127; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, mu 128; CHECK-NEXT: vid.v v8 129; CHECK-NEXT: ret 130 %v = call <vscale x 32 x i8> @llvm.experimental.stepvector.nxv32i8() 131 ret <vscale x 32 x i8> %v 132} 133 134declare <vscale x 64 x i8> @llvm.experimental.stepvector.nxv64i8() 135 136define <vscale x 64 x i8> @stepvector_nxv64i8() { 137; CHECK-LABEL: stepvector_nxv64i8: 138; CHECK: # %bb.0: 139; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, mu 140; CHECK-NEXT: vid.v v8 141; CHECK-NEXT: ret 142 %v = call <vscale x 64 x i8> @llvm.experimental.stepvector.nxv64i8() 143 ret <vscale x 64 x i8> %v 144} 145 146declare <vscale x 1 x i16> @llvm.experimental.stepvector.nxv1i16() 147 148define <vscale x 1 x i16> @stepvector_nxv1i16() { 149; CHECK-LABEL: stepvector_nxv1i16: 150; CHECK: # %bb.0: 151; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu 152; CHECK-NEXT: vid.v v8 153; CHECK-NEXT: ret 154 %v = call <vscale x 1 x i16> @llvm.experimental.stepvector.nxv1i16() 155 ret <vscale x 1 x i16> %v 156} 157 158declare <vscale x 2 x i16> @llvm.experimental.stepvector.nxv2i16() 159 160define <vscale x 2 x i16> @stepvector_nxv2i16() { 161; CHECK-LABEL: stepvector_nxv2i16: 162; CHECK: # %bb.0: 163; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu 164; CHECK-NEXT: vid.v v8 165; CHECK-NEXT: ret 166 %v = call <vscale x 2 x i16> @llvm.experimental.stepvector.nxv2i16() 167 ret <vscale x 2 x i16> %v 168} 169 170declare <vscale x 2 x i15> @llvm.experimental.stepvector.nxv2i15() 171 172define <vscale x 2 x i15> @stepvector_nxv2i15() { 173; CHECK-LABEL: stepvector_nxv2i15: 174; CHECK: # %bb.0: 175; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu 176; CHECK-NEXT: vid.v v8 177; CHECK-NEXT: ret 178 %v = call <vscale x 2 x i15> @llvm.experimental.stepvector.nxv2i15() 179 ret <vscale x 2 x i15> %v 180} 181 182declare <vscale x 3 x i16> @llvm.experimental.stepvector.nxv3i16() 183 184define <vscale x 3 x i16> @stepvector_nxv3i16() { 185; CHECK-LABEL: stepvector_nxv3i16: 186; CHECK: # %bb.0: 187; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu 188; CHECK-NEXT: vid.v v8 189; CHECK-NEXT: ret 190 %v = call <vscale x 3 x i16> @llvm.experimental.stepvector.nxv3i16() 191 ret <vscale x 3 x i16> %v 192} 193 194declare <vscale x 4 x i16> @llvm.experimental.stepvector.nxv4i16() 195 196define <vscale x 4 x i16> @stepvector_nxv4i16() { 197; CHECK-LABEL: stepvector_nxv4i16: 198; CHECK: # %bb.0: 199; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu 200; CHECK-NEXT: vid.v v8 201; CHECK-NEXT: ret 202 %v = call <vscale x 4 x i16> @llvm.experimental.stepvector.nxv4i16() 203 ret <vscale x 4 x i16> %v 204} 205 206declare <vscale x 8 x i16> @llvm.experimental.stepvector.nxv8i16() 207 208define <vscale x 8 x i16> @stepvector_nxv8i16() { 209; CHECK-LABEL: stepvector_nxv8i16: 210; CHECK: # %bb.0: 211; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu 212; CHECK-NEXT: vid.v v8 213; CHECK-NEXT: ret 214 %v = call <vscale x 8 x i16> @llvm.experimental.stepvector.nxv8i16() 215 ret <vscale x 8 x i16> %v 216} 217 218declare <vscale x 16 x i16> @llvm.experimental.stepvector.nxv16i16() 219 220define <vscale x 16 x i16> @stepvector_nxv16i16() { 221; CHECK-LABEL: stepvector_nxv16i16: 222; CHECK: # %bb.0: 223; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu 224; CHECK-NEXT: vid.v v8 225; CHECK-NEXT: ret 226 %v = call <vscale x 16 x i16> @llvm.experimental.stepvector.nxv16i16() 227 ret <vscale x 16 x i16> %v 228} 229 230define <vscale x 16 x i16> @add_stepvector_nxv16i16() { 231; CHECK-LABEL: add_stepvector_nxv16i16: 232; CHECK: # %bb.0: # %entry 233; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu 234; CHECK-NEXT: vid.v v8 235; CHECK-NEXT: vsll.vi v8, v8, 1 236; CHECK-NEXT: ret 237entry: 238 %0 = call <vscale x 16 x i16> @llvm.experimental.stepvector.nxv16i16() 239 %1 = call <vscale x 16 x i16> @llvm.experimental.stepvector.nxv16i16() 240 %2 = add <vscale x 16 x i16> %0, %1 241 ret <vscale x 16 x i16> %2 242} 243 244define <vscale x 16 x i16> @mul_stepvector_nxv16i16() { 245; CHECK-LABEL: mul_stepvector_nxv16i16: 246; CHECK: # %bb.0: # %entry 247; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu 248; CHECK-NEXT: vid.v v8 249; CHECK-NEXT: li a0, 3 250; CHECK-NEXT: vmul.vx v8, v8, a0 251; CHECK-NEXT: ret 252entry: 253 %0 = insertelement <vscale x 16 x i16> poison, i16 3, i32 0 254 %1 = shufflevector <vscale x 16 x i16> %0, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer 255 %2 = call <vscale x 16 x i16> @llvm.experimental.stepvector.nxv16i16() 256 %3 = mul <vscale x 16 x i16> %2, %1 257 ret <vscale x 16 x i16> %3 258} 259 260define <vscale x 16 x i16> @shl_stepvector_nxv16i16() { 261; CHECK-LABEL: shl_stepvector_nxv16i16: 262; CHECK: # %bb.0: # %entry 263; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu 264; CHECK-NEXT: vid.v v8 265; CHECK-NEXT: vsll.vi v8, v8, 2 266; CHECK-NEXT: ret 267entry: 268 %0 = insertelement <vscale x 16 x i16> poison, i16 2, i32 0 269 %1 = shufflevector <vscale x 16 x i16> %0, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer 270 %2 = call <vscale x 16 x i16> @llvm.experimental.stepvector.nxv16i16() 271 %3 = shl <vscale x 16 x i16> %2, %1 272 ret <vscale x 16 x i16> %3 273} 274 275declare <vscale x 32 x i16> @llvm.experimental.stepvector.nxv32i16() 276 277define <vscale x 32 x i16> @stepvector_nxv32i16() { 278; CHECK-LABEL: stepvector_nxv32i16: 279; CHECK: # %bb.0: 280; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu 281; CHECK-NEXT: vid.v v8 282; CHECK-NEXT: ret 283 %v = call <vscale x 32 x i16> @llvm.experimental.stepvector.nxv32i16() 284 ret <vscale x 32 x i16> %v 285} 286 287declare <vscale x 1 x i32> @llvm.experimental.stepvector.nxv1i32() 288 289define <vscale x 1 x i32> @stepvector_nxv1i32() { 290; CHECK-LABEL: stepvector_nxv1i32: 291; CHECK: # %bb.0: 292; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu 293; CHECK-NEXT: vid.v v8 294; CHECK-NEXT: ret 295 %v = call <vscale x 1 x i32> @llvm.experimental.stepvector.nxv1i32() 296 ret <vscale x 1 x i32> %v 297} 298 299declare <vscale x 2 x i32> @llvm.experimental.stepvector.nxv2i32() 300 301define <vscale x 2 x i32> @stepvector_nxv2i32() { 302; CHECK-LABEL: stepvector_nxv2i32: 303; CHECK: # %bb.0: 304; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu 305; CHECK-NEXT: vid.v v8 306; CHECK-NEXT: ret 307 %v = call <vscale x 2 x i32> @llvm.experimental.stepvector.nxv2i32() 308 ret <vscale x 2 x i32> %v 309} 310 311declare <vscale x 3 x i32> @llvm.experimental.stepvector.nxv3i32() 312 313define <vscale x 3 x i32> @stepvector_nxv3i32() { 314; CHECK-LABEL: stepvector_nxv3i32: 315; CHECK: # %bb.0: 316; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu 317; CHECK-NEXT: vid.v v8 318; CHECK-NEXT: ret 319 %v = call <vscale x 3 x i32> @llvm.experimental.stepvector.nxv3i32() 320 ret <vscale x 3 x i32> %v 321} 322 323declare <vscale x 4 x i32> @llvm.experimental.stepvector.nxv4i32() 324 325define <vscale x 4 x i32> @stepvector_nxv4i32() { 326; CHECK-LABEL: stepvector_nxv4i32: 327; CHECK: # %bb.0: 328; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu 329; CHECK-NEXT: vid.v v8 330; CHECK-NEXT: ret 331 %v = call <vscale x 4 x i32> @llvm.experimental.stepvector.nxv4i32() 332 ret <vscale x 4 x i32> %v 333} 334 335declare <vscale x 8 x i32> @llvm.experimental.stepvector.nxv8i32() 336 337define <vscale x 8 x i32> @stepvector_nxv8i32() { 338; CHECK-LABEL: stepvector_nxv8i32: 339; CHECK: # %bb.0: 340; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu 341; CHECK-NEXT: vid.v v8 342; CHECK-NEXT: ret 343 %v = call <vscale x 8 x i32> @llvm.experimental.stepvector.nxv8i32() 344 ret <vscale x 8 x i32> %v 345} 346 347declare <vscale x 16 x i32> @llvm.experimental.stepvector.nxv16i32() 348 349define <vscale x 16 x i32> @stepvector_nxv16i32() { 350; CHECK-LABEL: stepvector_nxv16i32: 351; CHECK: # %bb.0: 352; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu 353; CHECK-NEXT: vid.v v8 354; CHECK-NEXT: ret 355 %v = call <vscale x 16 x i32> @llvm.experimental.stepvector.nxv16i32() 356 ret <vscale x 16 x i32> %v 357} 358 359define <vscale x 16 x i32> @add_stepvector_nxv16i32() { 360; CHECK-LABEL: add_stepvector_nxv16i32: 361; CHECK: # %bb.0: # %entry 362; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu 363; CHECK-NEXT: vid.v v8 364; CHECK-NEXT: vsll.vi v8, v8, 1 365; CHECK-NEXT: ret 366entry: 367 %0 = call <vscale x 16 x i32> @llvm.experimental.stepvector.nxv16i32() 368 %1 = call <vscale x 16 x i32> @llvm.experimental.stepvector.nxv16i32() 369 %2 = add <vscale x 16 x i32> %0, %1 370 ret <vscale x 16 x i32> %2 371} 372 373define <vscale x 16 x i32> @mul_stepvector_nxv16i32() { 374; CHECK-LABEL: mul_stepvector_nxv16i32: 375; CHECK: # %bb.0: # %entry 376; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu 377; CHECK-NEXT: vid.v v8 378; CHECK-NEXT: li a0, 3 379; CHECK-NEXT: vmul.vx v8, v8, a0 380; CHECK-NEXT: ret 381entry: 382 %0 = insertelement <vscale x 16 x i32> poison, i32 3, i32 0 383 %1 = shufflevector <vscale x 16 x i32> %0, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer 384 %2 = call <vscale x 16 x i32> @llvm.experimental.stepvector.nxv16i32() 385 %3 = mul <vscale x 16 x i32> %2, %1 386 ret <vscale x 16 x i32> %3 387} 388 389define <vscale x 16 x i32> @shl_stepvector_nxv16i32() { 390; CHECK-LABEL: shl_stepvector_nxv16i32: 391; CHECK: # %bb.0: # %entry 392; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu 393; CHECK-NEXT: vid.v v8 394; CHECK-NEXT: vsll.vi v8, v8, 2 395; CHECK-NEXT: ret 396entry: 397 %0 = insertelement <vscale x 16 x i32> poison, i32 2, i32 0 398 %1 = shufflevector <vscale x 16 x i32> %0, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer 399 %2 = call <vscale x 16 x i32> @llvm.experimental.stepvector.nxv16i32() 400 %3 = shl <vscale x 16 x i32> %2, %1 401 ret <vscale x 16 x i32> %3 402} 403 404declare <vscale x 1 x i64> @llvm.experimental.stepvector.nxv1i64() 405 406define <vscale x 1 x i64> @stepvector_nxv1i64() { 407; CHECK-LABEL: stepvector_nxv1i64: 408; CHECK: # %bb.0: 409; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu 410; CHECK-NEXT: vid.v v8 411; CHECK-NEXT: ret 412 %v = call <vscale x 1 x i64> @llvm.experimental.stepvector.nxv1i64() 413 ret <vscale x 1 x i64> %v 414} 415 416declare <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64() 417 418define <vscale x 2 x i64> @stepvector_nxv2i64() { 419; CHECK-LABEL: stepvector_nxv2i64: 420; CHECK: # %bb.0: 421; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu 422; CHECK-NEXT: vid.v v8 423; CHECK-NEXT: ret 424 %v = call <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64() 425 ret <vscale x 2 x i64> %v 426} 427 428declare <vscale x 3 x i64> @llvm.experimental.stepvector.nxv3i64() 429 430define <vscale x 3 x i64> @stepvector_nxv3i64() { 431; CHECK-LABEL: stepvector_nxv3i64: 432; CHECK: # %bb.0: 433; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu 434; CHECK-NEXT: vid.v v8 435; CHECK-NEXT: ret 436 %v = call <vscale x 3 x i64> @llvm.experimental.stepvector.nxv3i64() 437 ret <vscale x 3 x i64> %v 438} 439 440declare <vscale x 4 x i64> @llvm.experimental.stepvector.nxv4i64() 441 442define <vscale x 4 x i64> @stepvector_nxv4i64() { 443; CHECK-LABEL: stepvector_nxv4i64: 444; CHECK: # %bb.0: 445; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu 446; CHECK-NEXT: vid.v v8 447; CHECK-NEXT: ret 448 %v = call <vscale x 4 x i64> @llvm.experimental.stepvector.nxv4i64() 449 ret <vscale x 4 x i64> %v 450} 451 452declare <vscale x 8 x i64> @llvm.experimental.stepvector.nxv8i64() 453 454define <vscale x 8 x i64> @stepvector_nxv8i64() { 455; CHECK-LABEL: stepvector_nxv8i64: 456; CHECK: # %bb.0: 457; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu 458; CHECK-NEXT: vid.v v8 459; CHECK-NEXT: ret 460 %v = call <vscale x 8 x i64> @llvm.experimental.stepvector.nxv8i64() 461 ret <vscale x 8 x i64> %v 462} 463 464define <vscale x 8 x i64> @add_stepvector_nxv8i64() { 465; CHECK-LABEL: add_stepvector_nxv8i64: 466; CHECK: # %bb.0: # %entry 467; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu 468; CHECK-NEXT: vid.v v8 469; CHECK-NEXT: vsll.vi v8, v8, 1 470; CHECK-NEXT: ret 471entry: 472 %0 = call <vscale x 8 x i64> @llvm.experimental.stepvector.nxv8i64() 473 %1 = call <vscale x 8 x i64> @llvm.experimental.stepvector.nxv8i64() 474 %2 = add <vscale x 8 x i64> %0, %1 475 ret <vscale x 8 x i64> %2 476} 477 478define <vscale x 8 x i64> @mul_stepvector_nxv8i64() { 479; CHECK-LABEL: mul_stepvector_nxv8i64: 480; CHECK: # %bb.0: # %entry 481; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu 482; CHECK-NEXT: vid.v v8 483; CHECK-NEXT: li a0, 3 484; CHECK-NEXT: vmul.vx v8, v8, a0 485; CHECK-NEXT: ret 486entry: 487 %0 = insertelement <vscale x 8 x i64> poison, i64 3, i32 0 488 %1 = shufflevector <vscale x 8 x i64> %0, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 489 %2 = call <vscale x 8 x i64> @llvm.experimental.stepvector.nxv8i64() 490 %3 = mul <vscale x 8 x i64> %2, %1 491 ret <vscale x 8 x i64> %3 492} 493 494define <vscale x 8 x i64> @mul_bigimm_stepvector_nxv8i64() { 495; RV32-LABEL: mul_bigimm_stepvector_nxv8i64: 496; RV32: # %bb.0: # %entry 497; RV32-NEXT: addi sp, sp, -16 498; RV32-NEXT: .cfi_def_cfa_offset 16 499; RV32-NEXT: li a0, 7 500; RV32-NEXT: sw a0, 12(sp) 501; RV32-NEXT: lui a0, 797989 502; RV32-NEXT: addi a0, a0, -683 503; RV32-NEXT: sw a0, 8(sp) 504; RV32-NEXT: addi a0, sp, 8 505; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu 506; RV32-NEXT: vlse64.v v8, (a0), zero 507; RV32-NEXT: vid.v v16 508; RV32-NEXT: vmul.vv v8, v16, v8 509; RV32-NEXT: addi sp, sp, 16 510; RV32-NEXT: ret 511; 512; RV64-LABEL: mul_bigimm_stepvector_nxv8i64: 513; RV64: # %bb.0: # %entry 514; RV64-NEXT: vsetvli a0, zero, e64, m8, ta, mu 515; RV64-NEXT: vid.v v8 516; RV64-NEXT: lui a0, 1987 517; RV64-NEXT: addiw a0, a0, -731 518; RV64-NEXT: slli a0, a0, 12 519; RV64-NEXT: addi a0, a0, -683 520; RV64-NEXT: vmul.vx v8, v8, a0 521; RV64-NEXT: ret 522entry: 523 %0 = insertelement <vscale x 8 x i64> poison, i64 33333333333, i32 0 524 %1 = shufflevector <vscale x 8 x i64> %0, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 525 %2 = call <vscale x 8 x i64> @llvm.experimental.stepvector.nxv8i64() 526 %3 = mul <vscale x 8 x i64> %2, %1 527 ret <vscale x 8 x i64> %3 528} 529 530define <vscale x 8 x i64> @shl_stepvector_nxv8i64() { 531; CHECK-LABEL: shl_stepvector_nxv8i64: 532; CHECK: # %bb.0: # %entry 533; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu 534; CHECK-NEXT: vid.v v8 535; CHECK-NEXT: vsll.vi v8, v8, 2 536; CHECK-NEXT: ret 537entry: 538 %0 = insertelement <vscale x 8 x i64> poison, i64 2, i32 0 539 %1 = shufflevector <vscale x 8 x i64> %0, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 540 %2 = call <vscale x 8 x i64> @llvm.experimental.stepvector.nxv8i64() 541 %3 = shl <vscale x 8 x i64> %2, %1 542 ret <vscale x 8 x i64> %3 543} 544 545declare <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64() 546 547define <vscale x 16 x i64> @stepvector_nxv16i64() { 548; RV32-LABEL: stepvector_nxv16i64: 549; RV32: # %bb.0: 550; RV32-NEXT: addi sp, sp, -16 551; RV32-NEXT: .cfi_def_cfa_offset 16 552; RV32-NEXT: sw zero, 12(sp) 553; RV32-NEXT: csrr a0, vlenb 554; RV32-NEXT: sw a0, 8(sp) 555; RV32-NEXT: addi a0, sp, 8 556; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu 557; RV32-NEXT: vlse64.v v16, (a0), zero 558; RV32-NEXT: vid.v v8 559; RV32-NEXT: vadd.vv v16, v8, v16 560; RV32-NEXT: addi sp, sp, 16 561; RV32-NEXT: ret 562; 563; RV64-LABEL: stepvector_nxv16i64: 564; RV64: # %bb.0: 565; RV64-NEXT: csrr a0, vlenb 566; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu 567; RV64-NEXT: vid.v v8 568; RV64-NEXT: vadd.vx v16, v8, a0 569; RV64-NEXT: ret 570 %v = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64() 571 ret <vscale x 16 x i64> %v 572} 573 574define <vscale x 16 x i64> @add_stepvector_nxv16i64() { 575; RV32-LABEL: add_stepvector_nxv16i64: 576; RV32: # %bb.0: # %entry 577; RV32-NEXT: addi sp, sp, -16 578; RV32-NEXT: .cfi_def_cfa_offset 16 579; RV32-NEXT: sw zero, 12(sp) 580; RV32-NEXT: csrr a0, vlenb 581; RV32-NEXT: slli a0, a0, 1 582; RV32-NEXT: sw a0, 8(sp) 583; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu 584; RV32-NEXT: addi a0, sp, 8 585; RV32-NEXT: vlse64.v v16, (a0), zero 586; RV32-NEXT: vid.v v8 587; RV32-NEXT: vsll.vi v8, v8, 1 588; RV32-NEXT: vadd.vv v16, v8, v16 589; RV32-NEXT: addi sp, sp, 16 590; RV32-NEXT: ret 591; 592; RV64-LABEL: add_stepvector_nxv16i64: 593; RV64: # %bb.0: # %entry 594; RV64-NEXT: csrr a0, vlenb 595; RV64-NEXT: slli a0, a0, 1 596; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu 597; RV64-NEXT: vid.v v8 598; RV64-NEXT: vsll.vi v8, v8, 1 599; RV64-NEXT: vadd.vx v16, v8, a0 600; RV64-NEXT: ret 601entry: 602 %0 = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64() 603 %1 = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64() 604 %2 = add <vscale x 16 x i64> %0, %1 605 ret <vscale x 16 x i64> %2 606} 607 608define <vscale x 16 x i64> @mul_stepvector_nxv16i64() { 609; RV32-LABEL: mul_stepvector_nxv16i64: 610; RV32: # %bb.0: # %entry 611; RV32-NEXT: addi sp, sp, -16 612; RV32-NEXT: .cfi_def_cfa_offset 16 613; RV32-NEXT: sw zero, 12(sp) 614; RV32-NEXT: csrr a0, vlenb 615; RV32-NEXT: slli a1, a0, 1 616; RV32-NEXT: add a0, a1, a0 617; RV32-NEXT: sw a0, 8(sp) 618; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu 619; RV32-NEXT: addi a0, sp, 8 620; RV32-NEXT: vlse64.v v16, (a0), zero 621; RV32-NEXT: vid.v v8 622; RV32-NEXT: li a0, 3 623; RV32-NEXT: vmul.vx v8, v8, a0 624; RV32-NEXT: vadd.vv v16, v8, v16 625; RV32-NEXT: addi sp, sp, 16 626; RV32-NEXT: ret 627; 628; RV64-LABEL: mul_stepvector_nxv16i64: 629; RV64: # %bb.0: # %entry 630; RV64-NEXT: vsetvli a0, zero, e64, m8, ta, mu 631; RV64-NEXT: vid.v v8 632; RV64-NEXT: li a0, 3 633; RV64-NEXT: vmul.vx v8, v8, a0 634; RV64-NEXT: csrr a0, vlenb 635; RV64-NEXT: slli a1, a0, 1 636; RV64-NEXT: add a0, a1, a0 637; RV64-NEXT: vadd.vx v16, v8, a0 638; RV64-NEXT: ret 639entry: 640 %0 = insertelement <vscale x 16 x i64> poison, i64 3, i32 0 641 %1 = shufflevector <vscale x 16 x i64> %0, <vscale x 16 x i64> poison, <vscale x 16 x i32> zeroinitializer 642 %2 = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64() 643 %3 = mul <vscale x 16 x i64> %2, %1 644 ret <vscale x 16 x i64> %3 645} 646 647define <vscale x 16 x i64> @mul_bigimm_stepvector_nxv16i64() { 648; RV32-LABEL: mul_bigimm_stepvector_nxv16i64: 649; RV32: # %bb.0: # %entry 650; RV32-NEXT: addi sp, sp, -16 651; RV32-NEXT: .cfi_def_cfa_offset 16 652; RV32-NEXT: li a0, 7 653; RV32-NEXT: sw a0, 12(sp) 654; RV32-NEXT: lui a0, 797989 655; RV32-NEXT: addi a0, a0, -683 656; RV32-NEXT: sw a0, 8(sp) 657; RV32-NEXT: csrr a0, vlenb 658; RV32-NEXT: lui a1, 11557 659; RV32-NEXT: addi a1, a1, -683 660; RV32-NEXT: mul a1, a0, a1 661; RV32-NEXT: sw a1, 8(sp) 662; RV32-NEXT: srli a0, a0, 3 663; RV32-NEXT: li a1, 62 664; RV32-NEXT: mul a1, a0, a1 665; RV32-NEXT: lui a2, 92455 666; RV32-NEXT: addi a2, a2, -1368 667; RV32-NEXT: mulhu a0, a0, a2 668; RV32-NEXT: add a0, a0, a1 669; RV32-NEXT: sw a0, 12(sp) 670; RV32-NEXT: addi a0, sp, 8 671; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu 672; RV32-NEXT: vlse64.v v8, (a0), zero 673; RV32-NEXT: vlse64.v v16, (a0), zero 674; RV32-NEXT: vid.v v24 675; RV32-NEXT: vmul.vv v8, v24, v8 676; RV32-NEXT: vadd.vv v16, v8, v16 677; RV32-NEXT: addi sp, sp, 16 678; RV32-NEXT: ret 679; 680; RV64-LABEL: mul_bigimm_stepvector_nxv16i64: 681; RV64: # %bb.0: # %entry 682; RV64-NEXT: csrr a0, vlenb 683; RV64-NEXT: lui a1, 1987 684; RV64-NEXT: addiw a1, a1, -731 685; RV64-NEXT: slli a1, a1, 12 686; RV64-NEXT: addi a1, a1, -683 687; RV64-NEXT: mul a0, a0, a1 688; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu 689; RV64-NEXT: vid.v v8 690; RV64-NEXT: vmul.vx v8, v8, a1 691; RV64-NEXT: vadd.vx v16, v8, a0 692; RV64-NEXT: ret 693entry: 694 %0 = insertelement <vscale x 16 x i64> poison, i64 33333333333, i32 0 695 %1 = shufflevector <vscale x 16 x i64> %0, <vscale x 16 x i64> poison, <vscale x 16 x i32> zeroinitializer 696 %2 = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64() 697 %3 = mul <vscale x 16 x i64> %2, %1 698 ret <vscale x 16 x i64> %3 699} 700 701define <vscale x 16 x i64> @shl_stepvector_nxv16i64() { 702; RV32-LABEL: shl_stepvector_nxv16i64: 703; RV32: # %bb.0: # %entry 704; RV32-NEXT: addi sp, sp, -16 705; RV32-NEXT: .cfi_def_cfa_offset 16 706; RV32-NEXT: sw zero, 12(sp) 707; RV32-NEXT: csrr a0, vlenb 708; RV32-NEXT: slli a0, a0, 2 709; RV32-NEXT: sw a0, 8(sp) 710; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu 711; RV32-NEXT: addi a0, sp, 8 712; RV32-NEXT: vlse64.v v16, (a0), zero 713; RV32-NEXT: vid.v v8 714; RV32-NEXT: vsll.vi v8, v8, 2 715; RV32-NEXT: vadd.vv v16, v8, v16 716; RV32-NEXT: addi sp, sp, 16 717; RV32-NEXT: ret 718; 719; RV64-LABEL: shl_stepvector_nxv16i64: 720; RV64: # %bb.0: # %entry 721; RV64-NEXT: csrr a0, vlenb 722; RV64-NEXT: slli a0, a0, 2 723; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu 724; RV64-NEXT: vid.v v8 725; RV64-NEXT: vsll.vi v8, v8, 2 726; RV64-NEXT: vadd.vx v16, v8, a0 727; RV64-NEXT: ret 728entry: 729 %0 = insertelement <vscale x 16 x i64> poison, i64 2, i32 0 730 %1 = shufflevector <vscale x 16 x i64> %0, <vscale x 16 x i64> poison, <vscale x 16 x i32> zeroinitializer 731 %2 = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64() 732 %3 = shl <vscale x 16 x i64> %2, %1 733 ret <vscale x 16 x i64> %3 734} 735