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Searched refs:lds_param_load (Results 1 – 8 of 8) sorted by relevance

/llvm-project-15.0.7/llvm/test/MC/AMDGPU/
H A Dldsdir.s54 lds_param_load v1, attr0.x wait_vdst:15 label
57 lds_param_load v2, attr0.y wait_vdst:14 label
60 lds_param_load v3, attr0.z wait_vdst:13 label
63 lds_param_load v4, attr0.w wait_vdst:12 label
66 lds_param_load v5, attr0.x wait_vdst:11 label
69 lds_param_load v6, attr1.x wait_vdst:10 label
72 lds_param_load v7, attr2.y wait_vdst:9 label
75 lds_param_load v8, attr3.z wait_vdst:8 label
78 lds_param_load v9, attr4.w wait_vdst:7 label
81 lds_param_load v10, attr11.x wait_vdst:6 label
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dllvm.amdgcn.lds.param.load.ll4 ; GFX11-LABEL: {{^}}lds_param_load:
6 ; GFX11-DAG: lds_param_load v{{[0-9]+}}, attr0.x
7 ; GFX11-DAG: lds_param_load v{{[0-9]+}}, attr0.y
8 ; GFX11-DAG: lds_param_load v{{[0-9]+}}, attr0.z
9 ; GFX11-DAG: lds_param_load v{{[0-9]+}}, attr0.w
10 ; GFX11-DAG: lds_param_load v{{[0-9]+}}, attr1.x
23 define amdgpu_ps void @lds_param_load(<4 x i32> inreg %buf, i32 inreg %arg) #0 {
26 ; Ensure memory clustering is occuring for lds_param_load
H A Dllvm.amdgcn.interp.inreg.ll10 ; GCN-NEXT: lds_param_load v0, attr0.y wait_vdst:15
11 ; GCN-NEXT: lds_param_load v1, attr1.x wait_vdst:15
40 ; GCN-NEXT: lds_param_load v0, attr0.x wait_vdst:15
41 ; GCN-NEXT: lds_param_load v1, attr1.x wait_vdst:15
42 ; GCN-NEXT: lds_param_load v2, attr2.x wait_vdst:15
43 ; GCN-NEXT: lds_param_load v3, attr3.x wait_vdst:15
83 ; GCN-NEXT: lds_param_load v2, attr0.x wait_vdst:15
84 ; GCN-NEXT: lds_param_load v3, attr1.x wait_vdst:15
85 ; GCN-NEXT: lds_param_load v4, attr2.x wait_vdst:15
86 ; GCN-NEXT: lds_param_load v5, attr3.x wait_vdst:15
[all …]
H A Dwqm-gfx11.ll11 ; CHECK-NEXT: lds_param_load v3, attr0.x wait_vdst:15
12 ; CHECK-NEXT: lds_param_load v4, attr0.y wait_vdst:15
13 ; CHECK-NEXT: lds_param_load v5, attr0.z wait_vdst:15
H A Ddual-source-blend-export.ll12 ; GCN-NEXT: lds_param_load v3, attr1.x wait_vdst:15
13 ; GCN-NEXT: lds_param_load v4, attr1.y wait_vdst:15
14 ; GCN-NEXT: lds_param_load v5, attr1.z wait_vdst:15
15 ; GCN-NEXT: lds_param_load v6, attr1.w wait_vdst:15
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dllvm.amdgcn.interp.inreg.ll10 ; GCN-NEXT: lds_param_load v0, attr0.y wait_vdst:15
11 ; GCN-NEXT: lds_param_load v1, attr1.x wait_vdst:15
40 ; GCN-NEXT: lds_param_load v0, attr0.x wait_vdst:15
41 ; GCN-NEXT: lds_param_load v1, attr1.x wait_vdst:15
42 ; GCN-NEXT: lds_param_load v2, attr2.x wait_vdst:15
43 ; GCN-NEXT: lds_param_load v3, attr3.x wait_vdst:15
83 ; GCN-NEXT: lds_param_load v2, attr0.x wait_vdst:15
84 ; GCN-NEXT: lds_param_load v3, attr1.x wait_vdst:15
85 ; GCN-NEXT: lds_param_load v4, attr2.x wait_vdst:15
86 ; GCN-NEXT: lds_param_load v5, attr3.x wait_vdst:15
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DLDSDIRInstructions.td92 def LDS_PARAM_LOAD : LDSDIR_Pseudo<"lds_param_load", 0>;
/llvm-project-15.0.7/llvm/test/MC/Disassembler/AMDGPU/
H A Dgfx11_dasm_all.txt9907 # GFX11: lds_param_load v16, attr63.w ; encoding: [0x10,0xff,0x00,0xce]
9910 # GFX11: lds_param_load v17, attr63.w ; encoding: [0x11,0xff,0x00,0xce]
9913 # GFX11: lds_param_load v1, attr0.x wait_vdst:15 ; encoding: [0x01,0x00,0x0f,0xce]
9916 # GFX11: lds_param_load v2, attr0.y wait_vdst:14 ; encoding: [0x02,0x01,0x0e,0xce]
9919 # GFX11: lds_param_load v3, attr0.z wait_vdst:13 ; encoding: [0x03,0x02,0x0d,0xce]
9922 # GFX11: lds_param_load v4, attr0.w wait_vdst:12 ; encoding: [0x04,0x03,0x0c,0xce]
9925 # GFX11: lds_param_load v5, attr0.x wait_vdst:11 ; encoding: [0x05,0x00,0x0b,0xce]
9928 # GFX11: lds_param_load v6, attr1.x wait_vdst:10 ; encoding: [0x06,0x04,0x0a,0xce]
9931 # GFX11: lds_param_load v7, attr2.y wait_vdst:9 ; encoding: [0x07,0x09,0x09,0xce]
9934 # GFX11: lds_param_load v8, attr3.z wait_vdst:8 ; encoding: [0x08,0x0e,0x08,0xce]
[all …]