1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s -check-prefix=GCN 3 4; This is a slightly modified IR from real case to make it concise. 5define amdgpu_ps void @_amdgpu_ps_main(i32 inreg %PrimMask, <2 x float> %InterpCenter) #0 { 6; GCN-LABEL: _amdgpu_ps_main: 7; GCN: ; %bb.0: ; %.entry 8; GCN-NEXT: s_mov_b32 s1, exec_lo 9; GCN-NEXT: s_wqm_b32 exec_lo, exec_lo 10; GCN-NEXT: s_mov_b32 m0, s0 11; GCN-NEXT: v_mbcnt_lo_u32_b32 v7, -1, 0 12; GCN-NEXT: lds_param_load v3, attr1.x wait_vdst:15 13; GCN-NEXT: lds_param_load v4, attr1.y wait_vdst:15 14; GCN-NEXT: lds_param_load v5, attr1.z wait_vdst:15 15; GCN-NEXT: lds_param_load v6, attr1.w wait_vdst:15 16; GCN-NEXT: v_mbcnt_hi_u32_b32 v7, -1, v7 17; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) 18; GCN-NEXT: v_dual_mov_b32 v2, v0 :: v_dual_and_b32 v7, 1, v7 19; GCN-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7 20; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) 21; GCN-NEXT: v_interp_p10_f32 v8, v4, v2, v4 wait_exp:2 22; GCN-NEXT: v_interp_p10_f32 v10, v5, v2, v5 wait_exp:1 23; GCN-NEXT: v_interp_p10_f32 v9, v6, v2, v6 24; GCN-NEXT: v_interp_p10_f32 v2, v3, v2, v3 wait_exp:7 25; GCN-NEXT: v_interp_p2_f32 v4, v4, v1, v8 wait_exp:7 26; GCN-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) 27; GCN-NEXT: v_interp_p2_f32 v5, v5, v1, v10 wait_exp:7 28; GCN-NEXT: v_interp_p2_f32 v6, v6, v1, v9 wait_exp:7 29; GCN-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) 30; GCN-NEXT: v_interp_p2_f32 v2, v3, v1, v2 wait_exp:7 31; GCN-NEXT: v_mov_b32_dpp v4, v4 dpp8:[1,0,3,2,5,4,7,6] 32; GCN-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) 33; GCN-NEXT: v_mov_b32_dpp v6, v6 dpp8:[1,0,3,2,5,4,7,6] 34; GCN-NEXT: v_dual_cndmask_b32 v3, v4, v5 :: v_dual_cndmask_b32 v4, v5, v4 35; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3) 36; GCN-NEXT: v_cndmask_b32_e32 v5, v2, v6, vcc_lo 37; GCN-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo 38; GCN-NEXT: v_mov_b32_dpp v4, v4 dpp8:[1,0,3,2,5,4,7,6] 39; GCN-NEXT: s_delay_alu instid0(VALU_DEP_3) 40; GCN-NEXT: v_mov_b32_dpp v5, v5 dpp8:[1,0,3,2,5,4,7,6] 41; GCN-NEXT: s_mov_b32 exec_lo, s1 42; GCN-NEXT: exp dual_src_blend0 v3, v2, off, off 43; GCN-NEXT: exp dual_src_blend1 v4, v5, off, off done 44; GCN-NEXT: s_endpgm 45.entry: 46 %InterpCenter.i0 = extractelement <2 x float> %InterpCenter, i64 0 47 %InterpCenter.i1 = extractelement <2 x float> %InterpCenter, i64 1 48 %i6 = call float @llvm.amdgcn.lds.param.load(i32 immarg 0, i32 immarg 1, i32 %PrimMask) 49 %i7 = call float @llvm.amdgcn.lds.param.load(i32 immarg 1, i32 immarg 1, i32 %PrimMask) 50 %i8 = call float @llvm.amdgcn.lds.param.load(i32 immarg 2, i32 immarg 1, i32 %PrimMask) 51 %i9 = call float @llvm.amdgcn.lds.param.load(i32 immarg 3, i32 immarg 1, i32 %PrimMask) 52 53 %i14 = call float @llvm.amdgcn.interp.inreg.p10(float %i8, float %InterpCenter.i0, float %i8) 54 %i15 = call float @llvm.amdgcn.interp.inreg.p2(float %i8, float %InterpCenter.i1, float %i14) 55 56 %i16 = call float @llvm.amdgcn.interp.inreg.p10(float %i7, float %InterpCenter.i0, float %i7) 57 %i17 = call float @llvm.amdgcn.interp.inreg.p2(float %i7, float %InterpCenter.i1, float %i16) 58 59 %i18 = call float @llvm.amdgcn.interp.inreg.p10(float %i6, float %InterpCenter.i0, float %i6) 60 %i19 = call float @llvm.amdgcn.interp.inreg.p2(float %i6, float %InterpCenter.i1, float %i18) 61 62 %i20 = call float @llvm.amdgcn.interp.inreg.p10(float %i9, float %InterpCenter.i0, float %i9) 63 %i21 = call float @llvm.amdgcn.interp.inreg.p2(float %i9, float %InterpCenter.i1, float %i20) 64 65 %i34 = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) 66 %i35 = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %i34) 67 %i36 = and i32 %i35, 1 68 %.not = icmp eq i32 %i36, 0 69 70 %i37 = bitcast float %i15 to i32 71 %i38 = bitcast float %i17 to i32 72 %i39 = call i32 @llvm.amdgcn.mov.dpp8.i32(i32 %i38, i32 14570689) 73 %i40 = select i1 %.not, i32 %i37, i32 %i39 74 %i41 = bitcast i32 %i40 to float 75 %i42 = select i1 %.not, i32 %i39, i32 %i37 76 %i43 = call i32 @llvm.amdgcn.mov.dpp8.i32(i32 %i42, i32 14570689) 77 %i44 = bitcast i32 %i43 to float 78 79 %i45 = bitcast float %i19 to i32 80 %i46 = bitcast float %i21 to i32 81 %i47 = call i32 @llvm.amdgcn.mov.dpp8.i32(i32 %i46, i32 14570689) 82 %i48 = select i1 %.not, i32 %i45, i32 %i47 83 %i49 = bitcast i32 %i48 to float 84 %i50 = select i1 %.not, i32 %i47, i32 %i45 85 %i51 = call i32 @llvm.amdgcn.mov.dpp8.i32(i32 %i50, i32 14570689) 86 %i52 = bitcast i32 %i51 to float 87 call void @llvm.amdgcn.exp.f32(i32 immarg 21, i32 immarg 3, float %i41, float %i49, float undef, float undef, i1 immarg false, i1 immarg true) 88 call void @llvm.amdgcn.exp.f32(i32 immarg 22, i32 immarg 3, float %i44, float %i52, float undef, float undef, i1 immarg true, i1 immarg true) 89 ret void 90} 91 92declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #2 93declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #2 94declare i32 @llvm.amdgcn.mov.dpp8.i32(i32, i32 immarg) #3 95declare void @llvm.amdgcn.exp.f32(i32 immarg, i32 immarg, float, float, float, float, i1 immarg, i1 immarg) #4 96declare float @llvm.amdgcn.interp.inreg.p10(float, float, float) #1 97declare float @llvm.amdgcn.interp.inreg.p2(float, float, float) #1 98declare float @llvm.amdgcn.lds.param.load(i32 immarg, i32 immarg, i32) #1 99 100attributes #0 = { nounwind } 101attributes #1 = { nounwind readnone speculatable willreturn } 102attributes #2 = { nounwind readnone willreturn } 103attributes #3 = { convergent nounwind readnone willreturn } 104attributes #4 = { inaccessiblememonly nounwind willreturn writeonly } 105