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Searched refs:isZExt (Results 1 – 21 of 21) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMFastISel.cpp189 bool isZExt);
912 Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8; in ARMEmitLoad()
916 if (isZExt) { in ARMEmitLoad()
932 Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8; in ARMEmitLoad()
936 Opc = isZExt ? ARM::LDRH : ARM::LDRSH; in ARMEmitLoad()
1338 bool isZExt) { in ARMEmitCmp() argument
2604 bool isZExt) { in ARMEmitIntExt() argument
2749 bool isZExt = isa<ZExtInst>(I); in SelectIntExt() local
2899 uint8_t isZExt : 1; member
2929 bool isZExt; in tryToFoldLoadIntoMI() local
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/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DMachineFrameInfo.h176 bool isZExt = false; member
529 return Objects[ObjectIdx+NumFixedObjects].isZExt; in isObjectZExt()
535 Objects[ObjectIdx+NumFixedObjects].isZExt = IsZExt; in setObjectZExt()
H A DTargetCallingConv.h73 bool isZExt() const { return IsZExt; } in isZExt() function
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCMachineFunctionInfo.cpp71 return LiveIn.second.isZExt(); in isLiveInZExt()
H A DPPCFastISel.cpp159 bool isZExt, unsigned DestReg,
H A DPPCISelLowering.cpp4262 else if (Flags.isZExt()) in extendArgForPPC64()
6848 else if (Flags.isZExt()) in truncateScalarIntegerArg()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp183 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
1750 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) { in selectRet()
1751 bool IsZExt = Outs[0].Flags.isZExt(); in selectRet()
1800 bool isZExt = isa<ZExtInst>(I); in selectIntExt() local
1817 if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt)) in selectIntExt()
1903 bool isZExt) { in emitIntExt() argument
1905 bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt); in emitIntExt()
H A DMipsISelLowering.cpp2888 else if (ArgFlags.isZExt()) in CC_MipsO32()
2900 else if (ArgFlags.isZExt()) in CC_MipsO32()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallingConv.td16 : CCIf<"ArgFlags.isSExt() || ArgFlags.isZExt()", A>;
H A DAMDGPUCallLowering.cpp317 } else if (RetInfo.Flags[0].isZExt()) { in lowerReturnVal()
H A DSIISelLowering.cpp1695 if (Arg && (Arg->Flags.isSExt() || Arg->Flags.isZExt()) && in convertArgType()
1697 unsigned Opc = Arg->Flags.isZExt() ? ISD::AssertZext : ISD::AssertSext; in convertArgType()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp353 } else if (Flags.isZExt()) { in buildCopyFromRegs()
558 if (Flags.isZExt()) in extendOpFromFlags()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZCallingConv.td12 : CCIf<"ArgFlags.isSExt() || ArgFlags.isZExt()", A>;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp572 if (!OrigArg.Flags[0].isZExt()) { in lowerFormalArguments()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp232 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
233 unsigned emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
3838 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) in selectRet()
3841 bool IsZExt = Outs[0].Flags.isZExt(); in selectRet()
H A DAArch64ISelLowering.cpp5982 if (!Ins[i].Flags.isZExt()) { in LowerFormalArguments()
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp380 else if (ArgFlags.isZExt()) in CC_Lanai32_VarArg()
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp508 else if (ArgFlags.isZExt()) in AnalyzeArguments()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86FastISel.cpp1246 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) in X86SelectRet()
1258 unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND : in X86SelectRet()
H A DX86ISelLowering.cpp5031 if (Flags.isZExt() != MFI.isObjectZExt(FI) || in MatchingStackOffset()
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp322 if (Flags.isZExt() != MFI.isObjectZExt(FI) || in MatchingStackOffset()