| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | MachineCycleAnalysis.cpp | 109 if (MO.isUse()) { in isCycleInvariant()
134 if (!MO.isUse()) in isCycleInvariant()
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| H A D | ProcessImplicitDefs.cpp | 76 if (MO.isReg() && MO.isUse() && MO.readsReg()) in canTurnIntoImplicitDef()
116 if (MO.isUse()) in processImplicitDef()
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| H A D | MachineLoopInfo.cpp | 172 if (MO.isUse()) { in isLoopInvariant()
194 if (!MO.isUse()) in isLoopInvariant()
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| H A D | MachineInstr.cpp | 261 if (NewMO->isUse()) { in addOperand()
271 if (NewMO->isUse() && isDebugInstr()) in addOperand()
949 if (!MO.isReg() || !MO.isUse()) in findRegisterUseOperandIdx()
977 if (MO.isUse()) in readsWritesVirtualRegister()
1056 assert(UseMO.isUse() && "UseIdx must be a use operand"); in tieOperands()
1090 if (MO.isUse()) in findTiedOperandIdx()
1095 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1) in findTiedOperandIdx()
1157 if (MO.isReg() && MO.isUse()) in clearKillInfo()
1424 if (!MO.isReg() || MO.isUse()) in allDefsAreDead()
1832 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) in addRegisterKilled()
[all …]
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| H A D | BreakFalseDeps.cpp | 197 if (!MO.isReg() || !MO.getReg() || !MO.isUse() || !MO.isUndef()) in processDefs()
222 if (MO.isUse()) in processDefs()
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| H A D | TwoAddressInstructionPass.cpp | 256 if (MO.isUse() && DI->second < LastUse) in noUseAfterLastDef()
364 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) in isTwoAddrUse()
410 if (MO.isReg() && MO.isUse() && in findOnlyInterestingUse()
1042 if (MO.isUse()) { in rescheduleKillAboveMI()
1081 if (MO.isUse()) { in rescheduleKillAboveMI()
1344 if (MO.isUse()) { in tryInstructionTransform()
1428 assert(SrcReg && SrcMO.isUse() && "two address instruction invalid"); in collectTiedOperands()
1549 assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() && in processTiedPairs()
1570 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) { in processTiedPairs()
1623 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) { in processTiedPairs()
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| H A D | MachineSink.cpp | 606 if (!MO.isReg() || !MO.isUse()) in isWorthBreakingCriticalEdge()
809 if (MO.isUse() && in isProfitableToSinkTo()
914 if (MO.isUse()) { in FindSuccToSinkTo()
926 if (MO.isUse()) continue; in FindSuccToSinkTo()
1325 if (MO.isUse()) { in blockPrologueInterferes()
1387 if (!MO.isReg() || MO.isUse()) in SinkInstruction()
1502 if (MO.isReg() && MO.isUse()) in SinkInstruction()
1740 } else if (MO.isUse()) { in hasRegisterDependency()
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| H A D | CriticalAntiDepBreaker.cpp | 214 if (MO.isUse() && Special) { in PrescanInstruction()
319 if (!MO.isUse()) continue; in ScanInstruction()
623 if (MO.isUse() && TRI->regsOverlap(AntiDepReg, Reg)) { in BreakAntiDependencies()
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| H A D | LiveIntervals.cpp | 787 if (MO.isUse()) { in addKillFlags()
863 float LiveIntervals::getSpillWeight(bool isDef, bool isUse, in getSpillWeight() argument
866 return getSpillWeight(isDef, isUse, MBFI, MI.getParent()); in getSpillWeight()
869 float LiveIntervals::getSpillWeight(bool isDef, bool isUse, in getSpillWeight() argument
872 return (isDef + isUse) * MBFI->getBlockFreqRelativeToEntryBlock(MBB); in getSpillWeight()
1017 if (MO.isUse()) { in updateAllRanges()
1121 if (MOP.isReg() && MOP.isUse()) in handleMoveDown()
1422 if (MO->isReg() && !MO->isUse()) in handleMoveUp()
1636 } else if (MO.isUse()) { in repairOldRegInRange()
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| H A D | DeadMachineInstructionElim.cpp | 172 if (MO.isReg() && MO.isUse()) { in eliminateDeadMI()
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| H A D | InlineSpiller.cpp | 580 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg()) in reMaterializeFor()
644 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg()) { in reMaterializeFor()
841 if (MO.isUse() && !MO.readsReg() && !MO.isTied()) in foldMemoryOperand()
873 if (MO.isUse()) in foldMemoryOperand()
901 if (MO->isUse()) in foldMemoryOperand()
1136 if (MO.isUse()) { in spillAroundUses()
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| H A D | RegisterScavenging.cpp | 139 if (MO.isUse()) { in determineKillsAndDefs()
189 if (MO.isUse()) { in forward()
528 if (MO.isReg() && MO.getReg() != 0 && !(MO.isUse() && MO.isUndef()) && in scavengeRegister()
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| H A D | MachineCSE.cpp | 174 if (!MO.isReg() || !MO.isUse()) in INITIALIZE_PASS_DEPENDENCY()
246 if (MO.isUse()) in isPhysDefTriviallyDead()
471 if (MO.isReg() && MO.isUse() && Register::isVirtualRegister(MO.getReg())) { in isProfitableToCSE()
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| /llvm-project-15.0.7/llvm/lib/Target/Sparc/ |
| H A D | DelaySlotFiller.cpp | 265 if (MO.isUse()) { in delayHasHazard()
306 assert(Reg.isUse() && "CALL first operand is not a use."); in insertCallDefsUses()
313 assert(Operand1.isUse() && "CALLrr second operand is not a use."); in insertCallDefsUses()
333 if (MO.isUse()) { in insertDefsUses()
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| /llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/ |
| H A D | MCInstrDescView.cpp | 46 bool Operand::isUse() const { return !IsDef; } in isUse() function in llvm::exegesis::Operand
177 if (Op.isUse()) in create()
181 if (Op.isUse() && Op.isImplicit()) in create()
260 if (Op.isUse()) in dump()
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| H A D | ParallelSnippetGenerator.cpp | 198 if (Op.isUse()) in generateCodeTemplates()
237 if (Op.isReg() && Op.isExplicit() && Op.isUse() && !Op.isMemory()) { in generateCodeTemplates()
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| H A D | MCInstrDescView.h | 71 bool isUse() const;
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| /llvm-project-15.0.7/llvm/lib/Target/Lanai/ |
| H A D | LanaiDelaySlotFiller.cpp | 213 if (MO.isUse()) { in delayHasHazard()
239 else if (MO.isUse()) in insertDefsUses()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenPredicate.cpp | 258 assert(DefI->getOperand(0).isDef() && DefI->getOperand(1).isUse()); in getPredRegFor()
354 if (MO.isReg() && MO.isUse()) in isScalarPred()
375 if (!MO.isReg() || !MO.isUse()) in convertToPredForm()
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| H A D | HexagonNewValueJump.cpp | 177 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) { in INITIALIZE_PASS_DEPENDENCY()
648 if (!MO.isReg() || !MO.isUse()) in runOnMachineFunction()
655 if (!Op.isReg() || !Op.isUse() || !Op.isKill()) in runOnMachineFunction()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86FixupBWInsts.cpp | 266 assert((MO.isDef() || MO.isUse()) && "Expected Def or Use only!"); in getSuperRegDestIfDead()
275 if (MO.isUse() && !TRI->isSubRegisterEq(OrigDestReg, MO.getReg()) && in getSuperRegDestIfDead()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | LiveIntervals.h | 103 static float getSpillWeight(bool isDef, bool isUse,
108 static float getSpillWeight(bool isDef, bool isUse,
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| H A D | MachineRegisterInfo.h | 1015 if ((!ReturnUses && op->isUse()) || in defusechain_iterator()
1029 if (Op->isUse()) in advance()
1123 if ((!ReturnUses && op->isUse()) || in defusechain_instr_iterator()
1137 if (Op->isUse()) in advance()
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| H A D | LiveRegUnits.h | 66 assert(O->isUse() && "Reg operand not a def and not a use"); in accumulateUsedDefed()
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| /llvm-project-15.0.7/llvm/lib/Target/BPF/ |
| H A D | BPFMIChecking.cpp | 116 if (!MO.isReg() || MO.isUse()) in hasLiveDefs()
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