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Searched refs:isSubRegisterEq (Results 1 – 12 of 12) sorted by relevance

/llvm-project-15.0.7/llvm/lib/MC/
H A DMCInstrDesc.cpp45 RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg())) in hasDefOfPhysReg()
50 RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg())) in hasDefOfPhysReg()
/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCRegisterInfo.h568 bool isSubRegisterEq(MCRegister RegA, MCRegister RegB) const { in isSubRegisterEq() function
581 return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB); in isSuperOrSubRegisterEq()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86FixupBWInsts.cpp275 if (MO.isUse() && !TRI->isSubRegisterEq(OrigDestReg, MO.getReg()) && in getSuperRegDestIfDead()
H A DX86InstrInfo.cpp3785 return TRI->isSubRegisterEq(NullValueReg, MO.getReg()); in preservesZeroValueInReg()
9138 if (!TRI->isSubRegisterEq(MI.getOperand(0).getReg(), Reg)) in describeLoadedValue()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIFrameLowering.cpp228 !TRI->isSubRegisterEq(Reg, GITPtrLoReg)) { in emitEntryFunctionFlatScratchInit()
389 !TRI->isSubRegisterEq(Reg, GITPtrLoReg)) { in getEntryFunctionReservedScratchRsrcReg()
476 TRI->isSubRegisterEq(ScratchRsrcReg, PreloadedScratchWaveOffsetReg)) { in emitEntryFunctionPrologue()
484 !TRI->isSubRegisterEq(ScratchRsrcReg, Reg) && GITPtrLoReg != Reg) { in emitEntryFunctionPrologue()
H A DGCNNSAReassign.cpp134 if (TRI->isSubRegisterEq(Reg, CSRegs[I]) && in canAssign()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMachineCopyPropagation.cpp243 if (!TRI.isSubRegisterEq(AvailSrc, Reg)) in findAvailBackwardCopy()
273 if (!TRI.isSubRegisterEq(AvailDef, Reg)) in findAvailCopy()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp4742 if (RI->isSubRegisterEq(Rn, Rt)) in validateInstruction()
4745 if (RI->isSubRegisterEq(Rn, Rt2)) in validateInstruction()
4788 if (RI->isSubRegisterEq(Rn, Rt)) in validateInstruction()
4791 if (RI->isSubRegisterEq(Rn, Rt2)) in validateInstruction()
4820 if (RI->isSubRegisterEq(Rn, Rt)) in validateInstruction()
4839 if (RI->isSubRegisterEq(Rn, Rt)) in validateInstruction()
4855 if (RI->isSubRegisterEq(Rt, Rs) || in validateInstruction()
4856 (RI->isSubRegisterEq(Rn, Rs) && Rn != AArch64::SP)) in validateInstruction()
4869 if (RI->isSubRegisterEq(Rt1, Rs) || RI->isSubRegisterEq(Rt2, Rs) || in validateInstruction()
4870 (RI->isSubRegisterEq(Rn, Rs) && Rn != AArch64::SP)) in validateInstruction()
/llvm-project-15.0.7/bolt/lib/Core/
H A DMCPlusBuilder.cpp443 RegInfo->isSubRegisterEq(Reg, MI.getOperand(I).getReg())) in hasUseOfPhysReg()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp585 IsSameOrSubReg = getRegisterInfo()->isSubRegisterEq(DepR, MOReg); in restoreLatency()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.cpp209 if (!FoundDef && TRI->isSubRegisterEq(MO.getReg(), SrcReg)) { in isConvertibleToVMV_V_V()
/llvm-project-15.0.7/bolt/lib/Target/X86/
H A DX86MCPlusBuilder.cpp1897 RegInfo->isSubRegisterEq(X86::RBP, StackPtrReg)) in convertMoveToConditionalMove()