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Searched refs:isSubRegister (Results 1 – 16 of 16) sorted by relevance

/llvm-project-15.0.7/llvm/lib/MC/
H A DMCInstrDesc.cpp36 if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs))) in hasImplicitDefOfPhysReg()
/llvm-project-15.0.7/llvm/lib/CodeGen/AsmPrinter/
H A DDwarfExpression.h125 bool isSubRegister() const { return SubRegSize; } in isSubRegister() function
H A DDwarfExpression.cpp345 assert(!Reg.isSubRegister() && "full register expected"); in addMachineRegExpression()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCChecker.cpp631 unsigned BadR = RI.isSubRegister(Hexagon::USR, R) ? UsrR : R; in checkRegisters()
644 unsigned BadR = RI.isSubRegister(Hexagon::USR, R) ? UsrR : R; in checkRegisters()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DAggressiveAntiDepBreaker.cpp587 bool IsSub = TRI->isSubRegister(SuperReg, Reg); in FindSuitableFreeRegisters()
915 if (R == AntiDepReg || TRI->isSubRegister(AntiDepReg, R)) in BreakAntiDependencies()
H A DMachineInstr.cpp1011 Found = TRI->isSubRegister(MOReg, Reg); in findRegisterDefOperandIdx()
1860 if (RegInfo->isSubRegister(IncomingReg, Reg)) in addRegisterKilled()
1925 if (RegInfo->isSubRegister(Reg, MOReg)) in addRegisterDead()
H A DLiveVariables.cpp216 if (TRI->isSubRegister(Reg, DefReg)) { in FindLastPartialDef()
H A DMachineCopyPropagation.cpp392 if (!TRI->isSubRegister(PreviousSrc, Src)) in isNopCopy()
/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCRegisterInfo.h560 bool isSubRegister(MCRegister RegA, MCRegister RegB) const { in isSubRegister() function
/llvm-project-15.0.7/bolt/lib/Core/
H A DMCPlusBuilder.cpp447 if (*ImpUses == Reg || RegInfo->isSubRegister(Reg, *ImpUses)) in hasUseOfPhysReg()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsInstrInfo.cpp957 if (TRI->isSuperRegister(Reg, DestReg) || TRI->isSubRegister(Reg, DestReg)) in describeLoadedValue()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.cpp634 assert(!isSubRegister(ScratchRSrcReg, StackPtrReg)); in getReservedRegs()
640 assert(!isSubRegister(ScratchRSrcReg, FrameReg)); in getReservedRegs()
646 assert(!isSubRegister(ScratchRSrcReg, BasePtrReg)); in getReservedRegs()
H A DSIInstrInfo.cpp3977 return TRI.isSubRegister(SuperVec.getReg(), SubReg.getReg()); in isSubRegOf()
H A DSIISelLowering.cpp12388 assert(!TRI->isSubRegister(Info->getScratchRSrcReg(), in finalizeLowering()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64LoadStoreOptimizer.cpp1930 if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg)) in findMatchingUpdateInsnForward()
2001 if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg)) in findMatchingUpdateInsnBackward()
H A DAArch64InstrInfo.cpp8068 TRI->isSubRegister(DestReg, DescribedReg)) { in describeORRLoadedValue()