| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCHazardRecognizers.cpp | 281 bool &isLoad, bool &isStore) { in GetInstrType() argument
285 isStore = MCID.mayStore(); in GetInstrType()
334 bool isFirst, isSingle, isCracked, isLoad, isStore; in getHazardType() local
337 isLoad, isStore); in getHazardType()
392 bool isFirst, isSingle, isCracked, isLoad, isStore; in EmitInstruction() local
395 isLoad, isStore); in EmitInstruction()
402 if (isStore && NumStores < 4 && !MI->memoperands_empty()) { in EmitInstruction()
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| H A D | PPCHazardRecognizers.h | 92 bool &isLoad, bool &isStore);
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| /llvm-project-15.0.7/polly/include/polly/Support/ |
| H A D | ScopHelper.h | 236 if (isStore()) in getValueOperand()
247 if (isStore()) in getPointerOperand()
258 if (isStore()) in isVolatile()
269 if (isStore()) in isSimple()
280 if (isStore()) in getOrdering()
291 if (isStore()) in isUnordered()
308 bool isStore() const { return I && llvm::isa<llvm::StoreInst>(I); } in isStore() function
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsInstructionSelector.cpp | 189 const bool isStore = Opc == TargetOpcode::G_STORE; in selectLoadStoreOpCode() local
196 if (isStore) in selectLoadStoreOpCode()
228 return isStore ? Mips::SWC1 : Mips::LWC1; in selectLoadStoreOpCode()
231 return isStore ? Mips::SDC164 : Mips::LDC164; in selectLoadStoreOpCode()
232 return isStore ? Mips::SDC1 : Mips::LDC1; in selectLoadStoreOpCode()
241 return isStore ? Mips::ST_B : Mips::LD_B; in selectLoadStoreOpCode()
243 return isStore ? Mips::ST_H : Mips::LD_H; in selectLoadStoreOpCode()
245 return isStore ? Mips::ST_W : Mips::LD_W; in selectLoadStoreOpCode()
247 return isStore ? Mips::ST_D : Mips::LD_D; in selectLoadStoreOpCode()
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| /llvm-project-15.0.7/llvm/lib/Target/M68k/ |
| H A D | M68kCollapseMOVEMPass.cpp | 145 bool isStore() const { return Access == AccessTy::Store; } in isStore() function in __anond2face1f0111::MOVEMState
209 if (State.isStore() == IsStore && State.getBase() == Reg && in ProcessMI()
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| /llvm-project-15.0.7/mlir/include/mlir/Dialect/Affine/Analysis/ |
| H A D | AffineAnalysis.h | 93 bool isStore() const;
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | MachineOperand.cpp | 1038 assert((isLoad() || isStore()) && "Not a load/store!"); in MachineMemOperand()
1115 assert((isLoad() || isStore()) && in print()
1119 if (isStore()) in print()
1135 OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into "); in print()
1138 OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into "); in print()
1182 OS << ((isLoad() && isStore()) ? " on " in print()
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| H A D | MachineVerifier.cpp | 1538 if ((!MMOs[0]->isStore() || MMOs[0]->isLoad()) || in verifyPreISelGenericInstruction()
1539 (MMOs[1]->isStore() || !MMOs[1]->isLoad())) { in verifyPreISelGenericInstruction()
1575 if ((!MMOs[0]->isStore() || MMOs[0]->isLoad())) { in verifyPreISelGenericInstruction()
1748 if (Op->isStore() && !MI->mayStore()) in visitMachineInstrBefore()
2197 if (MMO->isStore()) in visitMachineOperand()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 358 bool isStore = Opc == TargetOpcode::G_STORE; in selectLoadStoreOpCode() local
364 return isStore ? Opcodes.STORE8 : Opcodes.LOAD8; in selectLoadStoreOpCode()
366 return isStore ? Opcodes.STORE16 : Opcodes.LOAD16; in selectLoadStoreOpCode()
368 return isStore ? Opcodes.STORE32 : Opcodes.LOAD32; in selectLoadStoreOpCode()
377 return isStore ? ARM::VSTRS : ARM::VLDRS; in selectLoadStoreOpCode()
379 return isStore ? ARM::VSTRD : ARM::VLDRD; in selectLoadStoreOpCode()
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| /llvm-project-15.0.7/llvm/lib/Target/ARC/ |
| H A D | ARCInstrInfo.cpp | 58 static bool isStore(int Opcode) { in isStore() function
90 if (isStore(Opcode)) { in isStoreToStackSlot()
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| /llvm-project-15.0.7/bolt/lib/Passes/ |
| H A D | StokeInfo.cpp | 78 if (MIB->isStore(It) && !IsPush && !IsRipAddr) in checkInstr()
|
| /llvm-project-15.0.7/llvm/lib/Transforms/Scalar/ |
| H A D | EarlyCSE.cpp | 717 bool isStore() const { in isStore() function in __anon5cb5eb3b0311::EarlyCSE::ParseMemoryInst
1140 Value *Result = MemInst.isStore() in getMatchingValue()
1143 if (MemInst.isStore() && InVal.DefInst != Result) in getMatchingValue()
1519 if (MemInst.isValid() && MemInst.isStore()) { in processNode()
1554 if (MemInst.isValid() && MemInst.isStore()) { in processNode()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LoadStoreOpt.cpp | 245 if ((MUC0.MMO->isInvariant() && MUC1.MMO->isStore()) || in instMayAlias()
246 (MUC1.MMO->isInvariant() && MUC0.MMO->isStore())) in instMayAlias()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | MachineMemOperand.h | 288 bool isStore() const { return FlagVals & MOStore; } in isStore() function
|
| /llvm-project-15.0.7/clang/include/clang/Basic/ |
| H A D | TargetBuiltins.h | 262 bool isStore() const { return Flags & IsStore; } in isStore() function
|
| /llvm-project-15.0.7/bolt/lib/Core/ |
| H A D | DynoStats.cpp | 220 if (BC.MIB->isStore(Instr)) { in getDynoStats()
|
| /llvm-project-15.0.7/llvm/lib/Transforms/Vectorize/ |
| H A D | VPlanRecipes.cpp | 45 return cast<VPWidenMemoryInstructionRecipe>(this)->isStore(); in mayWriteToMemory()
76 return !cast<VPWidenMemoryInstructionRecipe>(this)->isStore(); in mayReadFromMemory()
954 if (!isStore()) { in print()
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| H A D | VPlan.h | 1724 return isStore() ? getNumOperands() == 3 : getNumOperands() == 2; in isMasked()
1764 bool isStore() const { return isa<StoreInst>(Ingredient); } in isStore() function
1768 assert(isStore() && "Stored value only available for store instructions"); in getStoredValue()
1797 (!isStore() || Op != getStoredValue()); in onlyFirstLaneUsed()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMInstPrinter.cpp | 264 bool isStore = Opcode == ARM::STREXD || Opcode == ARM::STLEXD; in printInst() local
265 unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg(); in printInst()
271 if (isStore) in printInst()
278 for (unsigned i = isStore ? 3 : 2; i < MI->getNumOperands(); ++i) in printInst()
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| /llvm-project-15.0.7/llvm/utils/TableGen/ |
| H A D | CodeGenDAGPatterns.cpp | 935 return isLoad() || isStore() || isAtomic() || hasNoUse() || in hasPredCode()
942 if (!isLoad() && !isStore() && !isAtomic()) { in getPredCode()
950 if (!isLoad() && !isStore()) { in getPredCode()
962 if (isLoad() + isStore() + isAtomic() > 1) in getPredCode()
991 if (isStore()) { in getPredCode()
1046 if (isLoad() || isStore() || isAtomic()) { in getPredCode()
1116 if (isLoad() || isStore()) { in getPredCode()
1217 bool TreePredicateFn::isStore() const { in isStore() function in TreePredicateFn
1347 if (isStore()) in getCodeToRunOnSDNode()
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| H A D | GlobalISelEmitter.cpp | 347 if (Predicate.isLoad() || Predicate.isStore()) { in isTrivialOperatorNode()
352 if (Predicate.isLoad() || Predicate.isStore() || Predicate.isAtomic()) { in isTrivialOperatorNode()
3834 if (Predicate.isLoad() || Predicate.isStore() || Predicate.isAtomic()) { in addBuiltinPredicates()
3871 if (Predicate.isStore()) { in addBuiltinPredicates()
3909 if (Predicate.isLoad() || Predicate.isStore() || Predicate.isAtomic()) { in addBuiltinPredicates()
3921 if (Predicate.isLoad() || Predicate.isStore()) { in addBuiltinPredicates()
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| /llvm-project-15.0.7/mlir/lib/Dialect/Affine/Analysis/ |
| H A D | Utils.cpp | 455 write = access.isStore(); in compute()
1235 bool MemRefAccess::isStore() const { in isStore() function in MemRefAccess
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| /llvm-project-15.0.7/llvm/lib/Transforms/Instrumentation/ |
| H A D | MemorySanitizer.cpp | 612 FunctionCallee getKmsanShadowOriginAccessFn(bool isStore, int size);
872 FunctionCallee MemorySanitizer::getKmsanShadowOriginAccessFn(bool isStore, in getKmsanShadowOriginAccessFn() argument
875 isStore ? MsanMetadataPtrForStore_1_8 : MsanMetadataPtrForLoad_1_8; in getKmsanShadowOriginAccessFn()
1503 bool isStore) { in getShadowOriginPtrKernel()
1508 FunctionCallee Getter = MS.getKmsanShadowOriginAccessFn(isStore, Size); in getShadowOriginPtrKernel()
1515 ShadowOriginPtrs = IRB.CreateCall(isStore ? MS.MsanMetadataPtrForStoreN in getShadowOriginPtrKernel()
1529 bool isStore) { in getShadowOriginPtr()
1531 return getShadowOriginPtrKernel(Addr, IRB, ShadowTy, isStore); in getShadowOriginPtr()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 823 const bool isStore = GenericOpc == TargetOpcode::G_STORE; in selectLoadStoreUIOp() local
828 return isStore ? AArch64::STRBBui : AArch64::LDRBBui; in selectLoadStoreUIOp()
830 return isStore ? AArch64::STRHHui : AArch64::LDRHHui; in selectLoadStoreUIOp()
832 return isStore ? AArch64::STRWui : AArch64::LDRWui; in selectLoadStoreUIOp()
834 return isStore ? AArch64::STRXui : AArch64::LDRXui; in selectLoadStoreUIOp()
840 return isStore ? AArch64::STRBui : AArch64::LDRBui; in selectLoadStoreUIOp()
842 return isStore ? AArch64::STRHui : AArch64::LDRHui; in selectLoadStoreUIOp()
844 return isStore ? AArch64::STRSui : AArch64::LDRSui; in selectLoadStoreUIOp()
846 return isStore ? AArch64::STRDui : AArch64::LDRDui; in selectLoadStoreUIOp()
848 return isStore ? AArch64::STRQui : AArch64::LDRQui; in selectLoadStoreUIOp()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIInsertWaitcnts.cpp | 1129 if (Memop->isStore() && SLoadAddresses.count(Ptr)) { in generateWaitcntInstBefore()
1144 if (Memop->isStore()) { in generateWaitcntInstBefore()
|