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Searched refs:isSignedIntSetCC (Results 1 – 10 of 10) sorted by relevance

/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1457 inline bool isSignedIntSetCC(CondCode Code) { in isSignedIntSetCC() function
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp4676 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteNode()
4710 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteNode()
4738 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteNode()
H A DTargetLowering.cpp4305 !ISD::isSignedIntSetCC(Cond) && in SimplifySetCC()
4562 if (ISD::isSignedIntSetCC(Cond)) { in SimplifySetCC()
H A DLegalizeIntegerTypes.cpp1771 if (ISD::isSignedIntSetCC(CCCode)) { in PromoteSetCCOperands()
H A DDAGCombiner.cpp10919 bool IsSigned = isSignedIntSetCC(CC); in visitVSELECT()
11421 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) in ExtendUsesToFormExtLoad()
11892 bool IsSignedCmp = ISD::isSignedIntSetCC(CC); in foldSextSetcc()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp5765 if (ISD::isSignedIntSetCC(CC)) in Select()
H A DPPCISelLowering.cpp13442 if (ISD::isSignedIntSetCC(CC)) { in DAGCombineTruncBoolExt()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp16777 isSignedIntSetCC(Code) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in performSignExtendSetCCCombine()
18340 if (Op0SExt && (isSignedIntSetCC(CC) || isIntEqualitySetCC(CC))) { in tryToWidenSetCCOperands()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp4759 !isSignedIntSetCC(CC)) { in getARMCmp()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp52153 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) { in combineSetCC()