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Searched refs:isSignExtLoad (Results 1 – 4 of 4) sorted by relevance

/llvm-project-15.0.7/llvm/utils/TableGen/
H A DCodeGenDAGPatterns.cpp968 !isSignExtLoad() && !isZeroExtLoad() && getMemoryVT() == nullptr && in getPredCode()
982 if (isSignExtLoad()) in getPredCode()
1010 !isZeroExtLoad() && !isSignExtLoad() && !isAtomicOrderingAcquire() && in getPredCode()
1113 if (isAtomic() && (isZeroExtLoad() || isSignExtLoad())) in getPredCode()
1126 if ((isNonExtLoad() + isAnyExtLoad() + isSignExtLoad() + in getPredCode()
1137 if (isSignExtLoad()) in getPredCode()
1232 bool TreePredicateFn::isSignExtLoad() const { in isSignExtLoad() function in TreePredicateFn
1362 if (isSignExtLoad()) in getCodeToRunOnSDNode()
H A DCodeGenDAGPatterns.h562 bool isSignExtLoad() const;
H A DGlobalISelEmitter.cpp237 if (P.isSignExtLoad()) in explainPredicates()
338 Predicate.isSignExtLoad() || Predicate.isZeroExtLoad()) in isTrivialOperatorNode()
3790 Predicate.isSignExtLoad()) in getEquivNode()
3897 Predicate.isSignExtLoad()) in addBuiltinPredicates()
/llvm-project-15.0.7/llvm/include/llvm/Target/GlobalISel/
H A DSelectionDAGCompat.td162 // as isSignExtLoad require that this is not a perfect 1:1 mapping since a