| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | VOP3Instructions.td | 122 let isReMaterializable = 1 in { 156 } // End isReMaterializable = 1 177 let isReMaterializable = 1 in { 220 } // End isReMaterializable = 1 232 let isReMaterializable = 1 in 240 let isReMaterializable = 1 in { 258 } // End isReMaterializable = 1 265 let isReMaterializable = 1 in { 275 } // End isReMaterializable = 1 542 let isReMaterializable = 1 in { [all …]
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| H A D | VOP1Instructions.td | 196 let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 234 let isReMaterializable = 1 in { 266 let FPDPRounding = 1, isReMaterializable = 0 in { 268 } // End FPDPRounding = 1, isReMaterializable = 0 328 } // End isReMaterializable = 1 389 let isReMaterializable = 1 in { 427 } // End isReMaterializable = 1 489 let isReMaterializable = 1 in 578 let isReMaterializable = 1;
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| H A D | SOPInstructions.td | 201 } // End isReMaterializable = 1 236 let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 256 let isReMaterializable = 1 in { 284 } // End isReMaterializable = 1 362 let isReMaterializable = 1 in 634 let isReMaterializable = 1 in { 643 } // End isReMaterializable = 1 678 let isReMaterializable = 1 in { 682 } // End isReMaterializable = 1 822 let isReMaterializable = 1, isMoveImm = 1 in { [all …]
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| H A D | VOP2Instructions.td | 280 let isReMaterializable = 1; 599 let isReMaterializable = 1 in { 621 } // End isReMaterializable = 1 634 let isReMaterializable = 1 in 668 let isReMaterializable = 1 in { 697 } // End isReMaterializable = 1 757 let isReMaterializable = 1 in { 794 } // End isReMaterializable = 1 805 let isReMaterializable = 1 in 916 let FPDPRounding = 1, isReMaterializable = 1 in { [all …]
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| H A D | VOP3PInstructions.td | 91 let isReMaterializable = 1 in { 120 } // End isReMaterializable = 1 213 let isReMaterializable = 1 in 234 let isReMaterializable = 1 in 553 let isAsCheapAsAMove = 1, isReMaterializable = 1 in { 558 } // End isAsCheapAsAMove = 1, isReMaterializable = 1 692 let SubtargetPredicate = HasPackedFP32Ops, isCommutable = 1, isReMaterializable = 1 in {
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| H A D | SIInstructions.td | 120 let isReMaterializable = 1; 136 let isReMaterializable = 1; 383 let isReMaterializable = 1; 393 let isReMaterializable = 1; 478 let isReMaterializable = 1;
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPseudo.td | 40 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0, 64 let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in { 71 let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1, 76 let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1, 278 let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1, 484 let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1,
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| /llvm-project-15.0.7/llvm/lib/Target/XCore/ |
| H A D | XCoreInstrInfo.td | 334 let isReMaterializable = 1 in 534 let hasSideEffects = 0, isReMaterializable = 1 in 538 let isReMaterializable = 1 in 560 let mayLoad = 1, isReMaterializable = 1, hasSideEffects = 0 in { 598 let isReMaterializable = 1 in { 652 let Defs = [R11], hasSideEffects = 0, isReMaterializable = 1 in 656 let Defs = [R11], isReMaterializable = 1 in 685 let Defs = [R11], isReMaterializable = 1 in { 724 let Defs = [R11], mayLoad = 1, isReMaterializable = 1, 768 let isReMaterializable = 1, hasSideEffects = 0 in
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| /llvm-project-15.0.7/llvm/utils/TableGen/ |
| H A D | InstrDocsEmitter.cpp | 122 FLAG(isReMaterializable) in EmitInstrDocs()
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| H A D | CodeGenInstruction.h | 261 bool isReMaterializable : 1; variable
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| H A D | CodeGenInstruction.cpp | 389 isReMaterializable = R->getValueAsBit("isReMaterializable"); in CodeGenInstruction()
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| H A D | InstrInfoEmitter.cpp | 1151 if (Inst.isReMaterializable) OS << "|(1ULL<<MCID::Rematerializable)"; in emitRecord()
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| /llvm-project-15.0.7/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.td | 407 isReMaterializable = 1 in 423 let isReMaterializable = 1; 507 let isReMaterializable = 1; 551 let isReMaterializable = 1; 567 let isReMaterializable = 1; 589 let isReMaterializable = 1;
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| /llvm-project-15.0.7/llvm/lib/Target/VE/ |
| H A D | VEInstrInfo.td | 981 let isReMaterializable = 1, isAsCheapAsAMove = 1, 1198 } // isReMaterializable, isAsCheapAsAMove 1249 } // isReMaterializable, isAsCheapAsAMove 1269 } // isReMaterializable, isAsCheapAsAMove 1274 let isReMaterializable = 1, isAsCheapAsAMove = 1 in 1284 let isReMaterializable = 1, isAsCheapAsAMove = 1 in 1291 let isReMaterializable = 1, isAsCheapAsAMove = 1 in 1295 let isReMaterializable = 1, isAsCheapAsAMove = 1 in 1324 let isReMaterializable = 1, isAsCheapAsAMove = 1 in 1331 let isReMaterializable = 1, isAsCheapAsAMove = 1 in [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyInstrInfo.td | 365 let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1 in { 382 } // isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86InstrAMX.td | 66 let isPseudo = true, isReMaterializable = 1, isAsCheapAsAMove = 1,
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| /llvm-project-15.0.7/llvm/lib/Target/CSKY/ |
| H A D | CSKYInstrInfo16Instr.td | 93 let Constraints = "$rZ = $rz", isReMaterializable = 1, isAsCheapAsAMove = 1 in { 108 let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 169 let isReMaterializable = 1;
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| /llvm-project-15.0.7/llvm/lib/Target/AVR/ |
| H A D | AVRInstrInfo.td | 1256 let isReMaterializable = 1 in { 1281 let canFoldAsLoad = 1, isReMaterializable = 1 in { 1308 let canFoldAsLoad = 1, isReMaterializable = 1 in { 1383 let canFoldAsLoad = 1, isReMaterializable = 1 in { 1650 let canFoldAsLoad = 1, isReMaterializable = 1, mayLoad = 1, 1742 let canFoldAsLoad = 1, isReMaterializable = 1 in {
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| /llvm-project-15.0.7/llvm/lib/Target/ARC/ |
| H A D | ARCInstrInfo.td | 310 let Uses=[STATUS32], isAsCheapAsAMove=0, isReMaterializable=0 in { 367 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 396 isReMaterializable = 0, Constraints = "$B = $B2" in {
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMInstrThumb.td | 691 let canFoldAsLoad = 1, isReMaterializable = 1, AddedComplexity = 10 in 717 let canFoldAsLoad = 1, isReMaterializable = 1 in 1491 let hasSideEffects = 0, isReMaterializable = 1 in 1730 let isReMaterializable = 1 in
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| H A D | ARMInstrInfo.td | 1528 let isReMaterializable = 1 in { 1601 let isReMaterializable = 1 in { 1995 let canFoldAsLoad = 1, isReMaterializable = 1 in { 2025 let canFoldAsLoad = 1, isReMaterializable = 1 in { 2408 let hasSideEffects = 0, isReMaterializable = 1 in 2811 isReMaterializable = 1, isCodeGenOnly = 1 in 3628 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3640 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 5969 let isReMaterializable = 1, isMoveImm = 1, Size = 8 in 5982 let isReMaterializable = 1 in { [all …]
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| H A D | ARMInstrThumb2.td | 926 let isReMaterializable = 1 in { 1246 let isReMaterializable = 1; 1424 let hasSideEffects = 0, isReMaterializable = 1 in 1439 let canFoldAsLoad = 1, isReMaterializable = 1 in 2147 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1, 2171 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 2891 let isReMaterializable = ReMat; 4234 let isReMaterializable = 1, isMoveImm = 1, Size = 8 in 4243 let isReMaterializable = 1 in { 4283 let canFoldAsLoad = 1, isReMaterializable = 1 in
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MicroMipsInstrInfo.td | 242 let isReMaterializable = 1; 414 let isReMaterializable = 1; 421 let isReMaterializable = 1;
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.td | 589 let isReMaterializable = 1, isAsCheapAsAMove = 1 in 624 // ADDI isn't always rematerializable, but isReMaterializable will be used as 626 let isReMaterializable = 1, isAsCheapAsAMove = 1 in 632 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
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| /llvm-project-15.0.7/llvm/docs/TableGen/ |
| H A D | index.rst | 126 bit isReMaterializable = 0;
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