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Searched refs:isPow2VectorType (Results 1 – 12 of 12) sorted by relevance

/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DValueTypes.h437 bool isPow2VectorType() const { in isPow2VectorType() function
445 if (!isPow2VectorType()) { in getPow2VectorType()
H A DTargetLowering.h465 if (!VT.isPow2VectorType()) in getPreferredVectorAction()
/llvm-project-15.0.7/llvm/include/llvm/Support/
H A DMachineValueType.h506 bool isPow2VectorType() const { in isPow2VectorType() function
514 if (isPow2VectorType()) in getPow2VectorType()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1004 if (!VT.isPow2VectorType()) { in getTypeConversion()
1074 if (!VT.isPow2VectorType()) { in getTypeConversion()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp1589 return VT.isPow2VectorType() ? TypeSplitVector : TypeWidenVector; in getPreferredVectorAction()
8681 if (MemVT.isPow2VectorType()) in LowerLOAD()
8697 if (MemVT.isPow2VectorType()) in LowerLOAD()
H A DAMDGPUISelLowering.cpp1018 if (MemVT.isVector() && !MemVT.isPow2VectorType()) { in analyzeFormalArgumentsCompute()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp6202 assert(VT.isVector() && !VT.isPow2VectorType() && isTypeLegal(VT)); in WidenVecOp_VSELECT()
H A DTargetLowering.cpp9447 if (VT.isPow2VectorType()) { in expandVecReduce()
H A DDAGCombiner.cpp11519 !DstVT.isVector() || !DstVT.isPow2VectorType() || in CombineExtLoad()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp1657 if (!VT.isPow2VectorType()) in useRVVForFixedLengthVectorVT()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp5672 if (!VT.isPow2VectorType()) in useSVEForFixedLengthVectorVT()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp13141 if (!VecVT.isPow2VectorType() || VecVT.getVectorNumElements() == 1) in PerformVQDMULHCombine()