| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | Register.h | 65 static bool isPhysicalRegister(unsigned Reg) { in isPhysicalRegister() function 66 return MCRegister::isPhysicalRegister(Reg); in isPhysicalRegister() 98 return isPhysicalRegister(Reg); in isPhysical() 122 MCRegister::isPhysicalRegister(Reg)); in asMCReg()
|
| H A D | LiveRegUnits.h | 170 Register::isPhysicalRegister(MOP.getReg())); in phys_regs_and_masks()
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | Thumb1InstrInfo.cpp | 84 (Register::isPhysicalRegister(SrcReg) && isARMLowRegister(SrcReg))) && in storeRegToStackSlot() 88 (Register::isPhysicalRegister(SrcReg) && isARMLowRegister(SrcReg))) { in storeRegToStackSlot() 113 (Register::isPhysicalRegister(DestReg) && isARMLowRegister(DestReg))) && in loadRegFromStackSlot() 117 (Register::isPhysicalRegister(DestReg) && isARMLowRegister(DestReg))) { in loadRegFromStackSlot()
|
| H A D | MLxExpansionPass.cpp | 90 if (Register::isPhysicalRegister(Reg)) in getAccDefMI() 118 if (Register::isPhysicalRegister(Reg) || !MRI->hasOneNonDBGUse(Reg)) in getDefReg() 128 if (Register::isPhysicalRegister(Reg) || !MRI->hasOneNonDBGUse(Reg)) in getDefReg() 142 if (Register::isPhysicalRegister(Reg)) in hasLoopHazard()
|
| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | DeadMachineInstructionElim.cpp | 81 if (Register::isPhysicalRegister(Reg)) { in isDead() 156 if (Register::isPhysicalRegister(Reg)) { in eliminateDeadMI() 174 if (Register::isPhysicalRegister(Reg)) { in eliminateDeadMI()
|
| H A D | CodeGenCommonISel.cpp | 103 if (!OPI2->isReg() || (!Register::isPhysicalRegister(OPI->getReg()) && in MIIsInTerminatorSequence() 104 Register::isPhysicalRegister(OPI2->getReg()))) in MIIsInTerminatorSequence()
|
| H A D | RDFRegisters.cpp | 109 assert(isRegMaskId(Reg) || Register::isPhysicalRegister(Reg)); in getAliasSet() 137 assert(Register::isPhysicalRegister(RA.Reg)); in aliasRR() 138 assert(Register::isPhysicalRegister(RB.Reg)); in aliasRR() 168 assert(Register::isPhysicalRegister(RR.Reg) && isRegMaskId(RM.Reg)); in aliasRM()
|
| H A D | ExpandPostRAPseudos.cpp | 96 assert(Register::isPhysicalRegister(DstReg) && in LowerSubregToReg() 98 assert(Register::isPhysicalRegister(InsReg) && in LowerSubregToReg()
|
| H A D | MachineInstrBundle.cpp | 201 if (!MO.isDead() && Register::isPhysicalRegister(Reg)) { in finalizeBundle() 331 if (!MOReg || !Register::isPhysicalRegister(MOReg)) in AnalyzePhysRegInBundle()
|
| H A D | MachineCycleAnalysis.cpp | 108 if (Register::isPhysicalRegister(Reg)) { in isCycleInvariant()
|
| H A D | TargetRegisterInfo.cpp | 213 assert(Register::isPhysicalRegister(reg) && in getMinimalPhysRegClass() 231 assert(Register::isPhysicalRegister(reg) && in getMinimalPhysRegClassLLT() 472 assert(Register::isPhysicalRegister(PhysReg) && in isCalleeSavedPhysReg()
|
| H A D | MachineInstr.cpp | 996 bool isPhys = Register::isPhysicalRegister(Reg); in findRegisterDefOperandIdx() 1007 if (!Found && TRI && isPhys && Register::isPhysicalRegister(MOReg)) { in findRegisterDefOperandIdx() 1165 if (Register::isPhysicalRegister(ToReg)) { in substituteRegister() 1825 bool isPhysReg = Register::isPhysicalRegister(IncomingReg); in addRegisterKilled() 1856 } else if (hasAliases && MO.isKill() && Register::isPhysicalRegister(Reg)) { in addRegisterKilled() 1890 if (!Register::isPhysicalRegister(Reg)) in clearRegisterKills() 1904 bool isPhysReg = Register::isPhysicalRegister(Reg); in addRegisterDead() 1921 Register::isPhysicalRegister(MOReg)) { in addRegisterDead() 1972 if (Register::isPhysicalRegister(Reg)) { in addRegisterDefined()
|
| H A D | RegisterCoalescer.cpp | 470 if (Register::isPhysicalRegister(Src)) { in setRegisters() 471 if (Register::isPhysicalRegister(Dst)) in setRegisters() 480 if (Register::isPhysicalRegister(Dst)) { in setRegisters() 547 if (Register::isPhysicalRegister(DstReg)) in flip() 953 if (Register::isPhysicalRegister(NewReg)) in removeCopyByCommutingDef() 1290 if (Register::isPhysicalRegister(SrcReg)) in reMaterializeTrivialDef() 1523 assert(Register::isPhysicalRegister(DstReg) && in reMaterializeTrivialDef() 1576 if (Register::isPhysicalRegister(DstReg)) in reMaterializeTrivialDef() 3888 if (Register::isPhysicalRegister(SrcReg) || in isLocalCopy() 3889 Register::isPhysicalRegister(DstReg)) in isLocalCopy() [all …]
|
| H A D | MachineSink.cpp | 614 if (Register::isPhysicalRegister(Reg)) in isWorthBreakingCriticalEdge() 808 if (Register::isPhysicalRegister(Reg)) { in isProfitableToSinkTo() 913 if (Register::isPhysicalRegister(Reg)) { in FindSuccToSinkTo() 1326 if (Register::isPhysicalRegister(Reg) && in blockPrologueInterferes() 1390 if (Reg == 0 || !Register::isPhysicalRegister(Reg)) in SinkInstruction() 1786 if (MO.isReg() && Register::isPhysicalRegister(MO.getReg())) { in tryToSinkCopy()
|
| H A D | PeepholeOptimizer.cpp | 699 if (Register::isPhysicalRegister(CurSrcPair.Reg)) in findNextSource() 747 if (Register::isPhysicalRegister(CurSrcPair.Reg)) in findNextSource() 1194 if (Register::isPhysicalRegister(MODef.getReg())) in optimizeCoalescableCopy() 1245 assert(!Register::isPhysicalRegister(Def.Reg) && in rewriteSource() 1304 if (Register::isPhysicalRegister(Def.Reg)) in optimizeUncoalescableCopy() 2113 if (!Register::isPhysicalRegister(Reg) && OneRegSrc) { in getNextSource()
|
| H A D | TargetInstrInfo.cpp | 196 bool Reg1IsRenamable = Register::isPhysicalRegister(Reg1) in commuteInstructionImpl() 199 bool Reg2IsRenamable = Register::isPhysicalRegister(Reg2) in commuteInstructionImpl() 241 if (Register::isPhysicalRegister(Reg1)) in commuteInstructionImpl() 243 if (Register::isPhysicalRegister(Reg2)) in commuteInstructionImpl() 463 if (Register::isPhysicalRegister(LiveOp.getReg())) in canFoldCopy() 967 if (Register::isPhysicalRegister(Reg)) { in isReallyTriviallyReMaterializableGeneric()
|
| H A D | ProcessImplicitDefs.cpp | 111 if (!Register::isPhysicalRegister(UserReg) || in processImplicitDef()
|
| H A D | RegisterBankInfo.cpp | 82 if (Register::isPhysicalRegister(Reg)) { in getRegBank() 100 assert(Register::isPhysicalRegister(Reg) && "Reg must be a physreg"); in getMinimalPhysRegClass() 493 if (Register::isPhysicalRegister(Reg)) { in getSizeInBits()
|
| H A D | MachineLoopInfo.cpp | 171 if (Register::isPhysicalRegister(Reg)) { in isLoopInvariant()
|
| /llvm-project-15.0.7/llvm/include/llvm/MC/ |
| H A D | MCRegister.h | 58 static bool isPhysicalRegister(unsigned Reg) { in isPhysicalRegister() function 68 assert(Val == NoRegister || isPhysicalRegister(Val)); in from()
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64PBQPRegAlloc.cpp | 165 if (Register::isPhysicalRegister(Rd) || Register::isPhysicalRegister(Ra)) { in addIntraChainConstraint() 167 << Register::isPhysicalRegister(Rd) << '\n'); in addIntraChainConstraint() 169 << Register::isPhysicalRegister(Ra) << '\n'); in addIntraChainConstraint()
|
| /llvm-project-15.0.7/llvm/tools/llvm-reduce/deltas/ |
| H A D | ReduceInstructionsMIR.cpp | 39 if (Register::isPhysicalRegister(Reg)) in getPrevDefOfRCInMBB() 95 if (Register::isPhysicalRegister(Reg)) in extractInstrFromFunction()
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonBlockRanges.cpp | 271 if (Register::isPhysicalRegister(R.Reg)) { in expandToSubRegs() 324 if (Register::isPhysicalRegister(R.Reg) && Reserved[R.Reg]) in computeInitialLiveRanges() 341 if (Register::isPhysicalRegister(S.Reg) && Reserved[S.Reg]) in computeInitialLiveRanges() 377 assert(!Register::isPhysicalRegister(S.Reg) || in computeInitialLiveRanges() 386 assert(!Register::isPhysicalRegister(S.Reg) || in computeInitialLiveRanges()
|
| H A D | RDFCopy.cpp | 48 assert(Register::isPhysicalRegister(DstR.Reg)); in interpretAsCopy() 49 assert(Register::isPhysicalRegister(SrcR.Reg)); in interpretAsCopy()
|
| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsRegisterBankInfo.cpp | 187 !Register::isPhysicalRegister(NonCopyInstr->getOperand(0).getReg())) in addDefUses() 209 !Register::isPhysicalRegister(Ret->getOperand(0).getReg()) && in skipCopiesOutgoing() 223 !Register::isPhysicalRegister(Ret->getOperand(1).getReg())) in skipCopiesIncoming() 363 assert((Register::isPhysicalRegister(CopyInst->getOperand(Op).getReg())) && in setTypesAccordingToPhysicalRegister()
|