| /llvm-project-15.0.7/llvm/utils/TableGen/ |
| H A D | InstrDocsEmitter.cpp | 106 FLAG(isMoveImm) in EmitInstrDocs()
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| H A D | CodeGenInstruction.h | 243 bool isMoveImm : 1; variable
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| H A D | CodeGenInstruction.cpp | 375 isMoveImm = R->getValueAsBit("isMoveImm"); in CodeGenInstruction()
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| H A D | InstrInfoEmitter.cpp | 1134 if (Inst.isMoveImm) OS << "|(1ULL<<MCID::MoveImm)"; in emitRecord()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPseudo.td | 40 let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0,
64 let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in {
278 let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1,
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyInstrInfo.td | 365 let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1 in {
382 } // isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1
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| H A D | WebAssemblyInstrSIMD.td | 457 let isMoveImm = 1, isReMaterializable = 1 in
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | VOP1Instructions.td | 118 let isMoveImm = should_mov_imm in {
201 } // End isMoveImm = 1
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| H A D | SOPInstructions.td | 197 let isMoveImm = 1 in {
207 } // End isMoveImm = 1
822 let isReMaterializable = 1, isMoveImm = 1 in {
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| H A D | VOP3PInstructions.td | 555 let isMoveImm = 1 in {
557 } // End isMoveImm = 1
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| H A D | SIInstructions.td | 122 let isMoveImm = 1;
138 let isMoveImm = 1;
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| H A D | VOPInstructions.td | 16 bit isMoveImm;
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| /llvm-project-15.0.7/llvm/lib/Target/CSKY/ |
| H A D | CSKYInstrFormats.td | 104 let isMoveImm = 1;
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| H A D | CSKYInstrInfo16Instr.td | 171 let isMoveImm = 1;
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMInstrThumb2.td | 2147 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
2171 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2892 let isMoveImm = MoveImm;
3475 let isMoveImm = 1 in
3485 let isMoveImm = 1 in
3494 let isMoveImm = 1 in
3518 let isMoveImm = 1 in
4234 let isReMaterializable = 1, isMoveImm = 1, Size = 8 in
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| H A D | ARMInstrInfo.td | 3628 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3640 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
4243 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
5029 let isMoveImm = 1 in
5039 let isMoveImm = 1 in
5048 let isMoveImm = 1 in
5057 let isMoveImm = 1 in
5969 let isReMaterializable = 1, isMoveImm = 1, Size = 8 in
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| H A D | ARMInstrThumb.td | 1198 let isMoveImm = 1 in
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrFP.td | 38 let isAsCheapAsAMove = 1, isMoveImm = 1 in {
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| H A D | SystemZInstrInfo.td | 432 let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in {
869 let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in
954 let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in {
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| H A D | SystemZInstrVector.td | 58 let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in {
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrP10.td | 616 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
626 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1300 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1, Predicates = [PrefixInstrs] in {
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| H A D | PPCInstrAltivec.td | 833 let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
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| /llvm-project-15.0.7/llvm/lib/Target/ARC/ |
| H A D | ARCInstrInfo.td | 367 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
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| /llvm-project-15.0.7/llvm/lib/Target/VE/ |
| H A D | VEInstrInfo.td | 559 let isMoveImm = MoveImm;
976 let isMoveImm = MoveImm;
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86InstrCompiler.td | 167 let Constraints = "$src = $dst", isMoveImm = 1, isPseudo = 1, Defs = [EFLAGS] in {
293 isPseudo = 1, isMoveImm = 1, AddedComplexity = 10 in
|