| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.h | 803 bool isInlineConstant(const APInt &Imm) const;
805 bool isInlineConstant(const APFloat &Imm) const { in isInlineConstant() function
806 return isInlineConstant(Imm.bitcastToAPInt()); in isInlineConstant()
811 bool isInlineConstant(const MachineOperand &MO, in isInlineConstant() function
813 return isInlineConstant(MO, OpInfo.OperandType); in isInlineConstant()
818 bool isInlineConstant(const MachineInstr &MI, in isInlineConstant() function
827 return isInlineConstant(DefMO, MI.getDesc().OpInfo[OpIdx]); in isInlineConstant()
837 bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx, in isInlineConstant() function
848 return isInlineConstant(MO, OpType); in isInlineConstant()
854 bool isInlineConstant(const MachineOperand &MO) const { in isInlineConstant() function
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| H A D | SIShrinkInstructions.cpp | 144 !TII->isInlineConstant(*Src.getParent(), in isKImmOperand()
150 !TII->isInlineConstant(*Src.getParent(), in isKUImmOperand()
158 return !TII->isInlineConstant(Src); in isKImmOrKUImmOperand()
163 return !TII->isInlineConstant(Src); in isKImmOrKUImmOperand()
173 if (!isInt<32>(Src.getImm()) || TII->isInlineConstant(Src)) in isReverseInlineImm()
364 if (Src2.isImm() && !TII->isInlineConstant(Src2)) { in shrinkMadFma()
392 if (Src1.isImm() && !TII->isInlineConstant(Src1)) in shrinkMadFma()
394 else if (Src0.isImm() && !TII->isInlineConstant(Src0)) in shrinkMadFma()
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| H A D | AMDGPURegBankCombiner.cpp | 226 if ((!MRI.hasOneNonDBGUse(K0->VReg) || TII.isInlineConstant(K0->Value)) && in matchFPMinMaxToMed3()
227 (!MRI.hasOneNonDBGUse(K1->VReg) || TII.isInlineConstant(K1->Value))) { in matchFPMinMaxToMed3()
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| H A D | SIFoldOperands.cpp | 442 !TII->isInlineConstant(*OpToFold, OpInfo)) { in tryAddToFoldList()
502 if (TII->isInlineConstant(*Op, OpTy)) in getRegSeqInit()
534 if (OpToFold.isImm() && TII->isInlineConstant(OpToFold, OpTy) && in tryToFoldACImm()
557 if (DefOp.isImm() && TII->isInlineConstant(DefOp, OpTy) && in tryToFoldACImm()
577 if (!TII->isInlineConstant(*Op, OpTy) || in tryToFoldACImm()
703 TII->isInlineConstant(OpToFold, AMDGPU::OPERAND_REG_INLINE_C_INT32)) { in foldOperand()
762 TII->isInlineConstant(*Def, AMDGPU::OPERAND_REG_INLINE_C_INT32)) { in foldOperand()
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| H A D | GCNVOPDUtils.cpp | 113 if (!TII.isInlineConstant(Comp.MI, 1)) in checkVOPDRegConstraints()
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| H A D | AMDGPUISelDAGToDAG.h | 132 return Subtarget->getInstrInfo()->isInlineConstant(Imm); in isInlineImmediate()
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| H A D | AMDGPUISelDAGToDAG.cpp | 338 return TII->isInlineConstant(-C->getAPIntValue()); in isInlineImmediate()
341 return TII->isInlineConstant(-C->getValueAPF().bitcastToAPInt()); in isInlineImmediate()
345 return TII->isInlineConstant(C->getAPIntValue()); in isInlineImmediate()
348 return TII->isInlineConstant(C->getValueAPF().bitcastToAPInt()); in isInlineImmediate()
1699 !TII->isInlineConstant(APInt(32, COffsetVal & 0xffffffff)) + in SelectGlobalSAddr()
1700 !TII->isInlineConstant(APInt(32, COffsetVal >> 32)); in SelectGlobalSAddr()
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| H A D | SIInstrInfo.cpp | 1919 if (Imm.isIntN(32) || isInlineConstant(Imm)) { in expandPostRAPseudo()
2938 if (!isInlineConstant(Imm)) in FoldImmediate()
2979 if (isInlineConstant(UseMI, *Src0, *ImmOp)) in FoldImmediate()
3047 isInlineConstant(Def->getOperand(1)) && in FoldImmediate()
3065 isInlineConstant(Def->getOperand(1)) && in FoldImmediate()
3318 if (Src0->isImm() && !isInlineConstant(MI, Src0Idx, *Src0)) in convertToThreeAddress()
3585 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const { in isInlineConstant() function in SIInstrInfo
3605 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO, in isInlineConstant() function in SIInstrInfo
3695 return !isInlineConstant(MO, OpInfo); in isLiteralConstantLike()
3735 if (MO.isImm() && isInlineConstant(MO, OpInfo)) { in isImmOperandLegal()
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| H A D | SIFixSGPRCopies.cpp | 758 TII->isInlineConstant(APInt(64, Copied.getImm(), true))) { in runOnMachineFunction()
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| H A D | AMDGPUInstructionSelector.cpp | 2229 if (IsSgpr && TII.isInlineConstant(Imm)) { in selectG_CONSTANT()
4068 !TII.isInlineConstant(APInt(32, ConstOffset & 0xffffffff)) + in selectGlobalSAddr()
4069 !TII.isInlineConstant(APInt(32, ConstOffset >> 32)); in selectGlobalSAddr()
4998 return TII.isInlineConstant(Imm); in isInlineImmediate()
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| H A D | SILoadStoreOptimizer.cpp | 1811 if (TII->isInlineConstant(V)) in createRegOrImm()
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| H A D | SIISelLowering.cpp | 9477 (CRHS->hasOneUse() && !TII->isInlineConstant(CRHS->getAPIntValue()))) { in splitBinaryBitConstantOp()
10436 TII->isInlineConstant(K0->getValueAPF().bitcastToAPInt())) && in performFPMed3ImmCombine()
10438 TII->isInlineConstant(K1->getValueAPF().bitcastToAPInt()))) { in performFPMed3ImmCombine()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 1657 bool isInlineConstant(const MCInst &Inst, unsigned OpIdx) const;
3335 bool AMDGPUAsmParser::isInlineConstant(const MCInst &Inst, in isInlineConstant() function in AMDGPUAsmParser
3404 return !isInlineConstant(Inst, OpIdx); in usesConstantBus()
4146 if (MO.isImm() && !isInlineConstant(Inst, OpIdx)) { in validateSOPLiteral()
4265 if (MO.isImm() && !isInlineConstant(Inst, OpIdx)) { in validateVOPLiteral()
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