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Searched refs:isInConsecutiveRegs (Results 1 – 5 of 5) sorted by relevance

/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetCallingConv.h124 bool isInConsecutiveRegs() const { return IsInConsecutiveRegs; } in isInConsecutiveRegs() function
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetCallingConv.td71 class CCIfConsecutiveRegs<CCAction A> : CCIf<"ArgFlags.isInConsecutiveRegs()", A> {
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp1057 if (Out.Flags.isInConsecutiveRegs()) in LowerCall()
1187 if (In.Flags.isInConsecutiveRegs()) in LowerCall()
1272 if (Out.Flags.isInConsecutiveRegs()) in LowerReturn()
1304 if (In.Flags.isInConsecutiveRegs()) in LowerFormalArguments()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp3885 if (!Flags.isInConsecutiveRegs()) in CalculateStackSlotSize()
3918 if (Flags.isInConsecutiveRegs()) { in CalculateStackSlotAlignment()
4551 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize; in LowerFormalArguments_64SVR4()
6373 } else if (!Flags.isInConsecutiveRegs()) { in LowerCall_64SVR4()
6409 !isLittleEndian && !Flags.isInConsecutiveRegs()) { in LowerCall_64SVR4()
6427 Flags.isInConsecutiveRegs()) ? 4 : 8; in LowerCall_64SVR4()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp5899 !Ins[i].Flags.isInConsecutiveRegs()) in LowerFormalArguments()
5945 if (Ins[i].Flags.isInConsecutiveRegs()) { in LowerFormalArguments()
6683 if (Outs[i].Flags.isInConsecutiveRegs()) { in LowerCall()
6777 !Flags.isInConsecutiveRegs()) { in LowerCall()