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Searched refs:isCtrl (Results 1 – 10 of 10) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp70 if (Pred.isCtrl()) in numberRCValPredInSU()
108 if (Succ.isCtrl()) in numberRCValSuccInSU()
145 if (Succ.isCtrl()) in numberCtrlDepsInSU()
154 if (Pred.isCtrl()) in numberCtrlPredInSU()
270 if (Succ.isCtrl()) in isResourceAvailable()
498 if (Pred.isCtrl() || (Pred.getSUnit()->NumRegDefsLeft == 0)) in scheduledNode()
514 if (!Succ.isCtrl()) in scheduledNode()
H A DScheduleDAGRRList.cpp1063 if (Pred.isCtrl()) in TryUnfoldSU()
1071 if (Succ.isCtrl()) in TryUnfoldSU()
2104 if (Pred.isCtrl()) in HighRegPressure()
2153 if (Pred.isCtrl()) in RegPressureDiff()
2196 if (Pred.isCtrl()) in scheduledNode()
2278 if (Pred.isCtrl()) in unscheduledNode()
2375 if (Pred.isCtrl()) continue; in hasOnlyLiveInOpers()
2397 if (Succ.isCtrl()) continue; in hasOnlyLiveOutUses()
2434 if (Pred.isCtrl()) continue; in initVRegCycle()
3001 if (!Pred.isCtrl()) { in PrescheduleNodesWithMultipleUses()
[all …]
H A DScheduleDAGSDNodes.cpp513 if (!SU.addPred(Dep) && !Dep.isCtrl() && OpSU->NumRegDefsLeft > 1) { in AddSchedEdges()
807 if (Pred.isCtrl()) in EmitPhysRegCopy()
817 if (Succ.isCtrl()) in EmitPhysRegCopy()
H A DScheduleDAGFast.cpp279 if (Pred.isCtrl()) in CopyAndMoveSuccessors()
288 if (Succ.isCtrl()) in CopyAndMoveSuccessors()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DGCNILPSched.cpp65 if (Pred.isCtrl()) continue; // ignore chain preds in CalcNodeSethiUllmanNumber()
109 if (Succ.isCtrl()) continue; // ignore chain succs in closestSucc()
124 if (Pred.isCtrl()) continue; // ignore chain preds in calcMaxScratches()
H A DSIMachineScheduler.cpp1211 SuccDep.isCtrl() ? NoData : Data); in createBlocksForVariant()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DScheduleDAG.h161 bool isCtrl() const { in isCtrl() function
657 return getSDep().isCtrl(); in isCtrlDep()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp69 if (SU->Preds[i].isCtrl()) in isBCTRAfterSet()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DVLIWMachineScheduler.cpp94 if (S.isCtrl()) in hasDependence()
H A DMachineScheduler.cpp1721 if ((Pred.isCtrl() && in groupMemOps()